EDA程序

1、分频器的设计 奇数y分频:(式中y为我们所要分频的数,而x取只要小于y就行,尽量取中间点的值) module jifenpin(clk,q,reset); input clk,reset; output q; reg[3:0] i; reg q; always@(posedge clk) if(!reset) begin q<=1; i<=0; end else if(i==x) begin q<=~q; i<=i+1; end else if(i==y) begin q<=~q; i<=0; end else i<=i+1; endmodule 偶数n分频 module erfenpin (q,clk,reset); input reset,clk; output q; reg q; reg [4:0]i; always @ (posedge clk ) if(!reset) begin q<=1'b1; i<=0; end else if(i==n/2) begin q<=~q; i<=0; end else i<=i+1; endmodule 2、频率计 module pinlvji(clk,fin,en,reset,load,reg32b); input clk,fin; output en,reset,load,reg32b; reg en; reg[5:0] i,j,reg32b; always @(posedge clk) en<=~en; assign reset=~(en|clk); assign load=~en; always @(posedge fin) begin if(reset) i=0; else if(en) i=i+1; j=i; end always @(posedge load) if(en==0) reg32b=j; endmodule 3、交通灯(状态机) module jiaotongdeng(clk,reset,sensor1,sensor2,red1,red2,yellow1 ,yellow2,green1,green2); input clk,reset,sensor1; input [2:0]sensor2; output red1,red2,yellow1,yellow2,green1,green2; reg red1,red2,yellow1,yellow2,green1,green2; reg [2:0]state; always @(posedge clk) if(!reset) begin state<=1; red1<=0; red2<=0; yellow1<=0; yellow2<=0; green1<=0; green2<=0; end else case(state) 0:begin if(sensor1==0) begin state<=1; green1<=1; red2<=1; end end 1:begin if(sensor1==0&&sensor2[2]==1) begin state<=2; red2<=1; yellow1<=1; end else if(sensor1==1) begin red1<=1; red2<=1; state<=0; end else state=1; end 2:begin if(sensor1==0&&sensor2[1]==1) begin state<=3; red1<=1; green2<=1; end else if(sensor1==1) begin red1=1; red2=1; state<=0; end else state=2; end 3:begin if(sensor1==0&&sensor2[0]==1) begin state<=4; red1<=1; yellow2<=1; end else if(sensor1==1) begin red1=1; red2=1; state<=0; end else state=3; end 4:begin if(sensor1==0&&sensor2[1]==1) begin state<=1; red2<=1; green1<=1; end else if(sensor1==1) begin red1=1; red2=1; state<=0; end else state=4; end endcase endmodule 4、数字时钟 module shizhong(clk,s,m,h); input clk; output[5:0] s,m,h; reg[5:0] s,m,h; reg mt,ht; wire mtclk,htclk; always@(posedge clk) begin if(s==59) begin s<=0; mt<=1; end else begin s<=s+1; mt<=0; end end assign mtclk=mt; always@(posedge mtclk) begin if(m==59) begin m<=0; ht<=1; end else begin m<=m+1; ht<=0; end end assign htclk=ht; always@(posedge htclk) begin if(h==23) h<=0; else h<=h+1; end endmodule 5、组合逻辑(数字时钟) module digit_clock(s,m,h,clk,clr,en); output [7:0] s,m; output [7:0] h; input clk,clr,en; wire clk,clr,en; wire[7:0] s,m,h; wire count_s,count_m,count_h; count_60 u0(s[7:4],s[3:0],count_s,clk,clr,en); count_60 u1(m[7:4],m[3:0],count_m,clk,clr,count_s); count_24 u2(h[7:4],h[3:0],count_h,clk,clr,count_m); endmodule