ARRIA V SCHEMATIC REVIEW WORKSHEET - FPGA CPLD …ARRIA V SCHEMATIC REVIEW WORKSHEET - FPGA CPLD …
Arria? V GX, GT, SX, and ST Device Schematic Review Worksheet
This document is intended to help you review your schematic and compare the pin usage against the Arria V Device Family Pin Connection
Guidelines (P...
ARRIA V SCHEMATIC REVIEW WORKSHEET - FPGA CPLD …
Arria? V GX, GT, SX, and ST Device Schematic Review Worksheet
This document is intended to help you review your schematic and compare the pin usage against the Arria V Device Family Pin Connection
Guidelines (PDF) version 1.9 and other referenced literature for this device family. The technical content is divided into focus areas such as FPGA
power supplies, transceiver power supplies and pin usage, configuration, and FPGA I/O, and external memory interfaces.
Within each focus area, there is a table that contains the voltage or pin name for all of the dedicated and dual purpose pins for the device family.
In some cases, the device density and package combination may not include some of the pins shown in this worksheet, you should cross
reference with the pin-out file for your specific device. Links to the device pin-out files are provided at the top of each section.
Before you begin using this worksheet to review your schematic and commit to board layout, Altera highly recommends:
1) Review the latest version of the Errata Sheet and Guidelines for Arria V ES Devices (PDF), Errata Sheet for Arria V Devices (PDF), and the
Knowledge Database for Arria V Device Known Issues and Arria V Device Handbook Known Issues.
2) Compile your design in the Quartus? II software to completion.
For example, there are many I/O related placement restrictions and VCCIO requirements for the I/O standards used in the device. If you do not
have a complete project, then at a minimum a top level project should be used with all I/O pins defined, placed, and apply all of the configurable
options that you plan to use. All I/O related megafunctions should also be included in the minimal project, including, but not limited to, external
memory interfaces, transceiver IP, PLLs, altlvds, and altddio. The I/O Analysis tool in the Pin Planner can then be used on the minimal project to
validate the pinout in the Quartus II software to assure there are no conflicts with the device rules and guidelines.
When using the I/O Analysis tool you must ensure there are no errors with your pinout. Additionally, you should check all warning and critical
warning messages to evaluate their impact on your design. You can right click your mouse over any warning or critical warning message and
select “Help”. This will bring open a new Help window with further information on the cause of the warning, and the action that is required.
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 1 of 131 DS-01028-4.0
For example, the following warning is generated when a PLL is driven by a global network where the source is a valid dedicated clock input pin, but the pin is not one dedicated to the particular PLL:
Warning: PLL "" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
Info: Input port INCLK[0] of node "" is driven by clock~clkctrl which is OUTCLK output port of Clock Control Block type node clock~clkctrl
The help file provides the following:
CAUSE: The specified PLL's input clock is not driven by a dedicated input pin. As a result, the input clock delay will not be fully compensated
by the PLL. Additionally, jitter performance depends on the switching rate of other design elements. This can also occur if a global
signal assignment is applied to the clock input pin, which forces the clock to use the non-dedicated global clock network. ACTION: If you want compensation of the specified input clock or better jitter performance, connect the input clock only to an input pin, or
assign the input pin only to a dedicated input clock location for the PLL. If you do not want compensation of the specified input clock,
then set the PLL to No Compensation mode.
When assigning the input pin to the proper dedicated clock pin location, refer to Clock Networks and PLLs in Arria V Devices (PDF) for the proper port mapping of dedicated clock input pins to PLLs.
There are many reports available for use after a successful compilation or I/O analysis. For example, you can use the “All Package Pins” and “I/O Bank Usage” reports within the Compilation – Fitter – Resource Section to see all of the I/O standards and I/O configurable options that are
assigned to all of the pins in your design, as well as view the required VCCIO for each I/O bank. These reports must match your schematic pin connections.
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The review table has the following heading:
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
The first column (Plane/Signal) lists the FPGA voltage or signal pin name. You should only edit this column to remove dedicated or dual purpose pin names that are not available for your device density and package option.
The second column (Schematic Name) is for you to enter your schematic name(s) for the signal(s) or plane connected to the FPGA pin(s).
The third column (Connection Guidelines) should be considered “read only” as this contains Altera’s recommended connection guidelines for the voltage plane or signal.
The fourth column (Comments/Issues) is an area provided as a “notepad” for you to comment on any deviations from the connection guidelines,
and to verify guidelines are met. In many cases there are notes that provide further information and detail that compliment the connection guidelines.
Here is an example of how the worksheet can be used:
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
provided by Altera> +1.1V Altera> Connected to +1.1V plane, no isolation VCC is necessary.
Missing low and medium range
decoupling, check PDN.
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Legal Note:
PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THIS SCHEMATIC REVIEW WORKSHEET (“WORKSHEET”) PROVIDED TO YOU. BY USING THIS WORKSHEET, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND
CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION OR ITS APPLICABLE SUBSIDIARIES ("ALTERA").
1. Subject to the terms and conditions of this Agreement, Altera grants to you, for no additional fee, a non-exclusive and non-transferable right to
use this Worksheet for the sole purpose of verifying the validity of the pin connections of an Altera programmable logic device-based design. You
may not use this Worksheet for any other purpose. There are no implied licenses granted under this Agreement, and all rights, except for those
granted under this Agreement, remain with Altera.
2. Altera does not guarantee or imply the reliability, or serviceability, of this Worksheet or other items provided as part of this Worksheet. This
Worksheet is provided 'AS IS'. ALTERA DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT. ALTERA HAS NO OBLIGATION TO PROVIDE YOU WITH ANY SUPPORT OR MAINTENANCE.
3. In no event shall the aggregate liability of Altera relating to this Agreement or the subject matter hereof under any legal theory (whether in tort,
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consequential, indirect, or special damages caused by your use of this Worksheet even if advised of the possibility of such damages.
4. This Agreement may be terminated by either party for any reason at any time upon 30-days’ prior written notice. This Agreement shall be governed by the laws of the State of California, without regard to conflict of law or choice of law principles. You agree to submit to the exclusive
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Agreement. The parties hereby agree that the party who is not the substantially prevailing party with respect to a dispute, claim, or controversy
relating to this Agreement shall pay the costs actually incurred by the substantially prevailing party in relation to such dispute, claim, or controversy,
including attorneys' fees. Failure to enforce any term or condition of this Agreement shall not be deemed a waiver of the right to later enforce such
term or condition or any other term or condition of the Agreement.
BY USING THIS WORKSHEET, YOU ACKNOWLEDGE THAT YOU HAVE READ THIS AGREEMENT, UNDERSTAND IT, AND AGREE TO BE BOUND BY ITS TERMS AND CONDITIONS. YOU AND ALTERA FURTHER AGREE THAT IT IS THE COMPLETE AND EXCLUSIVE STATEMENT OF THE AGREEMENT BETWEEN YOU AND ALTERA, WHICH SUPERSEDES ANY PROPOSAL OR PRIOR AGREEMENT, ORAL OR WRITTEN, AND ANY OTHER COMMUNICATIONS BETWEEN YOU AND ALTERA RELATING TO THE SUBJECT MATTER OF THIS AGREEMENT.
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 4 of 131 DS-01028-4.0
Index
Section I: Power
Section II: Configuration
Section III: Transceiver
Section IV: I/O
a: Clock Pins
b: Dedicated and Dual Purpose Pins
c: Dual Purpose Differential I/O pins
d: HPS I/O
Section V: External Memory Interface Pins
a: DDR3/DDR3L Interface Pins
b: DDR3/DDR3L Termination Guidelines
c: DDR2 Interface Pins
DDR2 Termination Guidelines d:
e: LPDDR2 Interface Pins
f: LPDDR2 Termination Guidelines
g: QDRII/+ Interface pins
h: QDRII/+ Termination Guidelines Section VI: Document Revision History
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Section I: Power
Documentation: Arria V Devices
Arria V Device Pin-Out Files
Arria V Device Family Pin Connection Guidelines (PDF)
Arria V Early Power Estimator
Arria V Early Power Estimator User Guide (PDF)
Power Delivery Network (PDN) Tool For Arria V Devices
Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
PowerPlay Power Analyzer Support Resources
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Errata Sheet and Guidelines for Arria V ES Devices (PDF)
Errata Sheet for Arria V Devices (PDF)
Known Arria V Issues
Index
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCC For Arria V GX -C4, -C5, -I5, and -C6 and Arria V GT Verify Guidelines have been met or list
-I5 devices: required actions for compliance.
Connect all VCC pins to a 1.1V low noise switching
regulator. See Notes (1-1) (1-2) (1-3) (1-4) (1-5).
For Arria V GX -I3 and GT -I3 devices:
Connect all VCC pins to a 1.15V low noise switching
regulator.
VCC may be sourced from the same regulator as
VCCP with a proper isolation filter.
Use the Arria V Early Power Estimator to determine
the current requirements for VCC and other supplies.
Decoupling for these pins depends on the design
decoupling requirements of the specific board.
VCCP For Arria V GX -C4, -C5, -I5, and -C6 and Arria V GT Verify Guidelines have been met or list
-I5 devices: required actions for compliance.
Connect all VCCP pins to a 1.1V low noise switching
regulator. See Notes (1-1) (1-2) (1-3) (1-4) (1-5).
For Arria V GX -I3 and GT –I3 devices:
Connect all VCCP pins to a 1.15V low noise
switching regulator.
VCCP may be sourced from the same regulator as
VCC with a proper isolation filter. Separate VCC and
VCCP planes into two different power layers on the
PCB.
Decoupling for these pins depends on the design
decoupling requirements of the specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCC_HPS Power supply for the HPS core. Verify Guidelines have been met or list
required actions for compliance. (Arria V SoC device For Arria V SX and ST devices except Arria V SX
variants only) and ST –I3 devices, connect all VCC_HPS pins to a See Notes (1-1) (1-2) (1-3) (1-4) (1-5).
1.1V low noise switching regulator.
for Arria V SX and ST –I3 devices, connect all
VCC_HPS pins to a 1.15V low noise switching
regulator.
If powering down of the FPGA fabric is not required,
VCC_HPS pins may be sourced from the same
regulator as VCC with a proper isolation filter.
Use the Arria V Early Power Estimator to determine
the current requirements for VCC_HPS and other
supplies.
Decoupling for these pins depends on the design
decoupling requirements of the specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCIO[3,4,7,8] Connect these pin to 1.2V, 1.25V, 1.35V, Verify Guidelines have been met or list
[A,B,C,D] 1.5V, 1.8V, 2.5V, 3.0V, or 3.3V supplies, required actions for compliance.
depending on the I/O standard connected to
(not all pins are the specified bank. See Notes (1-1) (1-2) (1-5). available in each
device / package When these pins require the same voltage combination) level as VCCPD and / or VCCPGM, they may
be tied to the same regulator as VCCPD and /
or VCCPGM.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCIO[6,7][A,B]_HPS, Connect these pin to 1.2V, 1.5V, 1.8V, 2.5V, Verify Guidelines have been met or list
VCCIO7[C,D,E]_HPS 3.0V, or 3.3V supplies, depending on the I/O required actions for compliance.
standard connected to the specified bank.
(Arria V SoC device See Notes (1-1) (1-2) (1-5). variants only) When these pins require the same voltage
level as VCCPD_HPS and / or
(not all pins are VCCRSTCLK_HPS, they may be tied to the available in each same regulator.
device / package
combination) If powering down of the FPGA fabric is not
required and if these pins have the same
voltage requirement as VCCIO, VCCIO_HPS
pins may be sourced from the same regulator
as VCCIO.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCPD3 The VCCPD pins require 2.5V, 3.0V, or 3.3V. Verify Guidelines have been met or list
VCCPD4A required actions for compliance. VCCPD4[BCD] VCCPD voltage connection depends on the
VCCPD7A VCCIO voltage of the bank. See Notes (1-1) (1-2) (1-5). VCCPD7[BCD]
VCCPD8 VCCPD is 3.3V for 3.3V VCCIO.
(not all pins are VCCPD is 3.0V for 3.0V VCCIO.
available in each
device / package VCCPD is 2.5V for
combination) 2.5V/1.8V/1.5V/1.35V/1.25V/1.2V VCCIO.
When these pins require the same voltage
level as VCCIO and / or VCCPGM, they may
be tied to the same regulator as VCCIO and /
or VCCPGM.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCPD6A6B_HPS The VCCPD pins require 2.5V, 3.0V, or 3.3V. Verify Guidelines have been met or list
VCCPD7[A,B,C,D,E]_ required actions for compliance. HPS When these pins have the same voltage
(1-5). requirements as VCCRSTCLK_HPS and See Notes (1-1) (1-2)
(Arria V SoC device VCCIO_HPS, they may be tied to the same variants only) regulator.
(not all pins are If powering down of the FPGA fabric is not available in each required and if these pins have the same device / package voltage requirement as VCCPD, VCCIO, and combination) VCCPGM, they may be tied to the same
regulator.
VCCPD voltage connection depends on the
VCCIO voltage of the bank.
VCCPD_HPS is 3.3V for 3.3V VCCIO_HPS.
VCCPD_HPS is 3.0V for 3.0V VCCIO_HPS.
VCCPD_HPS is 2.5V for 2.5V/1.8V/1.5V/1.2V
VCCIO_HPS.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCPGM Connect these pins to either 1.8V, 2.5V, 3.0V, Verify Guidelines have been met or list
or 3.3V. required actions for compliance.
When these pins require the same voltage See Notes (1-1) (1-2) (1-5).
level as VCCIO and / or VCCPD, they may be
tied to the same regulator as VCCIO and / or
VCCPD.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VREF[3,4,7,8] These are dual purpose pins. When used for Verify Guidelines have been met or list
[A,B,C,D]N0 their dedicated function, they are the input required actions for compliance.
reference voltage for each I/O bank. If a bank
(not all pins are uses a voltage referenced I/O standard, then See Note (1-1).
available in each these pins are used as the voltage-reference
device / package pins for the I/O bank.
combination)
When not used as a voltage reference input,
these pins can be used as I/O pins. When
used as I/O pins, they have higher
capacitance than regular I/O pins which will
slow the edge rates and affect I/O timing.
Avoid placing fast edge rate signals such as
clocks on these pins, and avoid using these
pins in buses since the I/O timing will not be
consistent with the rest of the bus.
If VREF pins are not used for their dedicated
function or as regular I/O pins, you should
connect them to either the VCCIO in the bank
where the pin resides or GND.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VREFB6[A,B]N0_HPS, Input reference voltage for each I/O bank. If a Verify Guidelines have been met or list
VREFB7A7B7C7D7Ebank uses a voltage referenced I/O standard required actions for compliance. N0_HPS for input operation, then these pins are used
as the voltage-reference pins for the bank. See Note (1-1). (Arria V SoC device
variants only) If the VREF pins are not used, you should
connect them to either the VCCIO in the bank (not all pins are in which the pin resides or GND.
available in each
device / package Decoupling for these pins depends on the combination) design decoupling requirements of the
specific board.
VCCRSTCLK_HPS VCCRSTCLK_HPS supplies power to HPS Verify Guidelines have been met or list
clock and reset pins. required actions for compliance. (Arria V SoC device
variants only) Connect these pins to either a 1.8V, 2.5V, See Notes (1-1) (1-2) (1-3) (1-5).
3.0V, or 3.3V power supply. When these pins
have the same voltage requirements as
VCCIO_HPS and VCCPD_HPS, they may be
tied to the same regulator.
If powering down of the FPGA fabric is not
required and if these pins have the same
voltage requirement as VCCIO, VCCPGM,
and VCCPD, they may be tied to the same
regulator.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCD_FPLL Connect all VCCD_FPLL pins to a 1.5V linear Verify Guidelines have been met or list
or low noise switching power supply. These required actions for compliance.
pins may be tied to the same regulator as
VCCBAT and VCCH_GXB. See Notes (1-1) (1-2) (1-3) (1-5).
These supplies may share power planes
across multiple Arria V devices.
If any PLLs are used in the device, you must
ensure the proper RREF_BR and RREF_TL
pins are connected to their own individual 2.0-
kΩ +/- 1% resistor to GND (see transceiver
section of this review for details).
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
VCCA_FPLL Connect these pins to a 2.5V low noise Verify Guidelines have been met or list
switching power supply through a proper required actions for compliance.
isolation filter.
See Notes (1-1) (1-2) (1-3) (1-5).
This power rail may be shared with VCCAUX
and VCCA_GXB. With a proper isolation filter
these pins may be sourced from the same
regulator as VCCIO, VCCPD, and VCCPGM
when each of these supplies require 2.5V.
This supply may share power planes across
multiple Arria V devices.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCPLL_HPS VCCPLL_HPS supplies power to the HPS Verify Guidelines have been met or list
core PLLs. required actions for compliance. (Arria V SoC device
variants only) Connect these pins to a 2.5V low noise See Notes (1-1) (1-2) (1-3) (1-5).
switching power supply through a proper
isolation filter.
This power rail may be shared with the
VCC_AUX_SHARED pin.
If powering down of the FPGA fabric is not
required and with a proper isolation filter,
these pins may be sourced from the same
regulator as VCCIO, VCCPD, VCCPGM,
VCCIO_HPS, VCCPD_HPS, and
VCCRSTCLK_HPS when each of these
power supplies require 2.5V.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCC_AUX Connect all VCC_AUX pins to a 2.5V low Verify Guidelines have been met or list
noise switching power supply through a required actions for compliance.
proper isolation filter.
See Notes (1-1) (1-2) (1-3) (1-5).
For Arria V GX and GT devices, this power
rail may be shared with VCCA_FPLL and
VCCA_GXB. With a proper isolation filter
these pins may be sourced from the same
regulator as VCCIO, VCCPD, and VCCPGM
when each of these power supplies require
2.5V.
For Arria V SX and ST device, VCC_AUX
must always be powered up for the PLL
operation and if powering down the FPGA
fabric is not required, this power rail may be
shared with VCC_AUX_SHARED,
VCCA_GXB, and VCCA_FPLL. With a proper
isolation filter these pins may be sourced from
the same regulator as VCCIO, VCCIO_HPS,
VCCPD, VCCPD_HPS, VCCPGM, and
VCCRSTCLK_HPS when each of these
power supplies require 2.5V.
These supplies may share power planes
across multiple Arria V devices.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCC_AUX_SHARED VCC_AUX_SHARED must always be Verify Guidelines have been met or list
powered up at 2.5V for the HPS operation. required actions for compliance. (Arria V SoC device
(1-5). variants only) This pin may be tied together to the same See Notes (1-1) (1-2) (1-3)
regulator as VCCPLL_HPS.
If powering down of the FPGA fabric is not
required, this power rail may be shared with
VCC_AUX, VCCA_GXB, and VCCA_FPLL
pins. Connect this pin to VCC_AUX using a
proper isolation filter.
With a proper isolation filter, these pins may
be sourced from the same regulator as
VCCIO, VCCIO_HPS, VCCPD, VCCPD_HPS,
VCCPGM and VCCRSTCLK_HPS when each
of these power supplies requires 2.5V.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
Index Top of Section
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCBAT Connect this pin to a non-volatile battery Verify Guidelines have been met or list
power source in the range of 1.2V – 3.0V required actions for compliance.
when using the design security volatile key. In
this case, do not connect this pin to a volatile
power source on the board. 3.0V is the
typical power selected for this supply.
When not using the volatile key, tie this to a
1.5V, 2.5V, or 3.0V supply.
Arria V devices will not exit POR if VCCBAT
stays at logic low.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
GND All GND pins must be connected to the board Verify Guidelines have been met or list
ground plane. required actions for compliance.
See Notes (1-1) (1-2).
Index Top of Section
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Notes:
1-1. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required and impedance of power path required based on static and switching current values. Refer to Altera’s Power Delivery Network (PDN) Tool for Arria V Devices for further information.
Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
1-2. This worksheet does not include power estimation for the different power supplies provided. Ensure each power supply is adequate for the device current requirements. Refer to Altera’s Early Power Estimation Tools and PowerPlay Power Analyzer Support Resources for further guidance.
Use Altera’s Early Power Estimation Tools to ensure the junction temperature of the device is within operating specifications based on your design
activity.
1-3. Low Noise Switching Regulator is defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has a fast transient response. The switching frequency range is not an Altera requirement. However, Altera does require the Line Regulation and Load Regulation meet the following requirements:
, Line Regulation < 0.4%.
, Load Regulation < 1.2%
1-4. Power pins should not share breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via. VCC must not share breakout vias.
1-5. These supplies may share power planes across multiple Arria V devices.
Index Top of Section
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Reviewed against Errata Sheet for Arria V Devices (PDF) version:
Additional Comments:
Index Top of Section
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Section II: Configuration
Arria V Recommended Reference Literature/Tool List
Arria V Pin-Out Files
Arria V Device Family Pin Connection Guidelines (PDF)
Configuration, Design Security, and Remote System Upgrades in Arria V Devices (PDF)
JTAG Boundary-Scan Testing in Arria V Devices (PDF)
USB-Blaster Download Cable User Guide (PDF)
ByteBlaster II Download Cable User Guide (PDF)
EthernetBlaster II Communications Cable User Guide (PDF)
AN 597: Getting Started Flow for Board Designs (PDF)
Errata Sheet and Guidelines for Arria V ES Devices (PDF)
Errata Sheet for Arria V Devices (PDF)
Index
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 23 of 131
DS-01028-4.0
Configuration Scheme Configuration Voltage
Plane/Signal Schematic Name Connection Guidelines Comments / Issues MSEL[0:4] These pins are internally connected through a Verify Guidelines have been met or list
25-kΩ resistor to GND. Do not leave these required actions for compliance.
pins floating.
When these pins are unused connect them to
GND.
Depending on the configuration scheme used
these pins should be tied to VCCPGM or
GND. Refer to Configuration, Design Security,
and Remote System Upgrades in Arria V
Devices (PDF) for the configuration scheme
options.
If only JTAG configuration is used, connect
these pins to ground.
nCE Dedicated active-low chip enable. When nCE Verify Guidelines have been met or list
is low, the device is enabled. When nCE is required actions for compliance.
high, the device is disabled.
In multi-device configuration, nCE of the first
device is tied low while its nCEO pin drives
the nCE of the next device in the chain. In
single device configuration and JTAG
programming, nCE should be connected to
GND or through a 10-kΩ pull-down to GND if
using an Active Serial header.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 24 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues nCONFIG Dedicated configuration control input. Pulling Verify Guidelines have been met or list
this pin low during user-mode will cause the required actions for compliance.
FPGA to lose its configuration data, enter a
reset state, and tri-state all I/O pins. Returning
this pin to a logic high level will initiate
reconfiguration.
nCONFIG should be connected directly to the
configuration controller when the FPGA uses
a passive configuration scheme, or through a
10-kΩ resistor tied to VCCPGM when using
an active serial configuration scheme.
If this pin is not used, it requires a connection
directly or through a 10-kΩ resistor to
VCCPGM.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 25 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues CONF_DONE This is a dedicated configuration done pin. As Verify Guidelines have been met or list
a status output, the CONF_DONE pin drives required actions for compliance.
low before and during configuration. Once all
configuration data is received without error
and the initialization cycle starts,
CONF_DONE is released. As a status input,
CONF_DONE goes high after all data is
received. Then the device initializes and
enters user mode.
It is not available as a user I/O pin.
If internal pull-up resistors on the configuration
controller are used, external 10-kΩ pull-up
resistors should not be used on this pin.
Otherwise, use an external 10-kΩ pull-up
resistor to VCCPGM should be used.
When using passive configuration schemes
this pin should also be monitored by the
configuration controller.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 26 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues nCEO During multi-device configuration, this pin Verify Guidelines have been met or list
feeds the nCE pin of a subsequent device. required actions for compliance.
Connect this pin to an external 10-kΩ pull-up
resistor to VCCPGM. During single device
configuration, this pin may be left floating.
This pin is not available for regular I/O usage
in multi-device configuration mode, see
rd04132011_29.
nSTATUS This is a dedicated configuration status pin. Verify Guidelines have been met or list
The FPGA drives nSTATUS low immediately required actions for compliance.
after power-up and releases it after POR time.
As a status output, the nSTATUS is pulled low
if an error occurs during configuration. As a
status input, the device enters an error state
when nSTATUS is driven low by an external
source during configuration or initialization. It
is not available as a user I/O pin.
When using Passive configuration schemes
this pin should also be monitored by the
configuration controller.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 27 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues TCK Connect this pin to a 1-kΩ pull-down resistor Verify Guidelines have been met or list
to GND. This pin has an internal 25-kΩ pull-required actions for compliance.
down.
Treat this signal like a clock and follow typical
clock routing guidelines.
TMS Connect this pin to a 1-kΩ - 10-kΩ pull-up Verify Guidelines have been met or list
resistor to VCCPD. required actions for compliance.
To disable the JTAG circuitry connect TMS to
VCCPD via a 1-kΩ resistor. This pin has an
internal 25-kΩ pull-up.
TDI Connect this pin to a 1-kΩ - 10-kΩ pull-up Verify Guidelines have been met or list
resistor to VCCPD. required actions for compliance.
To disable the JTAG circuitry connect TDI to
VCCPD via a 1-kΩ resistor. This pin has an
internal 25-kΩ pull-up.
TDO The JTAG circuitry can be disabled by leaving Verify Guidelines have been met or list
TDO unconnected. required actions for compliance.
In cases where TDO uses VCCPD = 2.5 V to
drive a 3.3V JTAG interface, there may be
leakage current in the TDI input buffer of the
interfacing devices. An external pull-up
resistor tied to 3.3 V on their TDI pin may be
used to eliminate the leakage current if
needed.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 28 of 131
DS-01028-4.0
Optional Dual Purpose
Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues DCLK Dedicated configuration clock pin. In PS and Verify Guidelines have been met or
FPP configuration, DCLK is used to clock list required actions for compliance.
configuration data from an external source
into the FPGA. In AS mode, DCLK is an
output from the FPGA that provides timing for
the configuration interface.
Do not leave this pin floating. Drive this pin
either high or low.
DCLK can be configured to be a user I/O pin
after configuration when the configuration
mode is an Active mode.
CRC_ERROR This pin is optional and is used when the Verify Guidelines have been met or
CRC error detection circuit is enabled. list required actions for compliance.
When using as optionally open-drain output
dedicated CRC_ERROR pin, connect this pin
to an external 10-kΩ pull-up resistor to
VCCPGM.
When not using as the dedicated
CRC_ERROR pin, and when not using as a
user I/O, connect this pin as defined in the
Quartus II software.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 29 of 131
DS-01028-4.0
External Memory
Interface Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues AS_DATA0 / ASDO / Dedicated AS configuration pin. When using Verify Guidelines have been met or DATA[0] an EPCS device (x1 mode) this is the ASDO list required actions for compliance.
pin and used to send address and control
signals between the FPGA and the
EPCS/EPCQ. Used as DATA[0] for FPP and
PS modes.
When not programming the device in AS
mode ASDO is not used. Also, when this pin
is not used it is recommended to leave the pin
unconnected.
AS_DATA[1:3] / Dedicated AS configuration data pins. Verify Guidelines have been met or DATA[1:3] Configuration data is transported on these list required actions for compliance.
pins when connected to the EPCQ devices.
Used as DATA[1:3 for FPP mode.
When this pin is not used it is recommended
to leave the pin unconnected.
nCSO / DATA[4] Dedicated output control signal from the Verify Guidelines have been met or
FPGA to the serial configuration device in AS list required actions for compliance.
mode that enables the configuration device.
When not programming the device in AS
mode nCSO is not used. Also, when this pin is
not used as an output then it is recommended
to leave the pin unconnected.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 30 of 131
DS-01028-4.0
Partial Reconfiguration
Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues PR_REQUEST Partial Reconfiguration Request pin. Drive this Verify Guidelines have been met or
pin high to start partial reconfiguration. Drive list required actions for compliance.
this pin low to end reconfiguration. This pin
can only be used in Partial Reconfiguration
using external host mode in FPP x16
configuration scheme.
When the dedicated input PR_REQUEST is
not used and this pin is not used as an I/O,
then it is recommended to tie this pin to GND.
PR_READY When using as optionally open-drain output Verify Guidelines have been met or
dedicated PR_READY pin, connect this pin to list required actions for compliance.
an external 10-kΩ pull-up resistor to
VCCPGM. When not using as the dedicated
PR_READY optionally open-drain output, and
when this pin is not used as an I/O pin, then
connect this pin as defined in the Quartus II
software.
PR_ERROR When using as optionally open-drain output Verify Guidelines have been met or
dedicated PR_ERROR pin, connect this pin to list required actions for compliance.
an external 10-kΩ pull-up resistor to
VCCPGM. When not using as the dedicated
PR_ERROR optionally open-drain output, and
when this pin is not used as an I/O pin, then
connect this pin as defined in the Quartus II
software.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 31 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues PR_DONE When using as optionally open-drain output Verify Guidelines have been met or
dedicated PR_DONE pin, connect this pin to list required actions for compliance.
an external 10-kΩ pull-up resistor to
VCCPGM.
When not using as the dedicated PR_DONE
optionally open-drain output, and when this
pin is not used as an I/O pin, then connect this
pin as defined in the Quartus II software.
CvP_CONFDONE When using as optionally open-drain output Verify Guidelines have been met or
dedicated CvP_CONFDONE pin, connect this list required actions for compliance.
pin to an external 10-kΩ pullup resistor to
VCCPGM.
When not using as the dedicated
CvP_CONFDONE optionally open-drain
output, and when this pin is not used as an
I/O pin, then connect this pin as defined in the
Quartus II software.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 32 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues DEV_CLRn This pin is optional and allows you to override Verify Guidelines have been met or
all clears on all device registers. When the list required actions for compliance.
dedicated input DEV_CLRn is not used and
this pin is not used as an I/O then it is
recommended to tie this pin to ground.
DEV_OE This pin is optional and allows you to override Verify Guidelines have been met or
all tri-states on the device. When the list required actions for compliance.
dedicated input DEV_OE is not used and this
pin is not used as an I/O then it is
recommended to tie this pin to ground.
DATA[5:15] Dual-purpose configuration input data pins Verify Guidelines have been met or
and user I/O pins after configuration. list required actions for compliance.
For FPP x8 use DATA[5:7]
For FPP x16 use DATA[5:15]
When the dedicated inputs for DATA[5:15] are
not used and these pins are not used as an
I/O then it is recommended to leave these
pins unconnected.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 33 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues INIT_DONE This is a dual-purpose pin and can be used as Verify Guidelines have been met or list
an I/O pin when not enabled as INIT_DONE. required actions for compliance.
When using as optionally open-drain output
dedicated INIT_DONE pin, a transition from
low to high at the pin indicates when the
device has entered user mode. The
INIT_DONE pin cannot be used as a user I/O
pin after configuration. Connect this pin to an
external 10-kΩ pull-up resistor to VCCPGM.
When not using as the dedicated INIT_DONE
pin, and when this pin is not used as an I/O
pin, then connect this pin as defined in the
Quartus II software.
CLKUSR Optional user-supplied clock input which Verify Guidelines have been met or list
synchronizes the initialization of one or more required actions for compliance.
devices. If not enabled as user-supplied
configuration clock, it can be used as a user
I/O pin.
If the CLKUSR pin is not used as a
configuration clock input and the pin is not
used as an I/O then it is recommended to
connect this pin to ground. Set this pin “as
output driving ground” in the Quartus II
software using the “Reserve Pins”
assignment.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 34 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues JTAG Header Power the EthernetBlaster II, ByteBlaster II or Verify Guidelines have been met or list
USB-Blaster cable’s VCC (pin 4 of the required actions for compliance.
header) with VCCPD.
For multi-device JTAG chains with different
VCCIO voltages, voltage translators may be
required to meet the I/O voltages for the
devices in the chain and JTAG header.
The EthernetBlaster II, ByteBlaster II and
USB-Blaster cables do not support a target
supply voltage of 1.2 V. For the target supply
voltage value, refer to the EthernetBlaster II
Communications Cable User Guide,
ByteBlaster II Download Cable User Guide
and the USB-Blaster Download Cable User
Guide.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 35 of 131
DS-01028-4.0
HPS Configuration and JTAG Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
BOOTSEL[2:0] During a cold reset this signal is sampled as a boot Verify Guidelines have been met or list
select input. required actions for compliance. (Arria V SoC device
variants only) Connect a pull-up or pull-down resistor such as 4.7-kΩ
- 10-kΩ to select the desired boot select values. This
resistor will not interfere with the slow speed interface
signals that could share this pin.
Refer to table A-1 in Booting and Configuration (PDF)
for BSEL values.
Ensure the selected boot device is present on the
schematic.
CLKSEL[1:0] During a cold reset this signal is sampled as a clock Verify Guidelines have been met or list
select input. required actions for compliance. (Arria V SoC device
variants only) Connect a pull-up or pull-down resistor such as 4.7-kΩ
- 10-kΩ to select the desired clock select values. This
resistor will not interfere with the slow speed interface
signals that could share this pin.
Refer to the appropriate CSEL table in Booting and
Configuration (PDF) for Clock Select values.
NAND: Table A-4
SD/MMC: Table A-8
QSPI: Table A-10
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 36 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
HPS_TDI JTAG test Data input pin for instructions as well as test Verify Guidelines have been met or list
and programming data. Data is shifted in on the rising required actions for compliance. (Arria V SoC device edge of the TCK pin.
variants only)
This pin has an internal 25-kΩ pull-up resistor that is
always active.
Connect this pin through a 1-kΩ - 10-kΩ pull-up resistor
to VCCPD_HPS in the dedicated I/O bank which the
JTAG pin resides.
To disable the JTAG circuitry, connect the TDI pin to
VCCPD_HPS using a 1-kΩ resistor.
HPS_TMS This pin has an internal 25-kΩ pull-up resistor that is Verify Guidelines have been met or list
always active. required actions for compliance. (Arria V SoC device
variants only) Connect this pin through a 1-kΩ - 10-kΩ - pull-up
resistor to the VCCPD_HPS in the dedicated I/O bank
which the JTAG pin resides.
To disable the JTAG circuitry, connect the TMS pin to
VCCPD_HPS using a 1-kΩ resistor.
HPS_TRST Active-low input to asynchronously reset the boundary-Verify Guidelines have been met or list
scan circuit. This pin has an internal 25-kΩ pull-up that required actions for compliance. (Arria V SoC device is always active.
variants only)
Connect this pin through a 1-kΩ - 10-kΩ pull-up resistor
to the VCCPD_HPS in the dedicated I/O bank which
the JTAG pin resides.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 37 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
HPS_TCK JTAG test clock input pin that clock input to the Verify Guidelines have been met or list
boundary-scan testing (BST) circuitry. required actions for compliance. (Arria V SoC device
variants only) This pin has an internal 25-kΩ pull-down that is always
active.
Connect this pin through a 1-kΩ - 10-kΩ pull-down
resistor to GND.
Treat this signal like a clock and follow typical clock
routing guidelines.
HPS_TDO JTAG test Data output pin for instructions as well as Verify Guidelines have been met or list
test and programming Data. required actions for compliance. (Arria V SoC device
variants only) To disable the JTAG circuitry, leave the HPS_TDO pin
unconnected.
In cases where the HPS_TDO pin uses VCCPD_HPS
= 2.5 V to drive a 3.3 V JTAG interface, there may be
leakage current in the HPS_TDI input buffer of the
interfacing devices. An external pull-up resistor tied to
3.3 V on the HPS_TDI pin may be used to eliminate the
leakage current if needed.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 38 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
HPS_nRST Warm reset to the HPS block. Verify Guidelines have been met or list
required actions for compliance. (Arria V SoC device This pin has an internal 25-kΩ pull-up resistor that is
variants only) always active.
Connect this pin through a 1-kΩ - 10-kΩ pull-up resistor
to VCCRSTCLK_HPS.
HPS_nPOR Cold reset to the HPS block. Verify Guidelines have been met or list
required actions for compliance. (Arria V SoC device This pin has an internal 25-kΩ pull-up resistor that is
variants only) always active.
Connect this pin through a 1-kΩ - 10-kΩ pull-up resistor
to VCCRSTCLK_HPS.
HPS_PORSEL Dedicated input that selects between a standard POR Verify Guidelines have been met or list
or a fast POR delay for HPS block. A logic low selects required actions for compliance. (Arria V SoC device a standard POR delay setting and a logic high selects
variants only) a fast POR delay setting.
This pin has an internal 25-kΩ pull-down resistor that is
always active.
Connect this pin directly to VCCRSTCLK_HPS or
GND.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 39 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues JTAG Header (HPS) Power the ByteBlaster II or USB-Blaster Verify Guidelines have been met or list
cable’s VCC (pin 4 of the header) with required actions for compliance. (Arria V SoC device variants VCCIO7A voltage.
only)
For multi-device JTAG chains with different
VCCIO voltages, voltage translators may be
required to meet the I/O voltages for the
devices in the chain and JTAG header.
The ByteBlaster II and USB-Blaster cables do
not support a target supply voltage of 1.2 V.
For the target supply voltage value, refer to
the ByteBlaster II Download Cable User
Guide and the USB-Blaster Download Cable
User Guide.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 40 of 131
DS-01028-4.0
Reviewed against Errata Sheet for Arria V Devices (PDF) version:
Additional Comments:
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 41 of 131
DS-01028-4.0
Section III: Transceiver
Documentation: Arria V Devices
Arria V Device Pin-Out Files
Arria V Device Family Pin Connection Guidelines (PDF)
Arria V Early Power Estimator
Arria V Early Power Estimator User Guide (PDF)
Power Delivery Network (PDN) Tool For Arria V Devices
Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 583: Designing Power Isolation Filters with Ferrite Beads for Altera FPGAs (PDF)
Arria V Hard IP for PCI Express User Guide (PDF)
Errata Sheet and Guidelines for Arria V ES Devices (PDF)
Errata Sheet for Arria V Devices (PDF)
Known Arria V Issues
Index
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 42 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCA_GXB[L,R][0:3] Analog power, transceiver high voltage, Verify Guidelines have been met or list
specific to the left (L) side or right (R) side of required actions for compliance. (not all pins are available the device.
in each device / package See Notes (3-1) (3-2) (3-3) (3-4) (3-5) combination) Connect VCCA_GXB to a 2.5V low noise (3-7).
switching regulator.
This power rail may be shared with
VCCA_FPLL and VCC_AUX. With a proper
isolation filter these pins may be sourced from
the same regulator as VCCIO, VCCPD and
VCCPGM, when each of these power
supplies require 2.5V.
Decoupling depends on the design decoupling
requirements of the specific board design.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 43 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCH_GXB[L,R][0:3] Analog power, transmitter output buffer Verify Guidelines have been met or list
specific to the left (L) side or right (R) side of required actions for compliance. (not all pins are available the device.
in each device / package See Notes (3-1) (3-2) (3-3) (3-4) (3-5) combination) Connect VCCH_GXB to a 1.5V linear or low (3-7).
noise switching regulator.
These pins may be sourced from the same
regulator as VCCD_FPLL and VCCBAT.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 44 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCT_GXB[L,R][0:3] Analog power, transmitter, specific to the left Verify Guidelines have been met or list
(L) side or right (R) side of the device. required actions for compliance. (not all pins are available
in each device / package For Arria V GX -C4, -C5, -I3, -I5, and -C6 See Notes (3-1) (3-2) (3-3) (3-4) (3-5) combination) devices with data rates <= 3.2Gbps, connect (3-7).
VCCT_GXB pins to a 1.1V low noise
switching regulator.
For Arria V GX -C4, -C5, -I3, and -I5 devices
with data rates > 3.2Gbps, connect
VCCT_GXB pins to a 1.15V low noise
switching regulator.
For Arria V GT devices, connect VCCT_GXB
pins to a 1.2V low noise switching regulator.
For Arria V GX -C4, -C5, -I5, and -C6 devices
with data rates <= 3.2Gbps, these pins may
be tied to the same 1.1V regulator as VCC
with a proper isolation filter.
For Arria V GX -C4, -C5, and -I5 devices with
data rates > 3.2Gbps, Arria V GX –I3 devices,
and Arria V GT devices, these pins can be
tied to the same regulator as VCCL_GXB and
VCCR_GXB with proper isolation filter.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 45 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCR_GXB[L,R][0:3] Analog power, receiver, specific to the left (L) Verify Guidelines have been met or list
side or right (R) side of the device. required actions for compliance. (not all pins are available
in each device / package For Arria V GX -C4, -C5, -I3, -I5, and -C6 See Notes (3-1) (3-2) (3-3) (3-4) (3-5) combination) devices with data rates <= 3.2Gbps, connect (3-7).
VCCR_GXB pins to a 1.1V low noise
switching regulator.
For Arria V GX -C4, -C5, -I3, and -I5 devices
with data rates > 3.2Gbps, connect
VCCR_GXB pins to a 1.15V low noise
switching regulator.
For Arria V GT devices, connect VCCR_GXB
pins to a 1.2V low noise switching regulator.
For Arria V GX –C4, -C5, -I5, and –C6
devices with data rates <= 3.2Gbps,
VCCR_GXB can share the same supply as
VCCL_GXB. VCCR_GXB and VCCL_GXB
can be shared with the same 1.1V power
regulator as VCC with proper isolation filter.
For Arria V GX -C4, -C5, and -I5 devices with
data rates > 3.2Gbps, Arria V GX –I3 devices,
and Arria V GT devices, these pins may be
tied to the same regulator as VCCL_GXB.
VCCR_GXB and VCCL_GXB can share the
same regulator as VCCT_GXB with proper
isolation filter.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board design.
Index Top of Section
Arria V GX, GT, SX, and ST Schematic Review Worksheet 4.0 Page 46 of 131
DS-01028-4.0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues VCCL_GXB[L,R][0:3] Analog power, transceiver clock network Verify Guidelines have been met or
power, specific to the left (L) side or the right list required actions for compliance. (not all pins are available (R) side of the device.
in each device / package See Notes (3-1) (3-2) (3-3) (3-4) (3-5) combination) For Arria V GX -C4, -C5, -I3, -I5, and -C6 (3-7).
devices with data rates <= 3.2Gbps, connect
VCCL_GXB pins to a 1.1V low noise
switching regulator.
For Arria V GX -C4, -C5, -I3, and -I5 devices
with data rates > 3.2Gbps, connect
VCCL_GXB pins to a 1.15V low noise
switching regulator.
For Arria V GT devices, connect VCCL_GXB
pins to a 1.2V low noise switching regulator.
For Arria V GX –C4, -C5, -I5, and –C6
devices with data rates <= 3.2Gbps,
VCCL_GXB can share the same supply as
VCCR_GXB. VCCL_GXB and VCCR_GXB
can be shared with the same 1.1V power
regulator as VCC with proper isolation filter.
For Arria V GX -C4, -C5, and -I5 devices with
data rates > 3.2Gbps, Arria V GX –I3 devices,
and Arria V GT devices, these pins may be
tied to the same regulator as VCCR_GXB.
VCCL_GXB and VCCR_GXB can share the
same regulator as VCCT_GXB with proper
isolation filter.
Decoupling for these pins depends on the
design decoupling requirements of the
specific board.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues REFCLK[0:3] [L,R]_p/n High speed differential reference clock Verify Guidelines have been met or
positive and negative receiver channels, list required actions for compliance. (not all pins are available specific to the left (L) side or right (R) side of
in each device / package the device. See Note (3-6). combination)
These pins may be AC-coupled or DC-
coupled when used. For HCSL I/O standard,
it only supports DC-coupling. In the PCI
Express configuration, DC-coupling is allowed
on the REFCLK if the selected REFCLK I/O
standard is HCSL.
Connect all unused REFCLK pins directly to
GND.
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Plane/Signal Schematic Name Connection Guidelines Comments/ Issues GXB_RX_[L,R][0:11]p/n, High speed positive (p) and negative (n) Verify Guidelines have been met or
GXB_REFCLK_[L,R][0:11]p/n differential receiver channels, or differential list required actions for compliance.
reference clocks. Specific to the left (L) side
(not all pins are available in or right (R) side of the device See Note (3-6). each device / package
combination) When used as GXB_RX for data rates >
3.2Gbps, these pins must be AC-coupled.
For data rates <= 3.2Gbps, these pins may
be AC-coupled or DC-coupled when used as
GXB_RX.
When used as GXB_REFCLK, these pins
must be AC-coupled except when used for
PCIe HCSL reference clocks which is the
only DC coupling configuration supported.
Connect all unused GXB_RXp /
GXB_REFCLKp pins directly to GND.
Connect all unused GXB_RXn /
GXB_REFCLKn pins directly to GND.
Some GXB_RX pins have the 10Gbps
capability in the Arria V GT device. For
details, refer to Transceiver Architecture in
Arria V Devices (PDF).
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Plane/Signal Schematic Name Connection Guidelines Comments/ Issues GXB_TX_[L,R][0:11]p/n High speed positive (p) or negative (n) Verify Guidelines have been met or list
differential transmitter channels. Specific to the required actions for compliance. (not all pins are available in left (L) side or right (R) side of the device.
each device / package
combination) Leave all unused GXB_TX pins floating.
Some GXB_TX pins have the 10Gbps capability
in the Arria V GT device. For details, refer to
Transceiver Architecture in Arria V Devices
(PDF).
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Plane/Signal Schematic Name Connection Guidelines Comments/ Issues RREF_BR Reference resistor for transceiver, specific to the Verify Guidelines have been met or list
right (R) side of the device, and PLL on bottom required actions for compliance.
and right sides of the device.
If any REFCLK pin or transceiver channel on the
right side of the device, or PLL on the bottom or
right side of the device is used, you must
connect the RREF pin on that side of the device
to its own individual 2.0-kΩ +/- 1% resistor to
GND. Otherwise, you may connect the RREF
pin on that side of the device directly to GND.
In the PCB layout, the trace from this pin to the
resistor needs to be routed so that it avoids any
aggressor signals.
RREF_TL Reference resistor for transceiver, specific to the
left (L) side of the device, and PLL on top and
left side of the device.
If any REFCLK pin or transceiver channel on the
left side of the device, or PLL on the top or left
side of the device is used, you must connect the
RREF pin on that side of the device to its own
individual 2.0-kΩ +/- 1% resistor to GND.
Otherwise, you may connect the RREF pin on
that side of the device directly to GND.
In the PCB layout, the trace from this pin to the
resistor needs to be routed so that it avoids any
aggressor signals.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
nPERST[L0,R0] Dedicated fundamental reset pin is only available when Verify Guidelines have been met or list
used in conjunction with PCIe HIP. One nPERST pin is required actions for compliance.
used per PCIe HIP. The Arria V GX and GT devices
always have two pins listed, even if the specific
component might have 0 or 1 PCIe hard IP blocks.
When this pin is not used as the fundamental reset, this
pin may be used as a user I/O pin. Connect this pin as
defined in the Quartus II software.
When low the transceivers are in reset. When high the
transceivers are out of reset. When these pins are not
used as the fundamental reset, they may be used as user
I/O.
nPERSTL0 = Bottom left PCIe HIP and CvP
nPERSTR0 = Bottom right PCIe HIP (when available)
For maximum compatibility, Altera recommends using
nPERSTL0 (the bottom left PCIe HIP) first, this is the
only PCIe HIP that supports CvP (Configuration Via
Protocol - over the PCIe link). When using the bottom
left PCIe HIP, connect nPERST from the PCIe slot
directly to nPERSTL0.
This pin may be driven by 3.3V regardless of the VCCIO
voltage level of the bank without a level translator as long
as the input signal meets the LVTTL VIH/VIL
specification and the overshoot specifications as listed in
the Arria V GX, GT, SX, and ST Device Datasheet (PDF).
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Notes:
3-1. Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the
frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current
draw and voltage droop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors.
On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board
design techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling. To assist in
decoupling analysis, Altera's Power Delivery Network (PDN) Tool for Arria V Devices serves as an excellent decoupling analysis tool.
3-2. Use the Early Power Estimation Tools to determine the current requirements for VCC and other power supplies. Power pins should not share
breakout vias from the BGA. Each ball on the BGA needs to have its own dedicated breakout via.
3-3. These supplies may share power planes across multiple Arria V devices.
3-4. Low Noise Switching Regulator - defined as a switching regulator circuit encapsulated in a thin surface mount package containing the switch
controller, power FETs, inductor, and other support components. The switching frequency is usually between 800kHz and 1MHz and has fast
transient response. The switching frequency range is not an Altera requirement. However, Altera does require the Line Regulation and Load
Regulation meet the following requirements:
, Line Regulation < 0.4%.
, Load Regulation < 1.2%
3-5. If all of the transceivers on one side of the device are not used, then the transceiver power pins on that side may be tied to GND. These pins
include VCCR_GXB, VCCT_GXB, VCCL_GXB, VCCH_GXB, and VCCA_GXB. All pins must be powered up or tied to GND.
3-6. For AC-coupled links, the AC-coupling capacitor can be placed anywhere along the channel. PCI Express protocol requires the AC-coupling
capacitor to be placed on the transmitter side of the interface that permits adapters to be plugged and unplugged.
3-7. Examples 1 - 15 and Figures 1 - 15 in the Arria V Device Family Pin Connection Guidelines (PDF) illustrate power supply sharing guidelines that are data rate dependent.
Index Top of Section
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Reviewed against Errata Sheet for Arria V Devices (PDF) version:
Additional Comments:
Index Top of Section
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Section IV: I/O
Documentation: Arria V Devices
Arria V Device Pin-Out Files
Arria V Device Family Pin Connection Guidelines (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
AN 597: Getting Started Flow for Board Designs (PDF)
Errata Sheet and Guidelines for Arria V ES Devices (PDF)
Errata Sheet for Arria V Devices (PDF)
Known Arria V Issues
Index
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Part A: Clock Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues CLK[0:23]p Multi-purpose pins with the following Verify Guidelines have been met or list
functionality: required actions for compliance. (not all pins are
available in each - Dedicated high speed positive differential See Note (4-1).
device / package clock or differential data input with OCT Rd combination) support.
- Single ended clock or data input with OCT
Rt support.
- Single ended output with OCT Rs support.
The programmable weak pull up resistor is
available for single ended I/O usage.
Use dedicated clock pins to drive clocks into
the device.
These pins can connect to the device PLLs
using dedicated routing paths or global
networks. Refer to Clock Networks and PLLs
in Arria V devices (PDF) for further
information on dedicated routing of clock pins
to PLLs.
Unused pins can be tied to GND or left
unconnected. If unconnected, use the
Quartus II software programmable options to
internally bias these pins. They can be
reserved as inputs tristate with weak pull up
resistor enabled, or as outputs driving GND.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues CLK[0:23]n Multi-purpose pins with the following Verify Guidelines have been met or list
functionality: required actions for compliance. (not all pins are
available in each - Dedicated high speed negative differential See Note (4-1).
device / package clock or differential data input with OCT Rd combination) support.
- Single ended clock or data input with OCT
Rt support.
- Single ended output with OCT Rs support.
The programmable weak pull up resistor is
available for single ended I/O usage.
Use dedicated clock pins to drive clocks into
the device.
These pins cannot connect to the device PLLs
using dedicated routing paths, they use global
or regional networks. Refer to Clock Networks
and PLLs in Arria V devices (PDF) for further
information on dedicated routing of clock pins
to PLLs.
Unused pins can be tied to GND or left
unconnected. If unconnected, use the
Quartus II software programmable options to
internally bias these pins. They can be
reserved as inputs tristate with weak pull up
resistor enabled, or as outputs driving GND.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues FPLL_[B,T][L,C,R]_ Dual purpose I/O pins that can be used as: Verify Guidelines have been met or list
CLKOUT0, or required actions for compliance. , Two single ended clock output pins, FPLL_[B,T][L,C,R]_ or
CLKOUTp, or See Note (4-1). , One differential clock output pair, or FPLL_[B,T][L,C,R]_ , Single ended external feedback input FB0 pin (not all pins are If not used for their dedicated PLL input or available in each output functionality, these pins are available device / package for regular single ended I/O usage, or as a combination) differential transmitter.
Unused pins can be tied to GND or left
unconnected. If unconnected, use the
Quartus II software programmable options to
internally bias these pins. They can be
reserved as inputs tristate with weak pull up FPLL_[B,T][L,C,R]_ resistor enabled, or as outputs driving GND. CLKOUT1, or FPLL_[B,T][L,C,R]_ CLKOUTn, (not all pins are available in each device / package combination)
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
FPLL_[B,T][L,C,R]_ Dual purpose I/O pins that can be used as: Verify Guidelines have been met or list CLKOUT2, or required actions for compliance. , Two single ended clock output pins,
FPLL_[B,T][L,C,R]_ or
FBp, or See Note (4-1). , One differential external feedback FPLL_[B,T][L,C,R]_ input pair, or
FB1 , Single ended external feedback input pin (not all pins are available in each If not used for their dedicated PLL feedback device / package input or output functionality, these pins are combination) available for regular single ended I/O usage, or as a differential receiver. Unused pins can be tied to GND or left unconnected. If unconnected, use the Quartus II software programmable options to FPLL_[B,T][L,C,R]_ internally bias these pins. They can be CLKOUT3, or reserved as inputs tristate with weak pull up FPLL_[B,T][L,C,R]_ resistor enabled, or as outputs driving GND. FBn
(not all pins are available in each device / package
combination)
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Additional Comments:
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Part B: Dedicated and Dual Purpose Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues RZQ[0,1,5,6] Calibrated on chip termination reference pins Verify Guidelines have been met or list
for I/O banks. The RZQ pins share the same required actions for compliance.
VCCIO with the I/O bank where they are
located. The external precision resistor must See Note (4-1).
be connected to the designated pin within the
bank.
When using calibrated OCT tie these pins to
GND through either a 240-Ω or 100-Ω
resistor, depending on the desired OCT
impedance. Refer to I/O Features in Arria V
Devices (PDF) for the OCT impedance
options for the desired OCT scheme.
If not required for its dedicated function, this
pin can be used as a regular I/O pin.
When not using RZQ# for the external
precision resistor or as a regular I/O pin, it is
recommended that the pin be connected to
GND.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
DNU Do not connect to power or ground or any Verify Guidelines have been met or list
other signal; these pins must be left required actions for compliance.
unconnected.
NC Do not drive signals into these pins. Verify Guidelines have been met or list
required actions for compliance.
When designing for device migration these
pins may be connected to power, ground, or a
signal trace depending on the pin assignment
of the devices selected migration. However, if
device migration is not a concern leave these
pins unconnected. See Knowledge Database
solution rd03132006_933.
Additional Comments:
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Part C: Dual Purpose Differential I/O pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues DIFFIO_RX[T,B][##]p, These are true LVDS receiver channels on Verify Guidelines have been met or list
DIFFIO_RX[T,B][##]n column I/O banks. Pins with a "p" suffix carry required actions for compliance.
the positive signal for the differential channel.
(Refer to the device Pins with an "n" suffix carry the negative See Note (4-1). Pin Table for number signal for the differential channel.
of channels based on
device selected) If not used for differential signaling, these pins
are available as single ended user I/O pins.
These pins do not have dedicated differential
transmitters.
True LVDS receivers support OCT Rd when
VCCPD is 2.5V.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues DIFFIO_TX[T,B][##]p, These are true LVDS transmitter channels on Verify Guidelines have been met or list
DIFFIO_TX[T,B][##]n column I/O banks. Pins with a "p" suffix carry required actions for compliance.
the positive signal for the differential channel.
(Refer to the device Pins with an "n" suffix carry the negative See Note (4-1). Pin Table for number signal for the differential channel.
of channels based on
device selected) If not used for differential signaling, these pins
are available as single ended user I/O pins.
These pins do not have differential receivers.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues DIFFOUT_[T,B][##]p, These are emulated LVDS output channels. Verify Guidelines have been met or list
DIFFOUT__[T,B][##]n All user I/Os, including I/Os with true LVDS required actions for compliance.
input buffers, can be configured as emulated
(Refer to the device LVDS output buffers. See Note (4-1).
Pin Table for number
of channels based on Pins with a "p" suffix carry the positive signal device selected) for the differential channel. Pins with an "n"
suffix carry the negative signal for the
differential channel.
If not used for differential signaling, these pins
are available as single ended user I/O pins.
Emulated LVDS transmitters require external
resistor networks.
Unused pins can be tied to GND or
unconnected. If unconnected, use Quartus II
software programmable options to internally
bias these pins. They can be reserved as
inputs tristate with weak pull up resistor
enabled, or as outputs driving GND.
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Notes:
4-1. Refer to Knowledge Database solution rd12102002_3281 for further information regarding the concerns when I/O pins are left floating with no internal or external bias. Ensure there are no conflicts between the Quartus II software device wide default configuration for unused I/Os and the
board level connection. Altera recommends setting unused I/O pins on a project wide basis to behave as inputs tri-state with weak pull up resistor
enabled. Individual unused pins can be reserved with specific behavior such as output driving ground or as output driving VCC to comply with the
PCB level connection.
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Part D: HPS I/O Pins
This section is used to review the HPS I/O pins for the SoC variants of the Arria V device family (SX and ST). In order for the HPS to operate, the CLKSEL[1..0] and BOOTSEL[2..0] pins must be connected correctly. For further details, refer to the Configuration section of this review document. For HPS external memory interface pin usage, refer to the External Memory Interfaces section of this review document.
A Quartus II project archive that includes all SoC hard peripherals configured and pinned out as they are intended to be used must be provided for this section of the review.
Each of the HPS I/O pins have multiple dedicated peripheral functions which are listed for each pin in the I/O section of this review. The I/O pin function on the schematic will be cross referenced to the Quartus II project usage to verify there are no conflicts. The peripheral pins are programmable through pin multiplexors. Each pin may have up to four functions, Refer to the Arria V GT, GX, ST, and SX Device Family Pin Connection Guidelines (PDF) for peripheral usage pin function sharing. Configuration of each pin is done during HPS configuration.
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HPS peripheral usage
Peripheral Pin multiplexing Mode TRACE CAN0 CAN1 I2C0 I2C1 I2C2 I2C3 UART0 UART1 SPIM0 SPIM1 SPIS0 SPIS1 SDMMC/SDIO QSPI NAND USB0 USB1 EMAC0 EMAC1
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VCCRSTCLK_HPS Voltage:
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
HPS_CLK1 The input clock must be present at this pin for HPS Verify Guidelines have been met or list
operation. required actions for compliance.
Dedicated clock input pin that drives the main PLL.
This provides clocks to the MPU, L3/L4 sub-systems,
debug sub-system and the Flash controllers. It can also
be programmed to drive the peripheral and SDRAM
PLLs.
Connect a single-ended clock source to this pin. The
I/O standard of the clock source must be compatible
with VCCRSTCLK_HPS.
Refer to the valid frequency range of the clock source
in the Arria V Device Datasheet (PDF). The input clock
must be present at this pin for HPS operation.
HPS_CLK2 Dedicated clock input pin that can be programmed to Verify Guidelines have been met or list
drive the peripheral and SDRAM PLLs. required actions for compliance.
Connect a single-ended clock source to this pin. The
I/O standard of the clock source must be compatible
with VCCRSTCLK_HPS.
Refer to the valid frequency range of the clock source
in Arria V Device Datasheet (PDF).
This is an optional HPS clock input pin. When you do
not use this pin, Altera recommends tying it to
VCCRSTCLK_HPS.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
HPS_RZQ_0 Reference pin for I/O banks. The HPS_RZQ_0 pin Verify Guidelines have been met or list
shares the same HPS_VCCIO with the I/O bank where required actions for compliance.
it is located.
The external precision resistor must be connected to
the designated pin within the bank. If not required, this
pin is a regular I/O pin.
When this pin is used for the OCT calibration, the
HPS_RZQ_0 pin is connected to GND through an
external 100-Ω or 240-Ω reference resistor depending
on the desired OCT impedance. For the OCT
impedance options for the desired OCT scheme, refer
to I/O Features In Arria V Devices (PDF).
When the Arria V SoC device does not use this
dedicated input pin for the external precision resistor or
as an I/O pin, Altera recommends connecting this pin to
GND.
HPS_GPI[#] General purpose inputs signals in the SDRAM bank. Verify Guidelines have been met or list
required actions for compliance. (Number of available These pins use the same VCCIO_HPS as the other
general purpose input HPS SDRAM pins.
pins is device specific)
If unused, configure these pins in the Quartus II
software as inputs tristate with weak pull-up resistor
enabled.
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TRACE
Plane/Signal Schematic Name Connection Guidelines Comments / Issues TRACE_CLK TRACE port. Verify Guidelines have been met or list
required actions for compliance.
Output trace clk.
TRACE_D[7:0] Output trace data. Verify Guidelines have been met or list
required actions for compliance.
If unused, program it in the Quartus II software as an
input with a weak pull-up.
CAN0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues CAN0_RX CAN0 interface. Verify Guidelines have been met or list
required actions for compliance.
Input Receive Data.
CAN0_TX Output Transmit data. Verify Guidelines have been met or list
required actions for compliance.
CAN1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues CAN1_RX CAN1 interface. Verify Guidelines have been met or list
required actions for compliance.
Input Receive Data.
CAN1_TX Output Transmit data. Verify Guidelines have been met or list
required actions for compliance.
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I2C0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues 2C controller pins. Verify Guidelines have been met or list I2C0_SDA I
required actions for compliance.
Bidirectional Serial Data.
I2C0_SCL Bidirectional Serial Clock. Verify Guidelines have been met or list
required actions for compliance.
I2C1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues 2I2C1_SDA IC controller pins. Verify Guidelines have been met or list
required actions for compliance.
Bidirectional Serial Data.
I2C1_SCL Bidirectional Serial Clock. Verify Guidelines have been met or list
required actions for compliance.
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I2C2
Plane/Signal Schematic Name Connection Guidelines Comments / Issues 2C controller pins. Verify Guidelines have been met or list I2C2_SDA I
required actions for compliance.
Bidirectional Serial Data.
I2C2_SCL Bidirectional Serial Clock. Verify Guidelines have been met or list
required actions for compliance.
I2C3
Plane/Signal Schematic Name Connection Guidelines Comments / Issues 2I2C3_SDA IC controller pins. Verify Guidelines have been met or list
required actions for compliance.
I2C3_SCL Bidirectional Serial Clock. Verify Guidelines have been met or list
required actions for compliance.
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UART0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues UART0_RX UART controller pins. Verify Guidelines have been met or list
required actions for compliance.
Input UART receive data.
UART0_TX Output UART transmit data. Verify Guidelines have been met or list
required actions for compliance.
Input UART Clear To Send signal (cts_n). Verify Guidelines have been met or list UART0_CTS
required actions for compliance.
UART0_RTS Output UART Ready To Send signal (rts_n). Verify Guidelines have been met or list
required actions for compliance.
UART1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues UART1_RX UART controller pins. Verify Guidelines have been met or list
required actions for compliance.
Input UART receive data.
UART1_TX Output UART transmit data. Verify Guidelines have been met or list
required actions for compliance.
UART1_CTS Input UART Clear To Send signal (cts_n). Verify Guidelines have been met or list
required actions for compliance.
UART1_RTS Output UART Ready To Send signal (rts_n). Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section HPS Peripheral Table
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SPIM0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues SPIM0_CLK SPI master controller pins. Verify Guidelines have been met or list
required actions for compliance.
Output SPI clock.
SPIM0_MOSI Output SPI Master Out Slave In Data. Verify Guidelines have been met or list
required actions for compliance.
SPIM0_MISO Input SPI Master In Slave Out Data. Verify Guidelines have been met or list
required actions for compliance.
SPIM0_SS0 Output SPI Slave Select 0. Verify Guidelines have been met or list
required actions for compliance.
SPIM0_SS1 Output SPI Slave Select 1. Verify Guidelines have been met or list
required actions for compliance.
SPIM1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues SPIM1_CLK SPI master controller pins. Verify Guidelines have been met or list
required actions for compliance.
Output SPI clock.
SPIM1_MOSI Output SPI Master Out Slave In Data. Verify Guidelines have been met or list
required actions for compliance.
SPIM1_MISO Input SPI Master In Slave Out Data. Verify Guidelines have been met or list
required actions for compliance.
SPIM1_SS0 Output SPI Slave Select 0. Verify Guidelines have been met or list
required actions for compliance.
SPIM1_SS1 Output SPI Slave Select 1. Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section HPS Peripheral Table
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SPIS0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues SPIS0_CLK SPI slave controller pins. Verify Guidelines have been met or list
required actions for compliance.
Input SPI clock.
SPIS0_MOSI Input SPI Master Out Slave In Data. Verify Guidelines have been met or list
required actions for compliance.
Output SPI Master In Slave Out Data. Verify Guidelines have been met or list SPIS0_MISO
required actions for compliance.
SPIS0_SS0 Input SPI Slave Select. Verify Guidelines have been met or list
required actions for compliance.
SPIS1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues SPIS1_CLK SPI slave controller pins. Verify Guidelines have been met or list
required actions for compliance.
Input SPI clock.
SPIS1_MOSI Input SPI Master Out Slave In Data. Verify Guidelines have been met or list
required actions for compliance.
SPIS1_MISO Output SPI Master In Slave Out Data. Verify Guidelines have been met or list
required actions for compliance.
SPIS1_SS0 Input SPI Slave Select. Verify Guidelines have been met or list
required actions for compliance.
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SDMMC/SDIO
Plane/Signal Schematic Name Connection Guidelines Comments / Issues SDMMC_CMD Where the SD/MMC controller is used these pins form Verify Guidelines have been met or list
an SD/MMC/CE-ATA interface. required actions for compliance.
Bidirectional card command.
SDMMC_PWREN Output external power enable. Verify Guidelines have been met or list
required actions for compliance.
SDMMC_D[7:0] Bidirectional card data. Verify Guidelines have been met or list
required actions for compliance.
SDMMC_CLK_IN Input clock to SD/MMC controller CIU. Verify Guidelines have been met or list
required actions for compliance.
SDMMC_CLK Output clock to card. Verify Guidelines have been met or list
required actions for compliance.
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QSPI
Plane/Signal Schematic Name Connection Guidelines Comments / Issues QSPI_SS[3:0] QSPI controller pins. Verify Guidelines have been met or list
required actions for compliance.
Output slave select signals.
QSPI_IO[0] Extended SPI mode: Verify Guidelines have been met or list
Output Data. required actions for compliance.
Dual or quad IO mode:
Bidirectional data.
QSPI_IO[1] Extended SPI mode: Verify Guidelines have been met or list
Input Data. required actions for compliance.
Dual or Quad IO mode:
Bidirectional data.
QSPI_IO[2] Extended SPI mode and dual IO mode: Verify Guidelines have been met or list
Output write protect. required actions for compliance.
Quad IO mode:
Bidirectional data.
QSPI_IO[3] Quad IO mode: Verify Guidelines have been met or list
Bidirectional data. required actions for compliance.
QSPI_CLK Output clock. Verify Guidelines have been met or list
required actions for compliance.
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NAND Controller
Plane/Signal Schematic Name Connection Guidelines Comments / Issues NAND_ALE If the NAND flash controller is used, these pins form Verify Guidelines have been met or list
the ONFI to a NAND flash device. required actions for compliance.
Output address latch enable.
NAND_CE Output chip enable. Verify Guidelines have been met or list
required actions for compliance.
Output command latch enable. Verify Guidelines have been met or list NAND_CLE
required actions for compliance.
NAND_RE Output read enable. Verify Guidelines have been met or list
required actions for compliance.
NAND_RB Input ready/busy. Verify Guidelines have been met or list
required actions for compliance.
NAND_DQ[7:0] Bidirectional command, address, data. Verify Guidelines have been met or list
required actions for compliance.
NAND_WP Output write protect. Verify Guidelines have been met or list
required actions for compliance.
NAND_WE Output write enable. Verify Guidelines have been met or list
required actions for compliance.
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USB0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues USB0_D[7:0] If USB0 is used these pins form the ULPI to a USB Verify Guidelines have been met or list
PHY. required actions for compliance.
Bidirectional data driven low by the controller during
idle.
Input clock receives the 60MHz clock from the ULPI Verify Guidelines have been met or list USB0_CLK
PHY. required actions for compliance.
USB0_STP Output stop data control. Verify Guidelines have been met or list
required actions for compliance.
USB0_DIR Input data bus control. Verify Guidelines have been met or list
required actions for compliance.
USB0_NXT Input next data control. Verify Guidelines have been met or list
required actions for compliance.
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USB1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues USB1_D[7:0] If USB1 is used these pins form the ULPI to a USB Verify Guidelines have been met or list
PHY. required actions for compliance.
Bidirectional data driven low by the controller during
idle.
Input clock receives the 60MHz clock from the ULPI Verify Guidelines have been met or list USB1_CLK
PHY. required actions for compliance.
USB1_STP Output stop data control. Verify Guidelines have been met or list
required actions for compliance.
USB1_DIR Input data bus control. Verify Guidelines have been met or list
required actions for compliance.
USB1_NXT Input next data control. Verify Guidelines have been met or list
required actions for compliance.
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EMAC0
Plane/Signal Schematic Name Connection Guidelines Comments / Issues RGMII0_TX_CLK If EMAC0 is used, these pins form the RGMII to an Verify Guidelines have been met or list
Ethernet PHY or switch. required actions for compliance.
Input transmit clock.
RGMII0_RX_CLK Input Receive clock. Verify Guidelines have been met or list
required actions for compliance.
Output transmit data. Verify Guidelines have been met or list RGMII0_TXD[3:0]
required actions for compliance.
RGMII0_TXCTL Output transmit control. Verify Guidelines have been met or list
required actions for compliance.
RGMII0_RXD[3:0] Input Receive data. Verify Guidelines have been met or list
required actions for compliance.
RGMII0_RXCTL Input Receive control. Verify Guidelines have been met or list
required actions for compliance.
RGMII0_MDC Output management clock. Verify Guidelines have been met or list
required actions for compliance.
RGMII0_MDIO Bidirectional management data. Verify Guidelines have been met or list
required actions for compliance.
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EMAC1
Plane/Signal Schematic Name Connection Guidelines Comments / Issues RGMII1_TX_CLK If EMAC1 is used, these pins form the RGMII to an Verify Guidelines have been met or list
Ethernet PHY or switch. required actions for compliance.
Input transmit clock.
RGMII1_RX_CLK Input Receive clock. Verify Guidelines have been met or list
required actions for compliance.
Output transmit data. Verify Guidelines have been met or list RGMII1_TXD[3:0]
required actions for compliance.
RGMII1_TXCTL Output transmit control. Verify Guidelines have been met or list
required actions for compliance.
RGMII1_RXD[3:0] Input Receive data. Verify Guidelines have been met or list
required actions for compliance.
RGMII1_RXCTL Input Receive control. Verify Guidelines have been met or list
required actions for compliance.
RGMII1_MDC Output management clock. Verify Guidelines have been met or list
required actions for compliance.
RGMII1_MDIO Bidirectional management data. Verify Guidelines have been met or list
required actions for compliance.
Index Top of Section HPS Peripheral Table
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GPIO
Plane/Signal Schematic Name Connection Guidelines Comments / Issues GPIO[70:0] Pins which are not used for one of the peripheral Verify Guidelines have been met or list
functions may be used as GPIO. required actions for compliance.
Unused pins can be tied to GND or unconnected. If
unconnected, use Quartus II software programmable
options to internally bias these pins. They can be
reserved as inputs tristate with weak pull-up resistor
enabled, or as outputs driving GND.
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Reviewed against Errata Sheet for Arria V Devices (PDF) version:
Additional Comments:
Index Top of Section HPS Peripheral Table
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Section V: External Memory Interfaces
Arria V Literature
Arria V Recommended Reference Literature/Tool List
Arria V Pin Out Files
Arria V Device Family Pin Connection Guidelines (PDF)
Altera Board Design Resource Center (General board design guidelines, PDN design, isolation, tools, and more)
Errata Sheet and Guidelines for Arria V ES Devices (PDF)
Errata Sheet for Arria V Devices (PDF)
External Memory Interface Literature
External Memory Interfaces in Arria V Devices (PDF)
DDR2 and DDR3 SDRAM Board Design Guidelines (PDF)
Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines (PDF)
RLDRAM II SRAM Board Design Guidelines (PDF)
QDR II SRAM Board Design Guidelines (PDF)
Planning Pin and FPGA Resources (PDF)
DDR, DDR2, DDR3, QDRII/+ SRAM, RLDRAMII Literature
External Memory interface Handbook
You can use the dedicated memory controllers for DDR2, DDR3 SDRAM, QDRII/+ SRAM and RLDRAMII interfaces.
For pin-outs when implementing Hard Memory Controllers, refer to the Arria V pin-out files. Hard Memory Controller has pre-assigned pins for DDR2 and DDR3 SDRAM along with QDRII/+ SRAM and RLDRAMII interfaces.
Index
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Part A: DDR3/DDR3L
Interface Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Data pin - DQ Place it on DQ pins of the DQ/DQS group. Verify Guidelines have been met or list
The order of the DQ bits within a designated required actions for compliance.
DQ group/bus is not important; however, use
caution when making pin assignments if you See Note (5-1).
plan on migrating to a different memory
interface that has a different DQ bus width
(e.g. migrating from x4 to x8). Analyze the
available DQ pins across all pertinent DQS
columns in the pin list.
Data strobe - Should be placed on corresponding DQS and Verify Guidelines have been met or list DQS/DQSn DQSn pins of the DQ/DQS group. required actions for compliance.
See Notes (5-1) (5-2).
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues mem_clk and Place on any unused DQ or DQS pins with Verify Guidelines have been met or list
mem_clk_n DIFFOUT capability for the mem_clk[n:0] and required actions for compliance.
mem_clk_n[n:0] signals (where n>=0).
See Note (5-2).
Do not place CK and CK# pins in the same
group as any other DQ or DQS pins.
If there are multiple CK and CK# pin pairs,
place them on DIFFOUT in the same single
DQ group of adequate width.
clock_source Input clock pin to the DDR3/ DDR3L core PLL Verify Guidelines have been met or list
required actions for compliance.
FPGA DDR3/DDR3L interfaces:
Dedicated PLL clock input pin with direct (not
using a global clock net) connection to the
PLL and DLL required by the interface.
HPS DDR3/DDR3L interfaces :
The SDRAM interface PLL input clock must
be sourced from HPS_CLK1 or HPS_CLK2.
Altera does not check this.
An important recommendation is to use a low
jitter clock source. See the recommendations
for Memory Output Clock Jitter in the Arria V
Datasheet. Altera does not check this.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
DM Data Mask Pin – Place it on one of the DQ Verify Guidelines have been met or list
pins in the group. DM pins need to be part of required actions for compliance.
the DQS/DQ group.
See Note (5-2).
Address Any user I/O pin. To minimize skew, you Verify Guidelines have been met or list
should place address and command pins in required actions for compliance.
the same bank or side of the device as the
following pins: See Note (5-2).
? mem_clk* pins.
? DQ, DQS, or DM pins.
Command Any user I/O pin. To minimize skew, you Verify Guidelines have been met or list
should place address and command pins in required actions for compliance.
the same bank or side of the device as the
following pins: See Note (5-2).
? mem_clk* pins.
? DQ, DQS, or DM pins.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Reset for Any user I/O pin in the same bank or side of Verify Guidelines have been met or list DDR3/DDR3L Memory the device as the following pins: required actions for compliance.
? mem_clk* pins.
? DQ, DQS, or DM pins.
Reset Dedicated clock input pin. (high fan-out signal) Verify Guidelines have been met or list
The reset pin can alternatively be generated. required actions for compliance.
Ensure the DDR3/DDR3L IP closes reset
Recovery/Removal timing in Report DDR.
RZQ Used when calibrated OCT for the memory Verify Guidelines have been met or list
interface pins is implemented. required actions for compliance.
Make sure that the VCCIO of your
DDR3/DDR3L interface bank and the VCCIO
of the bank with RZQ pin match.
If the RZQ pin is used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Notes:
5-1. DDR3 and DDR3L only support differential DQS signaling.
5-2. Arria V GX Hard Memory Interfaces and Arria V SoC HPS SDRAM Interfaces have pre-assigned pins for DDR3/DDR3L SDRAM interfaces.
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Additional Comments:
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Part B: DDR3DDR3L
Interface Termination
Guidelines
Plane/Signal Schematic Name Connection Guidelines Comments / Issues Memory clocks@ Arria V devices do not support DDR3/DDR3L Verify Guidelines have been met or list
Memory SDRAM with read or write leveling, so these required actions for compliance.
devices do not support standard
DDR3/DDR3L SDRAM DIMMs or See Note (5-3).
DDR3/DDR3L SDRAM components using the
standard DDR3/DDR3L SDRAM fly-by
address, command, and clock layout
topology.
Devices (without leveling) – differential
termination resistor needs to be included in
the design. Depending on your board stackup
and layout requirements, you choose your
differential termination resistor value.
Memory clocks@ DDR3 : Use series 50-Ω output termination Verify Guidelines have been met or list
FPGA without calibration. required actions for compliance.
DDR3L : Use series 40-Ω output termination See Note (5-3).
without calibration.
Source
_pin_assignments.tcl to
make the setting.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
DQS @ Memory Use ODT. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-3).
DQS @ FPGA DDR3 : Use parallel 50-Ω with calibration as Verify Guidelines have been met or list
input termination and series 50-Ω with required actions for compliance.
calibration as output termination.
See Note (5-3).
DDR3L : Use parallel 40-Ω with calibration as
input termination and series 40-Ω with
calibration as output termination. Source
_pin_assignments.tcl file to
make these assignments automatically.
DQ @ Memory Use ODT. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-3).
DQ @ FPGA DDR3 : Use parallel 50-Ω with calibration as Verify Guidelines have been met or list
input termination and series 50-Ω with required actions for compliance.
calibration as output termination.
DDR3L : Use parallel 40-Ω with calibration as See Note (5-3).
input termination and series 40-Ω with
calibration as output termination. Source
_pin_assignments.tcl file to
assign these assignments automatically.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues DM@ Memory Use ODT. Verify Guidelines have been met or list
required actions for compliance.
If DM pins are unused, refer to the
DDR3/DDR3L manufacturer's data sheet for See Note (5-3).
connection recommendations. Typically they
must be tied low using a resistor no greater
than 4*Rtt (the nominal ODT value used on
the memory device).
DM @ FPGA DDR3 : Use series 50-Ω with calibration as Verify Guidelines have been met or list
output termination. required actions for compliance.
DDR3L : Use series 40-Ω with calibration as See Note (5-3).
output termination.
Source
_pin_assignments.tcl file to
make this assignment automatically.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues Address [BA, Discrete Device (no leveling) - Unidirectional Verify Guidelines have been met or list
mem_addr] @ Memory class I termination. required actions for compliance.
Unidirectional class I termination. For multi-See Note (5-3).
loads Altera recommends the ideal topology is
a balanced symmetrical tree. Altera
recommends that the class I termination to
VTT is placed at the first split or division of the
symmetrical tree for discrete devices.
Address [BA, DDR3 : Use maximum current drive strength. Verify Guidelines have been met or list
mem_addr] @ FPGA required actions for compliance.
DDR3L : Use series 40-Ω without calibration
as output termination. See Note (5-3).
Source
_pin_assignments.tcl file to
make this assignment automatically.
Command [CKE, Discrete Device (no leveling) - Unidirectional Verify Guidelines have been met or list
CS_N, ODT, RAS, class I termination. required actions for compliance. CAS, WE_N] @
Memory Unidirectional class I termination. For multi-See Note (5-3).
loads Altera recommends the ideal topology is
a balanced symmetrical tree. Altera
recommends that the class I termination to
VTT is placed at the first split or division of the
symmetrical tree for discrete devices.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Command [CKE, DDR3 : Use maximum current drive strength. Verify Guidelines have been met or list CS_N, ODT, RAS, required actions for compliance. CAS, WE_N] @ FPGA DDR3L : Use series 40-Ω without calibration
as output termination. See Note (5-3).
Source
_pin_assignments.tcl file to
make this assignment automatically.
Reset for DDR3 : Use 1.5V CMOS output. Verify Guidelines have been met or list DDR3/DDR3L Memory required actions for compliance.
DDR3L : Use SSTL-135 output
It is not recommended to terminate this reset
to Vtt.
Notes:
5-3. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.
Additional Comments:
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Miscellaneous
Pin Description Schematic Name Connection Guidelines Comments / Issues Vref Use a voltage regulator to generate this Verify Guidelines have been met or list
voltage. required actions for compliance.
Vtt Use a voltage regulator to generate this Verify Guidelines have been met or list
voltage. required actions for compliance.
Typically DDR3/DDR3L DIMMS have
decoupling capacitors connected between
VTT and VDD and it is recommended that
designers follow this approach.
Note that DDR3/DDR3L DIMM layout
topology is not supported.
RZQ RZQ pin is connected to GND through an Verify Guidelines have been met or list
external 240-Ω or 100-Ω ?1% resistor. Refer required actions for compliance.
to I/O Features in Arria V Devices (PDF) for
the OCT impedance options for the desired
OCT scheme.
If the RZQ pin is used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Additional Comments:
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Part C: DDR2
Interface Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues Data pins - DQ Place it on DQ pins of the DQ/DQS group. Verify Guidelines have been met or list
The order of the DQ bits within a designated required actions for compliance.
DQ group/bus is not important; however, use
caution when making pin assignments if you See Note (5-4).
plan on migrating to a different memory
interface that has a different DQ bus width
(e.g. migrating from x4 to x8). Analyze the
available DQ pins across all pertinent DQS
columns in the pin list.
Data strobe - Differential DQS - Should be placed on Verify Guidelines have been met or list
DQS/DQSn corresponding DQS and DQSn pins of the required actions for compliance.
DQ/DQS group.
See Note (5-4).
Single ended DQS – Connect the DQS pin to
the DQS pin of the corresponding DQ/DQS
group.
Data Mask DM Place it on one of the DQ pins in the group. Verify Guidelines have been met or list
DM pins need to be part of the write DQS/DQ required actions for compliance.
group.
See Note (5-4).
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues mem_clk[n:0] and If you are using single-ended DQS signaling, Verify Guidelines have been met or list
mem_clk_n[n:0] place any unused DQ or DQS pins with required actions for compliance.
DIFFOUT capability in the same bank or on
the same side as the data pins. If you are See Note (5-4).
using differential DQS signaling, place any
unused DQ or DQS pins with DIFFOUT
capability for the mem_clk[n:0] and
mem_clk_n[n:0] signals (where n>=0).
Do not place CK and CK# pins in the same
group as any other DQ or DQS pins.
If there are multiple CK and CK# pin pairs,
place them on DIFFOUT in the same single
DQ group of adequate width.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues clock_source Input clock pin to the DDR2 core PLL – Verify Guidelines have been met or list
required actions for compliance.
FPGA DDR2 interface:
Dedicated PLL clock input pin with direct (not
using a global clock net) connection to the
PLL and DLL required by the interface.
HPS DDR2 interface :
The SDRAM interface PLL input clock must
be sourced from HPS_CLK1 or HPS_CLK2.
Altera does not check this.
An important recommendation is to use a low
jitter clock source. See the recommendations
for Memory Output Clock Jitter in the Arria V
Datasheet. Altera does not check this.
Address Any user I/O pin. To minimize skew, you Verify Guidelines have been met or list
should place address and command pins in required actions for compliance.
the same bank or side of the device as the
following pins: See Note (5-4).
? mem_clk* pins.
? DQ, DQS, or DM pins.
Command Any user I/O pin. To minimize skew, you Verify Guidelines have been met or list
should place address and command pins in required actions for compliance.
the same bank or side of the device as the
following pins: See Note (5-4).
? mem_clk* pins.
? DQ, DQS, or DM pins.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Reset Dedicated clock input pin. (high fan-out signal) Verify Guidelines have been met or list
The reset pin can alternatively be generated. required actions for compliance.
Ensure the DDR3 IP closes reset
Recovery/Removal timing in Report DDR.
RZQ Used for the implementation of calibrated Verify Guidelines have been met or list
OCT for the memory interface pins. required actions for compliance.
RZQ should be in any 1.8V VCCIO bank.
Make sure that the VCCIO of your DDR2
interface bank and the VCCIO of the bank
with RZQ pin match.
If the RZQ pins are used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Notes:
5-4. Arria V GX Hard Memory Interfaces and Arria V SoC HPS SDRAM Interfaces have pre-assigned pins for DDR2 SDRAM interfaces.
Additional Comments:
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Part D: DDR2
Termination
Guidelines
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Memory clocks @ Memory clocks use Unidirectional class I Verify Guidelines have been met or list Memory termination. They are typically differentially required actions for compliance.
terminated with an effective 100-Ω resistance.
See Note (5-5).
For DIMM no termination is required as
termination is placed on the DIMM itself.
Memory clocks@ Use series 50-Ω output termination without Verify Guidelines have been met or list FPGA calibration on the FPGA side. Source required actions for compliance.
_pin_assignments.tcl file to
make these assignments automatically. See Note (5-5).
DQS @ Memory Use ODT for DDR2. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-5).
DQS @ FPGA Use parallel 50-Ω with calibration as input Verify Guidelines have been met or list
termination. Use series 50-Ω with calibration required actions for compliance.
as output termination. Source
_pin_assignments.tcl file to See Note (5-5).
make these assignments automatically.
DQ @ Memory Use ODT for DDR2. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-5).
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
DQ @ FPGA Use parallel 50-Ω with calibration as input Verify Guidelines have been met or list
termination. required actions for compliance.
Use series 50-Ω with calibration as output
termination.
Source_pin_assignments.tcl
file to assign these assignments
automatically.
DM@ Memory Use ODT for DDR2. Verify Guidelines have been met or list
required actions for compliance.
If DM pins are unused, refer to the DDR2
manufacturer's data sheet for connection See Note (5-5).
recommendations. Typically they must be tied
low using a resistor no greater than 4*Rtt (the
nominal ODT value used by the memory
device).
DM @ FPGA Use series 50-Ω with calibration as output Verify Guidelines have been met or list
termination. Source required actions for compliance.
_pin_assignments.tcl file to
make this assignment automatically.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues Address [BA, Unidirectional class I termination. For multi-Verify Guidelines have been met or list
mem_addr] @ Memory loads Altera recommends the ideal topology is required actions for compliance.
a balanced symmetrical tree. Altera
recommends that the class I termination to See Note (5-5).
VTT is placed:
? At the DIMM connector (for interfaces using
DIMMs).
? At the first split or division of the
symmetrical tree for discrete devices.
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in de-rated interface
performance.
Address [BA, Use maximum current strength as the output Verify Guidelines have been met or list
mem_addr] @ FPGA drive strength. Source required actions for compliance.
_pin_assignments.tcl file to
make this assignment automatically.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Command [CKE, Unidirectional class I termination. For multi-Verify Guidelines have been met or list CS_N, ODT, RAS, loads Altera recommends the ideal topology is required actions for compliance. CAS, WE_N]@ a balanced symmetrical tree. Altera
Memory recommends that the class I termination to See Note (5-5).
VTT is placed:
? At the DIMM connector (for interfaces using
DIMMs).
? At the first split or division of the
symmetrical tree for discrete devices.
Nonsymmetrical topologies or DIMMs result in
over or undershoot and oscillations on the
line, which may require compensation
capacitors or a lower than ideal drive strength
to be specified resulting in de-rated interface.
Command [CKE, Use maximum current strength as the output Verify Guidelines have been met or list CS_N, ODT, RAS, drive strength. Source required actions for compliance. CAS, WE_N]@ FPGA _pin_assignments.tcl file to
make this assignment automatically.
Notes:
5-5. The termination schemes suggested in the table are general guidelines. You should do board level simulation for your particular system/board to determine optimal termination scheme.
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Miscellaneous
Pin Description Schematic Name Connection Guidelines Comments/ Issues
Vref Use voltage regulator to generate this voltage. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-6).
Vtt Use voltage regulator to generate this voltage. Verify Guidelines have been met or list
required actions for compliance.
See Note (5-6).
RZQ RZQ pin is connected to GND through an Verify Guidelines have been met or list
external 240-Ω or 100-Ω ?1% resistor. Refer required actions for compliance.
to I/O Features in Arria V Devices (PDF) for
the OCT impedance options for the desired
OCT scheme.
If the RZQ pin is used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Notes:
5-6. This worksheet does not calculate required decoupling, it is expected the designer will select decoupling based on analysis of power required and impedance of power path required based on static and switching current values. Refer to Altera’s Power Delivery Network (PDN) Tool for Arria V Devices for further information.
Capacitance values for the power supply should be selected after consideration of the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and
voltage drop requirements of the device/supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to “Equivalent Series Inductance” of the mounting of the packages. Proper board design
techniques such as interplane capacitance with low inductance should be considered for higher frequency decoupling.
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Additional Comments:
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Part E: LPDDR2
Interface Pins
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Data pins - DQ Place it on DQ pins of the DQ/DQS group. Verify Guidelines have been met or list
The order of the DQ bits within a designated required actions for compliance.
DQ group/bus is not important.
See Note (5-7).
Data strobe - Differential DQS - Should be placed on Verify Guidelines have been met or list DQS/DQSn corresponding DQS and DQSn pins of the required actions for compliance.
DQ/DQS group.
See Note (5-7).
Data Mask DM Place it on one of the DQ pins in the group. Verify Guidelines have been met or list
DM pins need to be part of the write DQ/DQS required actions for compliance.
group.
See Note (5-7).
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues mem_ck[n:0] and Place on any unused DQ or DQS pins with Verify Guidelines have been met or list
mem_ck_n[n:0] DIFFOUT capability for the mem_clk[n:0] and required actions for compliance.
mem_clk_n[n:0] signals (where n>=0).
See Note (5-7).
Do not place CK and CK# pins in the same
group as any other DQ or DQS pins.
If there are multiple CK and CK# pin pairs,
place them on DIFFOUT in the same single
DQ group of adequate width.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues clock_source Input clock pin to the LPDDR2 core PLL – Verify Guidelines have been met or list
required actions for compliance.
FPGA LPDDR2 interface:
Dedicated PLL clock input pin with direct (not
using a global clock net) connection to the
PLL and DLL required by the interface.
HPS LPDDR2 interface :
The SDRAM interface PLL input clock must
be sourced from HPS_CLK1 or HPS_CLK2.
Altera does not check this.
An important recommendation is to use a low
jitter clock source. See the recommendations
for Memory Output Clock Jitter in the Arria V
Datasheet. Altera does not check this.
Address/Command The LPDDR2 command code includes the Verify Guidelines have been met or list
address, cs_n and cke signals. required actions for compliance.
Any DDR-capable I/O pin. DDR capable pins See Note (5-7).
include pins that are in a DQ/DQS group and
the 4 additional pins that make up the 16 pin
group. Refer to the device pin tables for
further information.
To minimize skew, you should place address
and command pins in the same bank or side
of the device as the following pins :
? CK/CK#
? DQ. DQS, or DM pins.
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Reset Dedicated clock input pin. (high fan-out signal) Verify Guidelines have been met or list
The reset pin can alternatively be generated. required actions for compliance.
Ensure the LPDDR2 IP closes reset
Recovery/Removal timing in Report DDR.
RZQ Used for the implementation of calibrated Verify Guidelines have been met or list
OCT for the memory interface pins. required actions for compliance.
RZQ should be in any 1.2V VCCIO bank.
Make sure that the VCCIO of your LPDDR2
interface bank and the VCCIO of the bank
with RZQ pin match.
If the RZQ pins are used for standard non
external memory interfaces, refer to section
“Dedicated and Dual purpose pins” for
connection guidelines.
Notes:
5-7. Arria V GX Hard Memory Interfaces and Arria V SoC HPS SDRAM Interfaces have pre-assigned pins for DDR2 SDRAM interfaces
Additional Comments:
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Part F: LPDDR2
Termination
Guidelines
Plane/Signal Schematic Name Connection Guidelines Comments / Issues
Memory clocks @ Memory clocks use Unidirectional class I Verify Guidelines have been met or list Memory termination. They are typically differentially required actions for compliance.
terminated with an effective 100-Ω resistance.
See Note (5-8).
Memory clocks@ Use series 34-Ω output termination with Verify Guidelines have been met or list FPGA calibration on the FPGA side. Source required actions for compliance.
_pin_assignments.tcl file to
make these assignments automatically. See Note (5-8).
DQS @ Memory LPDDR2 does not use ODT. Typically an Verify Guidelines have been met or list
LPDDR2 memory component has a 240 ohm required actions for compliance.
resistor connected between its ZQ pin and
GND or VDDCA to allow mode register See Note (5-8).
programming of the driver output impedance.
Refer to the LPDDR2 SDRAM data sheet for
further information.
DQS @ FPGA Use series 34-Ω with calibration as output Verify Guidelines have been met or list
termination. Source required actions for compliance.
_pin_assignments.tcl file to
make these assignments automatically. See Note (5-8).
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Plane/Signal Schematic Name Connection Guidelines Comments / Issues
DQ @ Memory LPDDR2 does not use ODT. Typically an Verify Guidelines have been met or list
LPDDR2 memory component has a 240 ohm required actions for compliance.
resistor connected between its ZQ pin and
GND or VDDCA to allow mode register See Note (5-8).
programming of the driver output impedance.
Refer to the LPDDR2 SDRAM data sheet for
further information.
DQ @ FPGA Use series 34-Ω with calibration as output Verify Guidelines have been met or list
termination. required actions for compliance.
Source_pin_assignments.tcl
file to assign these assignments
automatically.
DM@ Memory LPDDR2 does not use ODT. No termination Verify Guidelines have been met or list
is recommended at the memory component. required actions for compliance.
See Note (5-8).
DM @ FPGA Use series 34-Ω with calibration as output Verify Guidelines have been met or list
termination. Source required actions for compliance.