ram是什么

ram是什么 ARM (Advanced RISC Machines) is a well-known enterprise in the microprocessor industry. It has designed a large number of high-performance, cheap and energy consuming RISC processors, related technologies and software. The utility model has the advantages of high performance, low cost and low energy consumption. Apply to a variety of fields, such as embedded control, consumer / educational multimedia, DSP and mobile applications. ARM licensed its technology to many of the world's leading semiconductor, software and OEM vendors, and each vendor received a unique set of ARM related technologies and services. With this partnership, ARM quickly became the founder of many global RISC standards. At present, a total of 30 semiconductor companies and ARM signed a licensing agreement for hardware technology, including Intel, IBM, LG semiconductor, NEC, SONY, Philip and national semiconductor such a large company. As for the software system partners include Microsoft, Sun Microsystems and MRI and a series of well-known companies. The ARM architecture is the first RISC microprocessor designed for a low budget market. ARM, the abbreviation of Advanced RISC Machines, can be considered either a company name or a generic term for a class of microprocessors, and can also be considered a technical name. In April 26, 1985, the first ARM prototype was created at Acorn computer Ltd in Cambridge, England, and was manufactured by SanJoseVLSI technology, California, USA. In the late 1980s, ARM quickly developed into Acorn desktop products to form the UK's computer education base. In 1990, the Advanced RISC Machines Limited (later referred to as ARM, Limited, ARM) was established. In 1990s, ARM 32 bit embedded RISC (Reduced lnstruction Set Computer) processor extended to the world, occupying the leading position of low power consumption, low cost and high performance embedded system applications. ARM neither sells chips nor sells chips; it sells only wafer technology licensing. [edit this section of]ARM learning and development, which software need to learn? To sum up, the most important are the following 1 ADS tune trial ADS+AXD, to be exact. ADS contains AXD. Originally used SDT, then ARM company stopped supporting SDT, changed to support ADS, or use ADS. Some people still program released the SDT version, but can be found in the corresponding ADS, people here do not fameng. ADS is the compiler, and AXD is the debugger. Compile it into AXF and debug it in ARM's RAM. 2 FLASHPGM FLASH burn software. AXF debugging in RAM, no power, it is convenient to modify the program. Debugging procedures, and then go down to FLASH, power direct operation. Similar software, there are many, what FLUTED, and FLSHP are, but FLASHPGM is the best, and if anyone asks FLASH does not support BIN format file problems, it depends on my written FLASHPGM used. 3, BANYANT commissioning agent (do not know the name or not, from such a difficult to remember, I usually call it "half sheep", because it knows that it has just eaten a few days of roast sheep) Debugging agents use it to help you use simpler JTAG (cheaper) to implement most of the functionality of the JTAG emulator, which was originally sold by 1K. JTAG debugging principle, look at my other notes. Simple, you can understand him as you do, JTAG drive on the line. There are many types of debugging agents, what H-JTAG, and ARM7 (do not know what specific call, remember executable file called ARM7.EXE) are, BANYANT is better. It should be noted that each debugging agent installation method is simple, but not the same, you need to see instructions. And AXD runs before debugging. Save money. Don't worry about it. 4 ARM-ELF-TOOLS tool chain UCLINUX development tools used inside, such as ARM-ELF-GCC only class. A tool chain is one that makes many tools packaged together to make things easier for you to develop. Specific installation method, look at my another note. In addition, if you develop LINUX, you need to use ARM-LINUX-TOOLS, which is different and not common. 5 U-BOOT Famous BOOTLOADER generation tools, similar to VIVI seems to be (the name is ambiguous ~ ~!) The generated BOOTLOADER is burned into FLASH, and then you can use BOOTLOADER to download and burn the rest With BOOTLOADER, you can go to UCLINUX. BOOTLOADER is like BIOS on a computer. Of course, UCOS doesn't need it. I don't know what to do with it The latest version is 1.1.4, and I'll use another note to see how it works. 6 UCLINUX packs UCLINUX source package, needless to say, right? Suggest that you use the ready-made experience first, and then compile your own, cut. Because the editing of a separate UCLINUX is relatively simple, it involves a wide range of topics. 7 VMWARE Veteran virtual machine software, a virtual machine on a machine LINUX (PC), so you can not switch back and forth. Remember to install VMWARE-TOOLS and install the method in my next note. 8 source insight code editing tool Linux under the use of kscope [edit this paragraph,]ARM company profile In 1991, ARM was founded in Cambridge, England, which mainly sold the authorization of chip design technology. At present, the use of ARM technology intellectual property (IP) core microprocessor, known as a ARM microprocessor, has control over the industry, consumer electronics, communication system, network system, wireless systems and other kinds of products in the market, ARM technology based on microprocessor applications accounted for 32 bit RISC microprocessor for more than 75% of the market share, ARM technology is gradually infiltrated into every aspect of our lives. ARM company is specialized in RISC chip design and development company based on intellectual property rights, as the supplier itself is not directly engaged in chip production, depending on the transfer license from the company production design features of the chip, the world's major semiconductor manufacturers to buy the design of the ARM microprocessor core from ARM, according to their different application fields, adding the appropriate external circuit, thereby forming a ARM microprocessor chip own into the market. At present, dozens of major semiconductor companies around the world are using the ARM company's authorization, Therefore, ARM technology not only makes more third party tools, manufacturing and software support, but also reduces the cost of the whole system and makes it easier for the product to enter the market. It is accepted by the consumers and is more competitive. The three main features of ARM processor are: less power consumption, powerful function, 16 bit /32 bit, double instruction set and many partners. The strength of the ARM commodity model is that it has more than 100 partners worldwide (Partners). ARM is a design company that does not manufacture chips itself. Using the transfer license system, the production of chips by partners. Extensions to the current ARM architecture include: ? Thumb 16 bit instruction set, in order to improve code density; ? arithmetic operations instruction set for DSP DSP applications; Jazeller allows direct execution of Java bytecode. The solution provided by the ARM processor family is: ? open platform for wireless, consumer electronics and image applications; ? embedded, real-time systems for storage, automation, industry, and networking applications; Smart card and SIM card security applications. The ARM processor itself is a 32 bit design, but it is also equipped with a 16 bit instruction set. Memory generally saves 35% over equivalent 32 bit code, yet retains all the advantages of a 32 bit system. ARM Jazelle technology makes the Java accelerated Java virtual machine based on software (JVM) much higher performance, compared with the same non Java accelerate the nuclear power consumption is reduced by 80%. The CPU features an increased DSP instruction set, providing enhanced 16 bit and 32 bit arithmetic operations, and improved performance and flexibility. ARM also provides two cutting-edge features to aid debugging of highly integrated SoC devices with deep embedded processors, which are embedded ICE-RT logic and embedded tracking macro (ETMS) series. [edit this paragraph] kernel type Family architecture, kernel feature cache (I/D), /MMU, regular MIPS, application in MHz ARM1, ARMv1, ARM1, none ARM2 ARMv2 ARM2 Architecture 2 adds the MUL (multiplication) instruction without 4 MIPS @ 8MHz, Acorn, Archimedes, Chessmachine ARMv2a, ARM250, Integrated (full), MEMC (MMU), images, and IO processors. Architecture 2A joins the SWP and SWPB (permutation) instructions. No, MEMC1a 7, MIPS @ 12MHz, Acorn, Archimedes ARM3 ARMv2a ARM2a uses processor caches for the first time on the ARM architecture, both 4K 12 MIPS @ 25MHz Acorn Archimedes The ARM6 ARMv3 ARM610 V3 architecture pioneered support for addressing 32 bit memory (for 26 bits), 4K, 28, MIPS, @ 33MHz, Acorn, Risc, PC, 600, Apple, Newton ARM7TDMI ARMv4T ARM7TDMI (-S) three level pipeline, no 15 MIPS @ MHz, Game, Boy, Advance, Nintendo, DS,, iPod ARM710T are 8KB, MMU 36 MIPS, @ 40, MHz, Acorn, Risc, PC 700, Psion 5, series, Apple, eMate 300 ARM720T are 8KB, MMU 60, MIPS @ 59.8, MHz, Zipit ARM740T MPU ARMv5TEJ, ARM7EJ-S, Jazelle, DBX, none arm9tdmi armv4t arm9tdmi 五级流水线 无 arm920t 16kb / 16kb, mmu 200 mips @ 180 mhz armadillo, gp32, gp2x (第一颗内核), tapwave zodiac (motorola (mx1) arm922t 8kb / 8kb, mmu arm940t 4kb / 4kb, mpu gp2x (第二颗内核) arm9e armv5te arm946e s 可变动, tightly coupled memories, mpu nintendo ds, nokia n gageconexant 802.11 chips arm966e s 无高速缓存, tcms st micro str91xf, 包含ethernet [2] arm968e s 无高速缓存, tcms armv5tej arm926ej s jazelle dbx 可变动, tcms, mmu 220 mips @ 200 mhz 移动电话: sony ericsson (k, w系列), siemens 和 benq (x65 系列和新版的) armv5te arm996hs 无振荡器处理器 无高速缓存, tcms, mpu arm10e armv5te arm1020e (vfp), 六级流水线 32kb / 32kb, mmu arm1022e (vfp) 16kb / 16kb, mmu armv5tej arm1026ej s jazelle dbx 可变动, mmu or mpu xscale armv5te 80200 / iop310 / iop315 i / o处理器 80219 400 / 600mhz thecus n2100 iop321 600 bogomips @ 600 mhz iyonix iop33x iop34x 1 2核, raid加速器 32k / 32kb l1, 512k l2, mmu pxa210 / pxa250 应用处理器, 七级流水线 zaurus sl - 5600 pxa255 32kb / 32kb, mmu 400 bogomips @ 400 mhz gumstix, palm tungsten e2 pxa26x 可达 400 mhz palm tungsten t3 pxa27x 800 mips @ 624 mhz htc universal, sl zaurus c1000300031003200, dell axim x30, x50, 和 x51 系列 pxa800 (e) f monahans 1000 mips @ 1.25 ghz pxa900 blackberry 8700, blackberry pearl (8100) ixc1100 control plane processor ixp2400 / ixp2800 ixp2850 ixp2325 / ixp2350 ixp42x nslu2 ixp460 / ixp465 arm11 armv6 arm1136j (r) - simd, jazelle dbx (vfp), 八级流水 线 可变动, mmu. ? @ 532 - 665mhz (i.mx31 soc) nokia n93, zune, nokia n800 armv6t2 arm1156t2 (r) - simd, thumb - 2 (vfp), 九级流水线 可 变动, mpu armv6kz arm1176jz (r) - simd, jazelle dbx (vfp) 可变动, mmu + trustzone ARMv6K ARM11 MPCore 1-4 core symmetric multiprocessor, SIMD, Jazelle, DBX, (VFP) variable, MMU Cortex ARMv7-A Cortex-A8 Application profile, VFP, NEON, Jazelle RCT, Thumb-2, 13-stage pipeline, MMU+TrustZone up (L1+L2) in to 2000 (2 DMIPS/MHz from 600 MHz to more than 1 of the speed of GHz Texas Instruments OMAP3) ARMv7-R Cortex-R4 (F) Embedded profile, (FPU) variable cache, MMU optional 600 DMIPS Broadcom is a user ARMv7-M, Cortex-M3, Microcontroller, profile, no cache, (MPU) 120, DMIPS @ 100MHz, Luminary, Micro[3], microcontroller family Design document The design documents and emphasis on streamlining the rapid design, the whole circuit is not adopting microcode, as used in early 8 Acorn 6502 processor microcomputer. The ARM architecture contains the following RISC features: Read / storage architecture does not support unaligned memory access address (ARMv6 kernel has support) orthogonal instruction set (random access instruction addressing mode can access the data Orthogonal instruction set) a 16 * 32-bit (register file) 32 register array bits operation code (opcode) fixed length encoding, reduce quantity of generated and reduce the decoding and pipelined burden. Most of them are executed with a CPU cycle. To reinforce this simple design, some special designs are added to the processors of the same time, such as Intel 80286 and Motorola 68020: Most instructions can be executed in a conditional way to reduce the load generated at the branch and compensate for the shortage of the branch predictor. Arithmetic instructions will only change the conditions in the encoding requirements (condition code) 32-bit barrel shifter (barrel shifter) can be used to perform arithmetic instructions and addressing most of the calculations without loss of effectiveness of powerful indexed addressing mode (addressing mode) simple but fast dual priority interrupt system, with a switchable register group in addition to the ARM in the design of fun things, is to use a 4-bit encoding ahead of each instruction, said each instruction execution is conditional type This greatly reduces the encoding bits used in memory access instructions; in other words, it avoids branching instructions on small narratives such as if. There is a standard example that cites Euclid's greatest common divisor algorithm: In the C programming language, the loop is: Int GCD (int i, int j) {while (I! = J (I) if > J I = J else); J = I; return I;} in ARM assembly language, cycle: Loop CMP Ri, Rj; set the condition "NE" (not to) if (I! = J); "GT" (greater than if) (I > J, or); "LT" (less than if) (I < J) SUBGT Ri, Ri, Rj; if the "GT" (greater than), I = I-J; SUBLT Rj, Rj, Ri; if the "LT" (below), j = J-I; BNE loop; if the "NE" (not to), Then go back to the loop, which avoids the branch between the then and the else clause. Another feature is the instruction set, the displacement (shift) and rotary (rotate) function and a "data processing" type instruction (between arithmetic, logic, and register the move), so for example, a C language description A = (J < 2); under ARM, can be reduced to only one word and one cycle can complete the instruction ADD, Ra, Ra, Rj, LSL, and #2, which results in more common ARM programs, can also be used more efficiently without the need for frequent memory access. Even when ARM is implemented at a generally slow rate, it performs well compared to more complex CPU designs. The ARM processor and some of the other RISC architectures are not often seen features, such as PC- (indeed relative addressing in ARM PC for the 16 register one) and increase or after increasing addressing mode. Other considerations are that the ARM processor will increase its instruction set over time. Some of the early ARM processor (earlier than ARM7TDMI), the number, for example may not have instructions can read two Bytes so, strictly speaking, to generate code for these processors, it is impossible to deal with the data such as the use of "volatile short" type of C language object. ARM7 and most of the earlier designs have three stage pipelining (Pipeline): fetch instruction, decode, and execute. Higher efficiency designs, such as ARM9, have five stages of pipelining. Additional ways of improving performance include a faster adder and a wider branch of predictive logic circuitry. This architecture uses the coprocessor to provide a non-invasive way to extend instruction sets that can be addressed by software instructions such as MCR, MRC, MRRC, and MCRR. The coprocessor space logic is often divided into 16 co processor number respectively from 0 to 15, and fifteenth co processor (CP15) is reserved for some of the commonly used control function, as is the use of cache and memory management unit (if included in the processor). In the ARM architecture machine, peripheral devices connected to the processor, usually through the device entity register corresponding to the ARM memory space, the coprocessor space, or is connected to another device connected to the processor in order (such as bus). The latency of the coprocessor is low, so some peripheral devices (such as the XScale interrupt controller) are designed to be accessed in different ways (via memory and coprocessor). Thumb The newer ARM processor has a 16-bit instruction pattern, called Thumb, which may be related to the execution of 4 instructions per conditional instruction. In Thumb mode, the smaller opcode has less functionality. For example, only branches can be conditional, and many opcode cannot access all CPU registers. However, shorter opcode provides overall better coding density (Note: the space in which the code takes up memory), even though some operations require more instruction. Especially when the memory port or bus width is limited to less than 32, Shorter Thumb opcode can be more effective in using limited memory bandwidth, thus providing better performance than 32 bit code. Typical embedded hardware only has a smaller 32-bit datapath addressing range and other narrower 16 bits addressing (e.g., Game, Boy, Advance). In this case, the feasible scheme is usually compiled into Thumb code, and to the best use of some (non Thumb) CPU program area 32 bit instruction set, which can take the 32-bit bus width of them in a limited memory. The first processor with Thumb technology is ARM7TDMI. All ARM9 and later families, including XScale, were included in the Thumb technology. Jazelle ARM also developed a technology, Jazelle DBX (Direct Bytecode eXecution), allowing them to accelerate the implementation of Java bytecode in some architectures, such as other execution mode, when the call to support some special software bytecodes, accelerate the implementation can provide some bytecodes. It can execute each other between existing ARM and Thumb patterns. The first processor with Jazelle technology is ARM926EJ-S:Jazelle, which is marked with an English letter "'J'" in the CPU name. It has enabled mobile phone manufacturers to speed up the implementation of Java ME games and applications, thus contributing to the continued development of the technology. Thumb-2 Thumb-2 technology first appeared in the ARM1156 kernel, and was published in 2003. Thumb-2 extends the restricted 16-bit Thumb instruction set to allow the instruction set to be used more widely with additional 32-bit instructions. As a result, Thumb-2's intended goal is to achieve near Thumb coding density, but can demonstrate near ARM instruction set performance in 32-bit memory. Thumb-2 has also produced a variety of instructions from the ARM and Thumb instructions, including bit field (bit-field) operations, branches (table), and conditional execution. Thumb Execution Environment (ThumbEE) ThumbEE, the so called Thumb-2EE, which the industry calls Jazelle RCT technology, was published in 2005, first seen in the Cortex-A8 processor. ThumbEE provides some extended from Thumb-2, in which the execution environment (Execution Environment), which is especially suitable for the instruction set to the implementation stage (Runtime) of the encoding (e.g. time compilation). Thumb-2EE is designed for some languages such as Limbo, Java, C#, Perl, and Python, and enables real-time compilers to output smaller compilers without affecting performance. New features provided by ThumbEE, included in each access instruction automatically check invalid index, and an array can perform a range check instruction, and can branch to the classifier (handlers), which contains a small part of the regular call encoding, usually used for implementation of high order language functions, such as memory allocation of a new object. Advanced SIMD (NEON) Advanced SIMD extensions, the industry calls NEON technology, It is a combination of 64 and 128 bit SIMD (Single, Instruction, Multiple, Data, single instruction, multiple data) instruction sets, which has the ability to standardize acceleration for multimedia and signal processing programs. NEON can perform MP3 sound decoding on the 10 MHz CPU, and can perform GSM AMR (Adaptive, Multi-Rate) speech coding below 13 MHz frequencies. NEON has a wide set of instruction sets, individual register arrays, and independently executed hardware. NEON supports integer and single precision floating point data for 8-, 16-, 32-, and 64-bit, and performs operations in SIMD with respect to the voice / video portion of graphics and game processing. SIMD is a decisive element in the vector processor, which has simultaneous multiple processing functions. In NEON technology, SIMD can support up to 16 simultaneous calculations. VFP VFP is a derivative technology for ARM architectures in cooperative processors. It provides low cost, single precision, and precision floating-point arithmetic capabilities, and is completely compatible with ANSI/IEEE Std 754-1985 binary floating point arithmetic standards. VFP provides most of the applications for floating-point applications such as PDA, smart phones, voice compression and decompression, 3D images and digital sound effects, printers, computer boxes, and automotive applications. The VFP architecture also supports SIMD (single instruction, multiple data) parallelization of short vector instruction execution. This is very useful in image and signal processing applications, such as reducing coding size and increasing output efficiency. In ARM-based processors, other visible floating-point or SIMD co processors also include the FPA, FPE, and iwMMXt. They provide functions similar to VFP, but they are not compatible on the opcode level. Security extension (TrustZone) TrustZone (TM) technology appears in ARMv6KZ and later application core architectures. It provides a low cost solution for adding single security cores to the system's single chip (SoC), supported by a hardware based access control scheme, to support two virtual processors. This way can make the application core to switch between the two states (usually called the domain (Worlds) and other functional areas to avoid name confusion), under this architecture can avoid the information from the core areas of a reliable leak to the relatively unsafe areas. Switching between this kernel domain is usually completely unrelated to the other functions of the processor, so that each field can operate independently but still use the same kernel, orthogonal. Memory and peripheral devices can also be used to understand the current field of kernel operations and provide access control for device confidentiality and coding in this manner. A typical TrustZone technology application is designed to perform the operating system entirely in a secure environment and to have less secure coding in a trusted environment. [edit this paragraph]ARM authorized party ARM itself does not manufacture or sell CPU by its own design, but authorizes the processor architecture to interested manufacturers. ARM offers a variety of licensing terms, including price and dissemination. For the licensee, ARM provides an integrated hardware description of the ARM kernel, including the complete software development tools (compilers, debugger, SDK), and sales rights for the ARM CPU silicon chip. For the fabless authorized party, the hope can be integrated into the ARM kernel of their own research and development of chip design, and usually only to get a production ready IP core (IP Core) certification. For these customers, ARM will release the selected ARM core gate circuit diagram, along with abstract simulation models and test programs to assist in design, integration, and verification. More customers, including integrated component manufacturers (IDM) and wafer manufacturers, are required to acquire the processor's intellectual property rights (IP) in the form of synthetic RTL (register transfer hierarchy, such as Verilog). By integrating the RTL, the customer has the ability to optimize and reinforce the architecture. This way can make designers to complete additional design objectives (such as high oscillation frequency, low loss of energy, instruction set extension) and not limited to not change the circuit diagram. Although ARM does not grant the Licensee the right to sell the ARM architecture itself, the licensee can sell the product at will (e.g. chips, components, evaluation boards, complete systems, etc.). Commercial Fabs are a special example because they not only sell silicon products that sell ARM kernels, but they also retain the right to rework the ARM kernel for other customers. Like most IP sellers, ARM determines the selling price of IP in terms of its use value. On the architecture, the more inefficient ARM kernel has lower licensing fees than the higher performing kernel. In the implementation of silicon chips, an integrated kernel is more expensive than a hardware macro (black box) kernel. For more complex price issues, ARM licensed commercial Fabs (such as Samsung and Fujitsu, Japan) can offer lower licensing prices to their fabs customers. Through wafer fab's own design technology, customers can obtain ARM kernel with lower or free ARM prepaid license fees. Compared to specialized semiconductor wafers (such as TSMC and TSMC) that do not have their own design technology, Fujitsu / Samsung charges two to three times more for each wafer. For a small number of applications, the wafer fab with the design department offers a lower overall price (through licensing fees). For mass production, special wafer fabs have become a better choice as a result of long-term cost reductions, resulting from lower wafer prices and reduced ARM costs for NRE. Many semiconductor companies hold ARM: Atmel, Broadcom, Cirrus authorized Logic and Freescale (in 2004 from Motorola, Fujitsu, Intel independent) (complaint mediation by Digital), IBM, Infineon, Nintendo, NXP semiconductors (independent from PHILPS in 2006), OKI electrical industry, Samsung Electronics, Sharp TI, STMicroelectronics, and VLSI etc. many of these companies have different forms of ARM authorization. Although ARM's licensing program is covered by confidentiality contracts, it is in the intellectual property industry, ARM is one of the most expensive CPU cores that are widely known. A single customer product, including a basic ARM kernel, may require an authorization fee of up to $200 thousand. And if it involves a lot of structural modifications, then the cost could be more than $10 million. Recommend you to learn ARM portal site www.arm16.com Reference: www.arm16.com