10B-Stratix_II_Overview

nullStratix II FPGAsStratix II FPGAsThe Stratix II & Stratix Device FamiliesThe Stratix II & Stratix Device FamiliesNew Levels of System IntegrationStratix II & Stratix DensityStratix II & Stratix Density(1) Equivalent Logic ElementsStratix II & Stratix Ordering CodeStratix II & Stratix Ordering CodeEP2S Stratix II Family Signature (EP1S: Stratix) 15 Approximate LE Count of Device * 1000 F Package Type (F = FineLine BGA, R = RQFP...) 1020 Pin Count (Number of Pins on Package) C Operating Temperature (Commercial, Industrial) 5 Speed Grade (5, 6, 7) (Smaller Speed Grade = Faster Device) ES Optional Suffix (Ex. ES = Engineering Sample)EP2S15F1020C3ESStratix II Packaging & User I/O PinsStratix II Packaging & User I/O PinsStratix Package Offerings & User I/OStratix Package Offerings & User I/OEP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80345 426 47335 x 35 683 683 683 68340 x 40345 426 47327 x 27426 586 597 597 61529 x 29 706 726 773 773 77333 x 33 822 1,022 1,20340 x 40Device672-Pin BGA Wire-Bond 1.27 mm956-Pin BGA Flip-Chip 1.27 mm672-Pin FBGA Wire-Bond 1.0 mm780-Pin FBGA Flip-Chip 1.0 mm1020-Pin FBGA Flip-Chip 1.0 mm1508-Pin FBGA Flip-Chip 1.0 mm Vertical Migration Supported484-Pin FBGA Flip-Chip 1.0 mm335 36123 x 23Stratix II and Stratix LayoutStratix II and Stratix LayoutPhase-Locked LoopsEP1S40EP2S60Stratix II Feature OverviewStratix II Feature OverviewHierarchical Clock Nets Logic Structure & Interconnects TriMatri Memory DSP Blocks I/O Elements & External Memory Interfaces High Speed Differential I/O Clock Management & PLLs ConfigurationHierarchical ClockingHierarchical ClockingDesigned to Minimize Skew Two Types 16 Device Global Clocks 32 Regional Clocks Use As Other High Fan-Out Control Signals Examples Asynchronous Clear & Preset Synchronous Clear & Load Clock Enable Can Drive Adjacent Regional Networks from Same SourceCLK[3..0]CLK[15..12]CLK[11..8]CLK[7..4]Global Clock NetworksCLK[1..0]CLK[15..14]Regional Clock NetworksMultiTrack InterconnectMultiTrack InterconnectHierarchical Series of Routing Channels All-Layer Copper 2 Types of Fixed Length Row & Column Channels Continuous Interconnects with a Specific RegionTriMatrix MemoryTriMatrix MemoryMore Data Bits for Larger Memory Buffering 512 Kbits per Block Max. 144 Bits Wide Up to 9 Blocks M-RAM BlockDSP BlocksDSP BlocksUp 96 DSP Blocks Each Configured for (8) 9x9 Multipliers (4) 18x18 Multipliers (1) 36x36 Multiplier Can Be Cascaded for Larger Operations Dedicated Configurable Math Circuitry Multiplier, Accumulate & Addition/Subtraction Rounding & Saturation Built-In Shift Register for Complete FIR Filter Implementation Selectable Input, Output & Pipeline Stage RegistersDSP Block ArchitectureDSP Block ArchitectureAdd/Sub/AccSummation UnitOutput RegisterXXXX+Input RegisterPipeline RegisterOutput MuxI/O ElementsI/O ElementsTo/From CoreBi-directional PinLATCHVcc0 1General I/O FlowDDR I/O FlowExternal Memory Support (Stratix II)External Memory Support (Stratix II)High-Speed Differential I/O TechnologyHigh-Speed Differential I/O TechnologySupport for LVDS, HyperTransport Up to 156 Receiver & 152 Transmitter Channels per Device Optimized for 1-Gbps Performance Implemented in Dedicated Circuitry Differential I/O Buffers Data Realignment Circuitry Phase Synchronizer Circuitry Dynamic Phase Alignment Serializer/Deserializer Fast PLLs On-Chip Termination1 Gbps1 GbpsInput ClockOutput ClockPLL FeaturesPLL FeaturesUp to 12 PLLs Up to 48 PLL Outputs Two Types Enhanced PLLs Fast PLLsStratix II Device ConfigurationStratix II Device ConfigurationDesign Security Remote & Local Update Modes Up to 800 Mbps Configuration Speeds Compression Design Security in Stratix IIDesign Security in Stratix IINEW Design Security Feature in Stratix II FPGAs Uses AES Technology 128-bit One-Time Programmable Non-Volatile Key Stored in FPGA Encrypted Configuration File Stored in External Memory Encrypted Configuration Data is Decrypted in real-time by FPGA using Security Key Supported in FPP, AS and PS SchemesRemote & Local UpdateRemote & Local UpdateStratix II Device Can Be Configured With Remotely Updated Configuration Information Supports A Single ‘Safe’ Factory and Up to 7 Application Configurations(1) Local Update Only Supports A Single Application ConfigurationRemote SourceStratix DeviceApplication Configuration DataConfiguration Device or Intelligent HostApplication Data 1 (1)Application Data 7Factory DataApplication or Factory Configuration DataApplication Configuration DataConfiguration Control SignalsWatchdog CircuitryStratix II Device FamilyStratix II Device FamilyStratix II vs. StratixStratix II vs. StratixYesYesRemote System UpgradesConfigurationYesNoFast Regional ClockR4, R8, R24, C4, C8, C16R4, R24 C4, C16InterconnectsYesNoFCRAM, ZBT, External Memory Regular I/ODedicated CircuitryQDRII SupportNoYesDesign Security4-input LEsALMsLogicLogic Structure & InterconnectsDSP BlocksTypeNoYesDynamic Mode SwitchingNoYesMixed ModeNoYesRounding & SaturationStratix Stratix IIFeatureNOYesCompressionStratix II vs. StratixStratix II vs. StratixPLL speed numbers for -5 parrtsMemory ComparisonMemory ComparisonLogic & DSP BlocksLogic & DSP Blocks(1) Equivalent Logic Elements