Quartus常见错误

Quartus常见错误 1. Error (10028): Can't resolve multiple constant drivers for net …… 解析：不能在两个以上always内对同一变量赋值，这个细节一般看看会看到，但是编程时，就是没想到。 2. Error (10158): Verilog HDL Module Declaration error at clkseg.v(1): port "XXXX" is not declared as port 解析：大意了，端口类型还没定义啊！ 3. Error (10110): variable "en" has mixed blocking and nonblocking Procedural Assignments -- must be all blocking or all nonblocking assignments 解析:en在程序中有时用非阻塞赋值，有时用阻塞赋值，这是禁止的。在初学的时候，可能分得不是很清楚，所以在检查时，一定要一步步观察慢慢来。 4. 4.Error (10161): Verilog HDL error at clkseg.v(36): object "count" is not declared 解析：这个错误应该很明显啦，只要能读得懂。 5．．．．Error (10170): Verilog HDL syntax error at clkseg.v(37) near text "***"; expecting ";" 解析：意思应该也很简单，就是检查的时候要细心点。 6.Error (10171): Verilog HDL syntax error at ir_ctrl.v(149) near end of file ; expecting an identifier, or "endmodule", or a parallel statement 解析：最后上了endmodule。一般编程的程序长了，到最后也就容易忘记。 7.Error (10278): Verilog HDL Port Declaration error at ir_ctrl.v(11): input port "ir" cannot be declared with type "" 解析：在Altra官网中就有该解释 http://www.altera.com.cn/support/kdb/solutions/rd03102006_162.html 官网上有很多东西值得我们发现学习。 8. 8.Error (10137): Verilog HDL Procedural Assignment error at test.v(24): object "check_9ms" on left-hand side of assignment must have a variable data type 解析：在Altra官网中就有该解释 http://www.altera.com.cn/support/kdb/solutions/rd06232003_8783.html 9.Error (10219): Verilog HDL Continuous Assignment error at clk_div.v(26): object "clkdiv_equ" on left-hand side of assignment must have a net type 解析：看得懂英语就懂了。 10.Error (10200): Verilog HDL Conditional Statement error at clk_div.v(22): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct 解析：看看官网的解释 http://www.altera.com.cn/support/kdb/solutions/rd06242003_6128.html 条件判断语句逻辑不匹配。always @ （） 括号内的敏感信号，与begin end 块中的判断语句逻辑不匹配。 例如 always @ （negedge xxx） begin if(xxx) .... end 敏感信号列表中判断的是xxx的下降沿，但是if语句判断的xxx是否为“1”，这样if语句将永远不可能执行，不符逻辑 解决方法：注意always @ 括号内的敏感信号列表，到底是上升沿还是下降沿，还是两个都要，根据不同场合选择合适的敏感信号 11.Error (10231): Verilog HDL error at LCD1602.v(40): value cannot be assigned to input "lcd_en" 解析:端口设置出错 12.Error (10137): Verilog HDL Procedural Assignment error at LCD1602.v(49): object "lcd_rs" on left-hand side of assignment must have a variable data type 解析：http://www.altera.com.cn/support/kdb/solutions/rd06232003_8783.html 13.Error (10170): Verilog HDL syntax error at test_vga.v(57) near text "<"; expecting "<=", or "=" 即这里产生的错误。 解析：一个空格，不小心分开了，而且有人喜欢把<=分开来写，这个在QUANRUS是不允许的呃。。。 14.Error: Application nios2-terminal on 127.0.0.1 is using the target device 解析：这种情况出现在JTAG模式下，你在使用NIOS下的JTAG功能（比如利用BLASTER进行在线仿真），同时你又想下载*.sof文件（就是在JTAG模式下下载程序）。简单说就是你的JTAG已经被占用了。解决办法就是关闭你正在使用的JTAG功能，然后再下载*.sof文件。初学者经常会犯这样的错误，一定要注意。 这里有http://www.cnblogs.com/kingst/archive/2010/05/04/1727613.html 15．Error (10818): Can't infer register for "dis_data[0]" at key_down.v(56) because it does not hold its value outside the clock edge 原因：赋值语句的逻辑混乱，由于条件判断语句采用了非阻塞赋值，容易产生逻辑混乱。 解决方法：将非阻塞赋值“<=”改成阻塞赋值“=”，并不是任何情况下都是用非阻塞赋值好，阻塞和非阻塞适用于不同环境，根据环境要求选择赋值方式 16.Warning (10230): Verilog HDL assignment warning at SMG_1S.v(21): truncated value with size 32 to match size of target (8) 原因：赋值语句的等号两端数据的位宽不一致。例如：sec <= sec + 1; sec定义是8位的寄存器型，而表达式中的“1”，默认为32位的十进制数，等式右边是32位数据，等式左边是8位变量，所以赋值时会有警告。 解决方法：把 "sec <= sec + 1; " 规范化，改写成" sec <= sec + 1'd 1 " 。 1. Warning: Found pins ing as undefined clocks and/or memory enables Info: Assuming node CLK is an undefined clock -=-----可能是说中产生的触发器没有使能端 2 Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list ----没把singal放到process（）中 3 Error: VHDL Interface Declaration error in clk_gen.vhd(29): interface object "clk_scan" of mode out cannot be read. Change object mode to buffer or inout. ------信号类型设置不对，out当作buffer来定义 4 Error: Node instance "clk_gen1" instantiates undefined entity "clk_gen" -------引用的例化元件未定义实体－－entity "clk_gen" 5 Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer 6 Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design. 7 Warning: VHDL Process Statement warning at divider_10.vhd(17): signal "cnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list -----缺少敏感信号 8 Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register 9 Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND 10 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details. 11 Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "sign" with clock skew larger than data delay. See Compilation Report for details. 12 Error: VHDL error at counter_clk.vhd(90): actual port "class" of mode "in" cannot be associated with formal port "class" of mode "out" ------两者不能连接起来 13 Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design. ------没有编写testbench文件，或者没有编辑输入变量的值 testbench里是元件申明和映射 14 Error: VHDL Binding Indication error at freqdetect_top.vhd(19): port "class" in design entity does not have std_logic_vector type that is specified for the same generic in the associated component ---在相关的元件里没有当前文件所定义的类型 15 Error: VHDL error at tongbu.vhd(16): can't infer register for signal "gate" because signal does not hold its outside clock edge 16 Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]" 17 Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node. ---"temp[19]"被优化掉了 18 Warning: Reduced register "gate~reg0" with stuck data_in port to stuck GND 19 Warning: Design contains 2 input pin(s) that do not drive logic Warning: No output dependent on input pin "clk" Warning: No output dependent on input pin "sign" ------输出信号与输入信号无关， 20 Warning: Found clock high time violation at 16625.0 ns on register "|impulcomp|gate1" 21 Error: VHDL error at impulcomp.vhd(19): can't implement clock enable condition specified using binary operator "or" 22 Error: VHDL Association List error at period_counter.vhd(38): actual parameter assigned to formal parameter "alarm", but formal parameter is not declared -------连接表错误，形参"alarm"赋值给实参，形参没定义，可能是形参与实参的位置颠倒了，规定形参在实参之前。 23 Error: Ignored construct behavier at period_counter.vhd(15) because of previous errors －－－－－－－－因为前一个错误而导致的错误 24 Error: VHDL error at period_counter.vhd(38): type of identifier "alarm" does not agree with its usage as std_logic type －－－－－－－－"alarm"的定义类型与使用的类型不一致 25 Error: VHDL error at shift_reg.vhd(24): can't synthesize logic for statement with conditions that test for the edges of multiple clocks -------同一进程中含有两个或多个if(edge)条件，（一个进程中之能有一个时钟沿） 26 Error: Can't resolve multiple constant drivers for net "datain_reg[22]" at shift_reg.vhd(19) 27 can't infer register for signal "num[0]" because signal does not hold its outside clock edge 28Error: Can't elaborate top-level user hierarchy 29 Error: Can't resolve multiple constant drivers for net "cs_in" at led_key.vhd(32) ----------有两个以上赋值语句，不能确定“cs_in”的值， 30 Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design. ---------------在源文件中找不到对应的节点“over”。 31 Error: Can't access JTAG chain 无法找到下载链 32 Info: Assuming node "clk" is an undefined clock