24进制计数器-VHDL

24进制计数器-VHDL --文件名:counter24.vhd。 --功能:24进制计数器。 --最后修改日期:2008.04.26 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter24 is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic_vector(5 downto 0); dout : out std_logic_vector(5 downto 0)); end counter24; architecture Behavioral of counter24 is signal count : std_logic_vector(5 downto 0); begin dout <= count; process(clk,reset,din) begin if reset= '0' then count <= din; elsif rising_edge(clk) then if count(3 downto 0)="1001" then count(3 downto 0)<="0000"; count(5 downto 4)<=count(5 downto 4) +1; else count(3 downto 0)<=count(3 downto 0)+1; end if; if count="100011" then count<="000000"; end if; end if; end process; end Behavioral;