www.cypress.com Document No. 001-70707 Rev. *D 1
AN70707
EZ-USB® FX3™ Hardware Design Guidelines and Schematic Checklist
Author: Rizwan Afridi, Hussein Osman
Associated Project: No
Associated Part Family: CYUSB3014
Software Version: N/A
Related Application Notes: None
AN70707 discusses recommended practices for EZ-USB
®
FX3™ hardware design and the critical items that a
developer must consider. The Cypress EZ-USB FX3 is the next generation USB 3.0 peripheral controller. With its
highly integrated and flexible features, developers can add USB 3.0 functionality to any system.
Contents
Introduction ....................................................................... 1
Power System ................................................................... 2
Overview ...................................................................... 2
Power Modes ............................................................... 3
Device Supply Decoupling............................................ 3
Inrush Current Consideration and Power
Supply Design .............................................................. 3
Clocking ............................................................................ 5
Crystal .......................................................................... 5
Clock ............................................................................ 6
Watchdog Timer ........................................................... 6
GPIF II Interface ................................................................ 6
I
2
C Interface ...................................................................... 6
Low Performance Peripherals (LPP) ................................. 7
JTAG ............................................................................ 7
I
2
S................................................................................. 7
SPI and UART .............................................................. 7
Booting .............................................................................. 7
EMI and ESD Considerations ............................................ 7
FX3 Device Package Dimensions ..................................... 8
Electrical Design Consideration ........................................ 8
USB 3.0 SuperSpeed Design Guidelines ..................... 8
Appendix A – PCB Layout Tips ....................................... 14
Introduction
The Cypress EZ-USB FX3 has an integrated USB 3.0 and
USB 2.0 physical layer (PHY), and a fully configurable,
parallel, general programmable interface called GPIF II,
which can connect to an external processor, ASIC, or
FPGA. EZ-USB FX3 enables data transfers up to
320 MBps from GPIF II to the USB interface.
To successfully add this high throughput pipe to a system,
a developer has to consider a number of critical items
when designing the system. Because of the packaging
and high-performance characteristics of the EZ-USB FX3
device, you should follow the guidelines for trace width,
stack up, and other layout considerations to make sure the
system will perform as expected.
A reference schematic for the EZ-USB FX3 DVK is
available at CYUSB3KIT-001 EZ-USB
®
FX3™.
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 2
Power System
Overview
The EZ-USB FX3 device CYUSB3014 power domains are shown in the block diagram in Figure 1. A description and the
voltage settings on each of these domains are provided in Table 1.
Figure 1. EZ-USB FX3 Power Domains Diagram
VBAT
VIO1
VIO2
VIO3
VIO4
VIO5
VDD
U3RXVDDQ
VBAT
0.01uF 0.1uF
VIO1
0.01uF 0.1uF
VIO2
0.01uF 0.1uF
VIO3
0.01uF 0.1uF
VIO4
0.01uF 0.1uF
VIO5
0.01uF 0.1uF
VDD
0.1uF22uF
U3RXVDDQ
0.1uF22uF
V
S
S
CVDDQ
0.01uF0.1uF
CVDDQ
AVDD
AVDD
0.1uF2.2uF
U3TXVDDQ
U3TXVDDQ
0.1uF22uF
VBUS
0.1uF
VBUS
A
V
S
S
U
2
A
F
E
U
3
V
S
S
U
2
P
L
L
Table 1. EZ-USB FX3 Power Domains Description
Parameter Description Min Typical Max Unit
VDD Core voltage supply 1.15 1.2 V typical 1.25 V
AVDD Analog voltage supply 1.15 1.2 V typical 1.25 V
VIO1 GPIF II I/O power domain 1.7 1.8, 2.5 and 3.3 V typical 3.6 V
VIO2 IO2 power domain 1.7 1.8, 2.5 and 3.3 V typical 3.6 V
VIO3 IO3 power domain 1.7 1.8, 2.5 and 3.3 V typical 3.6 V
VIO4 UART/SPI/I2S power domain 1.7 1.8, 2.5 and 3.3 V typical 3.6 V
VIO5 I
2
C and JTAG supply domain 1.15 1.2, 1.8, 2.5 and 3.3 V typical 3.6 V
VBATT USB voltage supply 3.2 3.7 V typical 6 V
VBUS USB voltage supply 4.0 5 V typical 6 V
CVDDQ Clock voltage supply 1.7 1.8, 3.3 V typical 3.6 V
U3TXVDDQ USB 3.0 1.2 V supply 1.15 1.2 V typical 1.25 V
U3RXVDDQ USB 3.0 1.2 V supply 1.15 1.2 V typical 1.25 V
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 3
Power Modes
EZ-USB FX3 supports different power modes:
Normal mode: This is the full functional operating
mode. In this mode the internal CPU clock and the
internal PLLs are enabled.
The I/O power supplies VIO2, VIO3, VIO4, and
VIO5 may be turned off when the corresponding
interface is not in use. VIO1 may not be turned off
at any time if the GPIF II interface is used in the
application.
VBATT is a power input to the USB PHY. It is
internally regulated to 3.3 V. When VBUS is
greater than 3.7 V, VBUS becomes the primary
supply to the USB circuitry unless there is a
software override. VBATT pin can be left open if
not used.
Suspend mode with USB 3.0 PHY enabled (L1):
Power supply for the wakeup source and core power
must be retained. All other power domains can be
turned off/on individually.
Suspend mode with USB 3.0 PHY disabled (L2):
Power supply for the wakeup source and core power
must be retained. All other power domains can be
turned off/on individually.
Standby mode (L3): Power supply for the wakeup
source and core power must be retained. All other
power domains can be turned off/on individually.
Core power down mode (L4): Core power is turned
off. All other power domains can be turned off/on
individually.
Device Supply Decoupling
Power supply decoupling is critical in ensuring that system
noise does not propagate into the device through the
power supply. Improper decoupling can lead to jittery
signaling, especially on the USB bus, which results in
higher CRC error rate and more retries. Decoupling
capacitors should be Ceramic type of a stable dielectric. It
is important to have the decoupling caps as close to the
power pins as possible and short trace runs for the power
and ground connections on the EZ-USB FX3 device to
solid power and ground planes. Figure 2 shows a sample
of decoupling caps placement.
Figure 2. Decoupling Caps Placements
Decoupling
Caps placed
close to the
device
The specific recommendation for the Ceramic capacitor
nearest to each EZ-USB FX3 power pin is given in
Table 2.
Table 2. Power Domain Decoupling Requirements
Cap Value Number of Caps Pin Name
22 uF, 0.01 uF
4 x 0.01 uF, 3 x 0.1 uF,
1 x 22 uF
VDD
0.1 uF, 2.2 uF 1 of each AVDD
0.1 uF, 22 uF 1 of each U3TXVDDQ
0.1 uF, 22 uF 1 of each U3RXVDDQ
0.1 uF, 0.01 uF 1 of each CVDDQ
0.1 uF, 0.01 uF 1 of each per supply VIO1-5
0.1 uF 1 VBUS
Inrush Current Consideration and Power
Supply Design
When the USB 3.0 Super Speed PHY is enabled for the
first time, or a reset event; an initial inrush current is
expected on the 1.2 V U3RXVDDQ and U3TXVDDQ
supplies for ~10 us. The magnitude of this current can be
as high as 800 mA. In order that this inrush current does
not cause the common 1.2 V supply to droop to
unacceptable levels, care must be taken in the design of
the power supply network for these supplies.
If the same 1.2 V supply is also used for the VDD core
supply, care must be taken to insure that the level on this
supply does not fall too low, as this has the potential to trip
the on-chip power-on reset (POR) circuit that will reset the
entire chip. The POR circuit can fire if the 1.2 V core VDD
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 4
voltage falls down to less than 0.83 V for more than
200 ns. The 1.2 V power network must be designed such
that the VDD does not drop below 0.83 V when an inrush
event occurs. Proper combination of decoupling capacitors
(as specified in the datasheet), inductor chokes and
regulator output impedance are required to make this
possible.
The following example waveforms show the inrush current
(Figure 4) and resultant drop in VDD levels (Figure 5)
when the current spike occurs. The results were obtained
from a non-optimized power supply design using
TPS76801QD power regulator, 2.2 uF decoupling caps
and chokes as shown in Figure 3.
Figure 3. Non-optimized Power Supply Design
U3RXVDDQ
U3TXVDDQ
VDD
FX3
0.1µF 2.2µF
0.1µF 2.2µF
0.1µF 2.2µF
Lchoke
Lchoke
Lchoke
Regulator
TPS76801QD
V1P2
Figure 4. Inrush Current (80 mV/0.1 Ω = 800 mA)
Figure 5. 1.2 V Power Domain Voltage Drop (200 mV)
In contrast, an optimized power design shown in Figure 6
below designed using the same regulator (TPS76801QD),
with the modification of using 22 uF decoupling capacitor
and removing the choke from VDD supply, shows a
reduction in the inrush (Figure 7) and an improvement in
the power supply drop (Figure 8).
Figure 6. Optimized Power Supply Design
U3RXVDDQ
U3TXVDDQ
VDD
FX3
0.1µF 22µF
0.1µF 22µF
0.1µF 22µF
Lchoke
Lchoke
Regulator
TPS76801QD
V1P2
Figure 7. Inrush Current (320 mA)
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 5
Figure 8. 1.2 V Power Domain Voltage Drop (112 mV)
Customers can choose any regulator with similar
specification.
Clocking
The EZ-USB FX3 device can use either a 19.2 MHz
crystal or any of 19.2 MHz, 26 MHz 38.4 MHz, or 52 MHz
clock as the clocking source.
Crystal
Figure 9 shows the connection of the crystal.
Figure 9. Crystal Circuit
The 19.2 MHz crystal requirements for is listed in Table 3.
Table 3. Crystal Requirements
Parameter Specification Unit
Tolerance ±100 ppm
Temp Range -40 to 85 °F
Load capacitance 12 pF
Drive level Use Equation-1 mW
The power dissipation of the crystal depends on the drive
level of the XTAL-OUT pin (for EZ-USB FX3 this is
1.32 V), the desired frequency (19.2 MHz) and the
equivalent resistance of the crystal.
Equation 1. Crystal Drive Level
A compatible crystal‟s drive level should not exceed the
power dissipation limitation of the crystal. Examples of
compatible crystals are shown in Table 4, it must be noted
that only the NX3225SA was characterized with the
EZ-USB FX3, and the rest for the crystals are provided as
example using the above equation.
Table 4. Crystal Selection
Device
Max R1
(Ohm)
from
datasheet
CL
eqv
(pF)
C0 (pF)
estimate
Drive
Level
using
equation
1 (uW)
Max
Drive
Level
(Spec)
uW
Epson FA-
H20
40 6 3 82 100
ITTI I16 80 6 3 171 300
NX2520SA 50 6 3 107 200
NX3225SA 50 6 3 107 200
Saronix-FL 40 6 3 82 100
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 6
Clock
Clock inputs to EZ-USB FX3 must meet the phase noise
and jitter requirements specified in the following table.
Table 5. Clock Requirements
Parameter Description
Specification
Units
Min Max
Phase noise 100 Hz Offset – –75 dB
1 kHz Offset – –104 dB
10 kHz Offset. – -120 dB
100 kHz Offset – -128 dB
1 MHz Offset – -130 dB
Maximum
frequency
deviation
– 150 ppm
Duty cycle 30 70 %
Overshoot – 3 %
Undershoot – -3 %
Rise time/fall
time
– 3 ns
Based on the clocking option that is used, the frequency
select, FSLC[2:0], lines can be tied to power, through a
weak pull-up resistor, or to ground. Table 6 shows the
values of FSLC[2:0] for the different clocking options.
Table 6. Frequency Select Configuration
FSLC[2] FSLC[1] FSLC[0]
Crystal/Clock
Frequency
0 0 0 19.2 MHz crystal
1 0 0 19.2 MHz input clock
1 0 1 26 MHz input clock
1 1 0 38.4 MHz input clock
1 1 1 52 MHz input clock
CVDDQ supply is the supply associated with the clock
input. It should be set to the same voltage level as the
external clock input (if any).
If only external clock input is used, the XTALIN and
XTALOUT pins can be left unconnected. If only crystal
clocking is used, the CLKIN pin can be left unconnected.
Watchdog Timer
A 32.768 kHz clock input can be used for watchdog timer
operation during Standby mode. This may be optionally
supplied by an external source.
Table 7. Wachdog Timer Requirements
Parameter Min Max Unit
Duty Cycle 40 60 %
Frequency Deviation - ±200 ppm
GPIF II Interface
EZ-USB FX3 offers a high-performance general
programmable interface, GPIF II. This interface enables
functionality similar to but more advanced than FX2LP‟s
GPIF and Slave FIFO interfaces. AN65974 “Designing
with the EZ-USB FX3 Slave FIFO Interface” and AN75779
“Interfacing the EZ-USB FX3 to an Image Sensor in UVC
Framework” are two popular application notes regarding
the GPIF interface.
Following are some general design guidelines for the
EZ-USB FX3‟s GPIF II interface.
The maximum frequency of the GPIF II interface is
100 MHz. It is recommended that all lines on the GPIF
II bus should be length matched within 500 mils. We
also recommend using 22-Ohm series termination
resistors
If the GPIF lines are to be routed for more than
5 inches or routed through a medium, which can
cause impedance mismatch, we recommend doing
signal integrity simulation using the EZ-USB FX3 IBIS
model, available at CYUSB3KIT-001 EZ-USB
®
FX3™
and come up with a termination.
GPIO[16] (PCLK) should be used as the GPIF II clock
signal in all synchronous interfaces.
GPIO[32:30] (PMODE[2:0]) signals should be
configured appropriately at FX3 boot-up. After boot-
up, these signals can be used as GPIOs.
INT# signal cannot be used as a GPIO.
I2C Interface
EZ-USB FX3 has an I
2
C interface compatible with the I
2
C
Bus Specification Revision 3. EZ-USB FX3‟s I
2
C interface
is capable of operating as I
2
C Master only. For example,
EZ-USB FX3 may boot from an EEPROM connected to
the I
2
C interface, as a selectable boot option. EZ-USB
FX3‟s I
2
C Master Controller also supports Multi-master
mode functionality.
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 7
The power supply for the I
2
C interface is VIO5, which is a
separate power domain from the other serial peripherals.
This is to allow the I
2
C interface the flexibility to operate at
a different voltage than the other serial interfaces.
The bus frequencies supported by the I
2
C controller are
100 kHz, 400 kHz, and 1 MHz. When VIO5 is 1.2 V, the
maximum operating frequency supported is 100 kHz.
When VIO5 is 1.8 V, 2.5 V, or 3.3 V, the operating
frequencies supported are 400 kHz and 1 MHz.
If an external EEPROM is used on the I
2
C bus for firmware
image booting, 2 kΩ pull-up resistors should be placed on
the SCL and SDA lines for proper operation as shown in
Figure 10.
Figure 10. I
2
C Configuration
Low Performance Peripherals (LPP)
JTAG
EZ-USB FX3 has a JTAG interface to provide a standard
five-pin interface for connecting to a JTAG debugger. This
feature enables the debugging of the firmware through the
CPU core's on-chip debug circuitry. There is no need for
external pull up/down on the JTAG signals as the JTAG
signals TDI, TMC, TRST# signals have fixed 50 kΩ
internal pull-ups and the TCK signal has a fixed 10 kΩ
pull-down resistor.
I2S
EZ-USB FX3 has an I
2
S port to support external audio
codec devices. EZ-USB FX3 functions as an I
2
S master
(transmitter only). EZ-USB FX3 can generate the system
clock as an output on the I2S_MCLK line or accept an
external system clock input on the same line.
SPI and UART
EZ-USB FX3 supports an SPI master interface on the
serial peripherals port. The SPI GPIOs are shared with the
UART GPIOs. There should be no pull up/down on MOSI
and MISO signals. Figure 11 shows the correct SPI signal
connection using the M25P40-VMN6TPB SPI device.
Figure 11. SPI Configuration
Booting
EZ-USB FX3 can be either the main processor in a system
or a co-processor to another main processor. The booting
option you use depends on the specific system
implementation. PMODE[2:0] configures the boot option
and can be connected directly to the main processor or
hardwired on the board depending on the booting option
that will be used. The following table shows the levels of
the PMODE[2:0] signals required for the different booting
options.
Table 8. PMODE Signals Setting
PMODE[2:0] Boot from
Z00 Sync ADMUX (16-bit)
Z01 Async ADMUX (16-bit)
Z11 USB boot
Z0Z Async SRAM (16-bit)
Z1Z I
2
C, on failure, USB boot is enabled
1ZZ I
2
C only
0Z1 SPI, on failure, USB boot is enabled
Note Z = High-Z, Open drain, No connect
We recommend adding pull-up and pull-down options on
the PMODE[2:0] signals and load the combination needed
for preferred booting option. This will give the flexibility to
debug the system during early development.
EMI and ESD Considerations
You must consider EMI and ESD on a case-by-case basis
relative to the product enclosure, deployment
environment, and regulatory statutes. This application note
does not give specific recommendations regarding EMI,
EZ-USB FX3 meets EMI requirements outlined by FCC
15B (USA) and EN55022 (Europe) for consumer
electronics. EZ-USB FX3 can tolerate reasonable EMI,
EZ-USB
®
FX3™ Hardware Design Guidelines and Schematic Checklist
www.cypress.com Document No. 001-70707 Rev. *D 8
which is conducted by the aggressor, outlined by these
specifications and continue to function as expected.
However this application note gives general EMI and ESD
considerations. Refer to Appendix A – PCB Layout Tips
for general information on PCB layout techniques. You
can also refer „Appendix A: PCB Layout Tips of AN61290 -
PSoC
®
3 and PSoC 5 Hardware Design Considerations‟,
which has a list of layout tips to improve EMI/EMC and
also have reference books on this topic.
EZ-USB FX3 has built-in ESD protection on the D+, D-
and GND pins on the USB interface. The ESD protection
levels provided on these ports are:
±2.2 kV human body model (HBM) based on ±6 kV
Contact Discharge and ±8 kV Air Gap Discharge
based on IEC61000-4-2 level 3A
±8 kV Contact Discharge and ±15 kV Air Gap
Discharge based on IEC61000-4-2 level 4C.
This protection ensures the device will continue to function
after ESD events up to the levels stated.
The SSRX+, SSRX-, SSTX+, SSTX- pins have only up to
±2.2 kV human body model (HBM) internal ESD
protection.
You can include additional protection to these pins by
using high performance, low capacitance external ESD
devices (SP3010-04UTG), as shown in Figure 12. To
prevent an effect on the performance of this bus, the
added capacitance should not exceed 0.5 pF.
Figure 12. Low Capacitance External USB SuperSpeed
ESD Protection
In terms of EMI, all signal and clock traces emit
electromagnetic (EM) radiation when they switch from one
level to another. To meet the various standards in different
countries, these emissions must be minimized. You can
use several techniques to lower EM emissions:
Consider putting the power and ground planes as t