万年历quartus仿真
2019-01-20 35页 doc 96KB 48阅读
is_496339
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万年历quartus仿真秒模块（60进制计数器）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY miao IS
PORT(chu,CLK:IN STD_LOGIC;
CQ1,CQ2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END miao;
ARCHITECTURE behav OF miao IS
signal Q1,Q2: STD_LOGIC_VECTOR...
秒模块（60进制计数器）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY miao IS
PORT(chu,CLK:IN STD_LOGIC;
CQ1,CQ2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END miao;
ARCHITECTURE behav OF miao IS
signal Q1,Q2: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS(chu,CLK)
BEGIN
if chu='1' then
Q1<="0000";Q2<="0000";
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
END IF;
IF Q2=5 AND Q1=9 THEN
Q1<="0000";Q2<="0000";COUT<='1';
ELSE COUT<='0';
END IF;
END IF;
CQ1<=Q1;CQ2<=Q2;
END PROCESS;
END;
分模块（60进制计数器）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY fen IS
PORT(chu,CLK:IN STD_LOGIC;
S1,S2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CQ1,CQ2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END fen;
ARCHITECTURE behav OF fen IS
signal Q1,Q2: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS(chu,CLK)
BEGIN
if chu='1' then
Q1<=S1;Q2<=S2;
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
END IF;
IF Q2=5 AND Q1=9 THEN
Q1<="0000";Q2<="0000";COUT<='1';
ELSE COUT<='0';
END IF;
END IF;
CQ1<=Q1;CQ2<=Q2;
END PROCESS;
END;
时模块（24进制计数器）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shi IS
PORT(chu,CLK:IN STD_LOGIC;
S1,S2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CQ1,CQ2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT:OUT STD_LOGIC);
END shi;
ARCHITECTURE behav OF shi IS
signal Q1,Q2: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS(chu,CLK)
BEGIN
if chu='1' then
Q1<=S1;Q2<=S2;
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
END IF;
IF Q2=2 AND Q1=3 THEN
Q1<="0000";Q2<="0000";COUT<='1';
ELSE COUT<='0';
END IF;
END IF;
CQ1<=Q1;CQ2<=Q2;
END PROCESS;
END;
日模块（31进制计数器）
Entity ri is
Port( chu,clk : in std_logic;
a,b : in std_logic;
S1,S2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
T1,T2 : out std_logic_vector(3 downto 0);
cout : out std_logic);
end ri;
Architecture one of ri is
signal Q1,Q2: STD_LOGIC_VECTOR(3 DOWNTO 0);
signal ab: STD_LOGIC_VECTOR(1 DOWNTO 0);
Begin
PROCESS(chu,clk,a,b)
begin
if chu='1' then Q1<=S1;Q2<=S2;
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
end if;
ab<=a&b;
case ab is
when"00"=> if Q2=3 AND Q1=1 THEN Q2<="0000"; Q1<="0001"; cout<='1';else cout<='0';
end if;
when"01"=>
if Q2=3 and Q1=0 THEN
Q2<="0000" ;Q1<="0001";cout<='1';
else cout<='0';
end if;
when"10"=>
if Q2=2 AND Q1=8 then
Q2<="0000" ;Q1<="0001";cout<='1';
else cout<='0';
end if;
when"11"=>
if Q2=2 AND Q1=9 then
Q2<="0000" ;Q1<="0001";cout<='1';
else cout<='0';
end if;
when others =>NULL;
end case;
END IF;
T1<=Q1;
T2<=Q2;
END PROCESS;
END ARCHITECTURE one;
月模块(12进制计数器)
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY yue IS
PORT(chu,CLK,run:IN STD_LOGIC;
S1,S2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Y1,Y2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
a,b:OUT STD_LOGIC;
COUT:OUT STD_LOGIC);
END yue;
ARCHITECTURE ONE OF yue IS
signal Q2,Q1:STD_LOGIC_VECTOR (3 DOWNTO 0);
signal Q2Q1:STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
PROCESS(chu,CLK,run)
BEGIN
IF chu='1' then
Q1<=S1;Q2<=S2;
elsIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
END IF;
IF Q2=1 AND Q1=2 THEN Q1<="0001";Q2<="0000";COUT<='1';
ELSE COUT<='0';
END IF;
end if;
end PROCESS;
PROCESS(q2,q1)
begin
Q2Q1<=Q2&Q1;
case Q2Q1 is
when"00000001"=> a<='0';b<='0';
when"00000010"=>if run='1'then a<='1';b<='1'; else a<='1';b<='0'; end if;
when"00000011"=>a<='0';b<='0';
when"00000100"=>a<='0';b<='1';
when"00000101"=>a<='0';b<='0';
when"00000110"=>a<='0';b<='1';
when"00000111"=>a<='0';b<='0';
when"00001000"=>a<='0';b<='0';
when"00001001"=>a<='0';b<='1';
when"00010000"=>a<='0';b<='0';
when"00010001"=>a<='0';b<='1';
when"00010010"=>a<='0';b<='0';
when others=>null;
end case;
END PROCESS;
Y1<=Q1;Y2<=Q2;
END ARCHITECTURE ONE;
年模块（一万进制计数器）
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY nian IS
PORT(chu,A,B,CLK:IN STD_LOGIC;
S1,S2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
N1,N2,N3,N4:OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END nian;
ARCHITECTURE ABC OF nian IS
signal Q1,Q2,Q3,Q4:STD_LOGIC_VECTOR (3 DOWNTO 0);
signal Z:STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS(chu,A)
BEGIN
IF chu='1' then
CASE A IS
WHEN'1'=>
Q4<=S2;Q3<=S1;
when'0'=>
Q2<=S2;Q1<=S1;
WHEN OTHERS=>NULL;
END CASE;
--IF A='0'THEN Q4<="0010";Q3<="0000";Q2<="0001";Q1<="0001";
--ELSIF B='1' THEN Q4<=S2;Q3<=S1;
--ELSE Q2<=S2;Q1<=S1;
--END IF;
--END IF;
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=9 THEN Q1<="0000";Q2<=Q2+1;
END IF;
IF Q2=9 aAND Q1=9 THEN Q2<="0000";Q3<=Q3+1;
END IF;
IF Q3=9 AND Q2=9 and Q1=9 THEN Q3<="0000";Q4<=Q4+1;
END IF;
IF Q4=9 AND Q3=9 AND Q2=9 AND Q1=9 THEN
Q1<="0000";Q2<="0000";Q3<="0000";Q4<="0000";
END IF;
end if;
end PROCESS;
N1<=Q1;N2<=Q2;N3<=Q3;N4<=Q4;
end ABC;
闰年模块
ENTITY runnian is
PORT( n1,n2,n3,n0 :in std_logic_vector( 3 downto 0);
ru1 :OUT std_logic);
END runnian ;
--*********************************************
ARCHITECTURE abc OF runnian IS
signal ru :std_logic;
BEGIN
process(n1,n2,n3,n0)
BEGIN
if n0=0 and n1=0 then
if n3(0)='0'then
if N2=0 OR N2=4 OR N2=8 then ru<='1';
else ru<='0';
end if;
else
if n2=2 or n2=6 then ru<='1';
else ru<='0';
end if ;
end if;
else
if n1(0)='0'then
if N0=0 OR N0=4 OR N0=8 then ru<='1';
else ru<='0';
end if;
else
if n0=2 or n0=6 then ru<='1';
else ru<='0';
end if ;
end if;
end if;
ru1<=ru;
end process;
end abc;
星期模块（8进制计数器）
ENTITY xingqi IS
PORT(chu,CLK:IN STD_LOGIC;
s1:in STD_LOGIC_VECTOR (3 DOWNTO 0);
C1:OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END xingqi;
ARCHITECTURE abc OF xingqi IS
signal Q1: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
PROCESS(chu,CLK)
BEGIN
if chu='1' then
Q1<=s1;
ELSIF CLK'EVENT AND CLK='1' THEN
Q1<=Q1+1;
IF Q1=7 THEN Q1<="0001";
END IF;
END IF;
C1<=Q1;
END PROCESS;
END abc;
生日模块
ENTITY shengri IS
Port( chu : in std_logic;
a,b,c :IN STD_LOGIC;
y2,y1,r2,r1:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
q2,q1:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
nao:OUT STD_LOGIC);
END shengri;
ARCHITECTURE abc OF shengri IS
signal y2y1,r2r1,q2q1,sy1,sy2,sy3,sr1,sr2,sr3:STD_LOGIC_VECTOR (7 DOWNTO 0);
signal sr,s1,s2,s3:STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ab:STD_LOGIC_VECTOR (1 DOWNTO 0);
--signal Q2Q1:STD_LOGIC;
BEGIN
PRocESS(a,b,c,chu)
begin
ab<=a&b;y2y1<=y2&y1;
r2r1<=r2&r1;q2q1<=q2&q1;
s1<=sy1&sr1;s2<=sy2&sr2;s3<=sy3&sr3;
sr<=y2y1&r2r1;
IF chu='1' THEN if c='1' then
case ab is when"00"=> s1<=s1;s2<=s2;s3<=s3;
when"01"=> sy1<=q2q1;
when"10"=> sy2<=q2q1;
when"11"=>sy3<=q2q1;
when others =>null;
end case;
else
case ab is
when"00"=>s1<=s1;s2<=s2;s3<=s3;
when"01"=>sr1<=q2q1;
when"10"=>sr2<=q2q1;
when"11"=> sr3<=q2q1;
when others =>null;
end case;end if;end if;
if sr=s1 or sr=s2 or sr=s3 then nao<='1';
ELSE nao<='0';
end if;
end process;
end abc;
控制模块
library ieee;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY kong IS
PORT(a,b,c,d,e,CHU,G,F:IN STD_LOGIC;
Q1,Q2:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
N1,N2,Y1,Y2,R1,R2,S1,S2,F1,F2,X1,SR1,SR2:OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
NC,NA,NB,SRC,SA,SRB,YC,RC,SC,FC,MC,XC:OUT STD_LOGIC);
END kong;
ARCHITECTURE ONE OF kong IS
signal abcde:STD_LOGIC_VECTOR(4 DOWNTO 0);
BEGIN
PROCESS(a,b,c,d,e)
BEGIN
abcde<=a&b&c&d&e;
case abcde is
WHEN"10000"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10001"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10010"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10011"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10100"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10101"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10110"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"10111"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11000"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11001"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11010"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11011"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11100"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11101"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11110"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"11111"=>N1<="0000";N2<="0010";Y1<="0001";Y2<="0000";R1<="0001";R2<="0000";S1<="1001";S2<="0000";F1<="0000";F2<="0000";X1<="0001";
NC<='1';YC<='1';RC<='1';SC<='1';FC<='1';MC<='1';XC<='1';SRC<='0';
WHEN"01000"=>MC<=CHU;NC<='0';YC<='0';RC<='0';SC<='0';FC<='0';XC<='0';SRC<='0';
WHEN"01001"=>X1<=Q1;XC<=CHU;NC<='0';YC<='0';RC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"01010"=>R1<=Q1;R2<=Q2;RC<=CHU;NC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"01011"=>Y1<=Q1;Y2<=Q2;YC<=CHU;NC<='0';RC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"01100"=>N1<=Q1;N2<=Q2;NC<=CHU;NB<=G;NA<=F;RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"01101"=>S1<=Q1;S2<=Q2;SC<=CHU;NC<='0';YC<='0';XC<='0';RC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"01110"=>F1<=Q1;F2<=Q2;FC<=CHU;NC<='0';YC<='0';XC<='0';RC<='0';SC<='0';MC<='0';SRC<='0';
WHEN"01111"=>SR1<=Q1;SR2<=Q2;SRC<=CHU;SA<=F;SRB<=G;NC<='0';YC<='0';XC<='0';RC<='0';FC<='0';MC<='0';SC<='0';
WHEN"00000"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00001"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00010"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00011"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00100"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00101"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00110"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN"00111"=>NC<='0';RC<='0';YC<='0';XC<='0';SC<='0';FC<='0';MC<='0';SRC<='0';
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END ONE;
切换模块
ENTITY qie IS
PORT(qie:IN STD_LOGIC;
N1,N2,N3,N4,Y1,Y2,R1,R2,S1,S2,F1,F2,M2,M1,X1:in STD_LOGIC_VECTOR(3 DOWNTO 0);
L1,L2,L3,L4,L5,L6,L7,L8:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END qie;
ARCHITECTURE ONE OF qie IS
signal C1,C2,C3,C4,C5,C6,C7,C8:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(qie)
BEGIN
if qie='1' then C8<=N4;C7<=N3;C6<=N2;C5<=N1;C4<=Y2;C3<=Y1;C2<=R2;C1<=R1;
ELSE C8<=S2;C7<=S1;C6<=F2;C5<=F1;C4<=M1;C3<=M2;C2<="0000";C1<=X1;
end if;
end process;
L1<=C1;L2<=C2;L3<=C3;L4<=C4;L5<=C5;L6<=C6;L7<=C7;L8<=C8;
END ONE;
译码器模块（由7448和7404构成）
1hz模块
entity fenpin12 is
port(clk:in std_logic;
clk_out:out std_logic);
end;
architecture art of fenpin12 is
signal count:integer range 0 to 6;
signal clk_data:std_logic;
begin
process(clk,count)
begin
if clk'event and clk='1' then
if count=6 then
Count<=0;
clk_data<=not clk_data;
else count<=count+1;
end if;
end if;
clk_out<=clk_data;
end process;
end art;
1000分频
entity fenpin1000 is
port(clk:in std_logic;
clk_out:out std_logic);
end;
architecture art of fenpin1000 is
signal count:integer range 0 to 1000;
signal clk_data:std_logic;
begin
process(clk,count)
begin
if clk'event and clk='1' then
if count=1000 then
Count<=0;
clk_data<=not clk_data;
else count<=count+1;
end if;
end if;
clk_out<=clk_data;
end process;
end art;
分频调控模块
entity fenpintiao is
port(clk:in std_logic;
clk_out:out std_logic);
end;
architecture art of fenpintiao is
signal count:integer range 0 to 1000;
signal clk_data:std_logic;
begin
process(clk,count)
begin
if clk'event and clk='1' then
if count=1000 then
Count<=0;
clk_data<=not clk_data;
else count<=count+1;
end if;
end if;
clk_out<=clk_data;
end process;
end art;
总电路图
引脚分配
/
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