FPGA可编程逻辑器件芯片10AX027H4F34I3SG中文规格书

PeripheryPerformanceSpecificationsThissectiondescribestheperipheryperformance,high-speedI/O,andexternalmemoryinterface.Actualachievablefrequencydependsondesignandsystemspecificfactors.EnsurepropertimingclosureinyourdesignandperformHSPICE/IBISsimulationsbasedonyourspecificdesignandsystemsetuptodeterminethemaximumachievablefrequencyinyoursystem.High-SpeedI/OSpecificationsTable47.High-SpeedI/OSpecificationsforIntelArria10DevicesWhenserializer/deserializer(SERDES)factorJ=3to10,usetheSERDESblock.ForLVDSapplications,youmustusethePLLsinintegerPLLmode.Youmustcalculatetheleftovertimingmargininthereceiverbyperforminglinktimingclosureanalysis.Youmustconsidertheboardskewmargin,transmitterchannel-to-channelskew,andreceiversamplingmargintodeterminetheleftovertimingmargin.TheIntelArria10devicessupportthefollowingoutputstandardsusingtrueLVDSoutputbuffertypesonallI/Obanks:•TrueRSDSoutputstandardwithdataratesofupto360Mbps•Truemini-LVDSoutputstandardwithdataratesofupto400MbpsSymbolCondition–E1S(71),–E1H,–I1S(71),–I1H–E2L,–E2S(71),–I2L,–I2S(71)–E3L,–E3S(71),–E3V,–I3L,–I3S(71),–I3VUnitMinTypMaxMinTypMaxMinTypMaxfHSCLK_in(inputclockfrequency)TrueDifferentialI/OStandardsClockboostfactorW=1to40(72)10—80010—70010—625MHzfHSCLK_in(inputclockfrequency)SingleEndedI/OStandardsClockboostfactorW=1to40(72)10—62510—62510—525MHzfHSCLK_OUT(outputclockfrequency)———800(73)——700(73)——625(73)MHzcontinued...(71)–E1Sand–E2SspeedgradesareapplicabletobothVCC=0.9Vand0.95V.–E3SspeedgradeisonlyapplicabletoVCC=0.9V.(72)ClockBoostFactor(W)istheratiobetweentheinputdatarateandtheinputclockrate.(73)ThisisachievedbyusingthePHYclocknetwork.Intel®Arria®10DeviceDatasheetA10-DATASHEET|2020.06.26SendFeedbackIntel®Arria®10DeviceDatasheetA10-DATASHEET|2020.06.26SendFeedbackTransceiverPerformanceforIntelArria10GTDevicesTable25.TransmitterandReceiverDataRatePerformanceSymbol/DescriptionConditionTransceiverSpeedGrade1TransceiverSpeedGrade2UnitChip-to-chip(40)MaximumdatarateVCCR_GXB=VCCT_GXB=1.12VGTChannel(41)25.825.8GbpsGXChannel17.415GbpsMaximumdatarateVCCR_GXB=VCCT_GXB=1.03VGXChannel1614.2GbpsMaximumdatarateVCCR_GXB=VCCT_GXB=0.95VGXChannel11.311.3GbpsMinimumdatarateGTChannel1.0(42)GbpsGXChannelBackplane(40)MaximumdatarateVCCR_GXB=VCCT_GXB=1.12VGXChannel12.512.5GbpsMaximumdatarateVCCR_GXB=VCCT_GXB=1.03VGXChannel12.512.5GbpsMinimumdatarateGXChannel1.0(42)GbpsIntel®Arria®10DeviceDatasheetA10-DATASHEET|2020.06.26SendFeedbackIntel®Arria®10DeviceDatasheetA10-DATASHEET|2020.06.26SendFeedbackExternalTemperatureSensingDiodeSpecificationsTable45.ExternalTemperatureSensingDiodeSpecificationsforIntelArria10Devices•Thetypicalvalueisat25°C.•Diodeaccuracyimproveswithlowerinjectioncurrent.•AbsoluteaccuracyisdependentonthirdpartyexternaldiodeADCandintegrationspecifics.DescriptionMinTypMaxUnitIbias,diodesourcecurrent10—100μAVbias,voltageacrossdiode0.3—0.9VSeriesresistance——<1ΩDiodeidealityfactor—1.03——InternalVoltageSensorSpecificationsTable46.InternalVoltageSensorSpecificationsforIntelArria10DevicesParameterMinimumTypicalMaximumUnitResolution——6BitSamplingrate——500KspsDifferentialnon-linearity(DNL)——±1LSBIntegralnon-linearity(INL)——±1LSBGainerror——±1%Offseterror——±1LSBInputcapacitance—20—pFClockfrequency0.1—11MHzUnipolarInputModeInputsignalrangeforVsigp0—1.5VCommonmodevoltageonVsign0—0.25VInputsignalrangeforVsigp–Vsign0—1.25VIntel®Arria®10DeviceDatasheetA10-DATASHEET|2020.06.26SendFeedback