ADC0809-VHDL程序并显示

ADC0809-VHDL程序并显示 --编程软件:ISE 10.1 --10年北京市电设比赛准备程序，调了半天的程序，绝对能用，但是说不考了 --后面有引脚配置代码 --程序 library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity adcok is PORT( D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK,EOC:IN STD_LOGIC; ALE,START,OE:OUT STD_LOGIC; ADDA:OUT STD_LOGIC_VECTOR(2 DOWNTO 0); Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); clockout:out std_logic; seg7 : out STD_LOGIC_VECTOR (6 downto 0); an : out STD_LOGIC_VECTOR (3 downto 0); dp : out STD_LOGIC); end adcok; architecture Behavioral of adcok is TYPE STATES IS(ST0,ST1,ST2,ST3,ST4,ST5,ST6,ST7); SIGNAL CURRENT_STATE,NEXT_STATE:STATES:=ST0; SIGNAL REGL : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL REG : STD_LOGIC_VECTOR(15 DOWNTO 0):="0000000000000000"; SIGNAL LOCK : STD_LOGIC; signal cclk,clkseg:std_logic; signal s : std_logic_vector(1 downto 0):="00"; signal digit : std_logic_vector(3 downto 0); signal aen : std_logic_vector(3 downto 0); signal qat,qbt,qct,qdt: STD_LOGIC_VECTOR (3 downto 0); signal b : STD_LOGIC_VECTOR (13 downto 0):="00000000000000"; signal p : STD_LOGIC_VECTOR (16 downto 0):="00000000000000000"; begin ADDA<="000";--LOCK1<=LOCK; clockout <=cclk; REG(7 DOWNTO 0) <= REGL; Q<=REGL; dp<='0'; aen(0)<=qdt(3) or qdt(2) or qdt(1) or qdt(0); aen(1)<=qdt(3) or qdt(2) or qdt(1) or qdt(0) or qct(3) or qct(2) or qct(1) or qct(0); aen(2)<=qdt(3) or qdt(2) or qdt(1) or qdt(0) or qct(3) or qct(2) or qct(1) or qct(0) or qbt(3) or qbt(2) or qbt(1) or qbt(0); aen(3)<='1'; b(7 downto 0)<=REGL(7 DOWNTO 0); ------------------------------------------ qat <= P(3 downto 0); qbt <= P(7 downto 4); qct <= P(11 downto 8); qdt <= "0000"; ------------------------------------------ process(b) variable z : std_logic_vector(32 downto 0); begin for i in 0 to 32 loop z(i):='0'; end loop; z(16 downto 3) := b; for j in 0 to 10 loop if(z(17 downto 14)>"0100") then z(17 downto 14):= z(17 downto 14) + "0011"; end if; if(z(21 downto 18)>"0100") then z(21 downto 18):= z(21 downto 18) + "0011"; end if; if(z(25 downto 22)>"0100") then z(25 downto 22):= z(25 downto 22) + "0011"; end if; if(z(29 downto 26)>"0100") then z(29 downto 26):= z(29 downto 26) + "0011"; end if; z(32 downto 1):=z(31 downto 0); end loop; p<=z(30 downto 14); end process; PROCESS(CLK) VARIABLE q:INTEGER:=0; BEGIN IF CLK'EVENT AND CLK='1' THEN q:=q+1; IF q<=199 THEN clkseg<='0'; ELSIF q<399 THEN clkseg<='1'; ELSE q:=0; END IF; END IF; END PROCESS; -------------------------------------------- PROCESS(CLK) VARIABLE q4:INTEGER:=0; BEGIN IF CLK'EVENT AND CLK='1' THEN q4:=q4+1; IF q4<=49 THEN cclk<='0'; ELSIF q4<99 THEN cclk<='1'; ELSE q4:=0; END IF; END IF; END PROCESS; ------------------------------------------------- PROCESS(cclk) BEGIN IF(cclk'EVENT AND cclk='1') THEN CURRENT_STATE<=NEXT_STATE; END IF; END PROCESS; --------------------------------------------- PROCESS(LOCK) BEGIN IF LOCK='1' AND LOCK' EVENT THEN REGL<=D; END IF; END PROCESS; ------------------------------ process(CURRENT_STATE,EOC) BEGIN CASE CURRENT_STATE IS WHEN ST0=>ALE<='0';START<='0';OE<='0';LOCK<='0'; NEXT_STATE<=ST1; WHEN ST1=>ALE<='1';START<='0';OE<='0';LOCK<='0'; NEXT_STATE<=ST2; WHEN ST2=>ALE<='1';START<='1';OE<='0';LOCK<='0'; NEXT_STATE<=ST3; WHEN ST3=>ALE<='0';START<='1';OE<='0';LOCK<='0'; NEXT_STATE<=ST4; WHEN ST4=>ALE<='0';START<='0';OE<='0';LOCK<='0'; IF(EOC='1')THEN NEXT_STATE<=ST4; ELSE NEXT_STATE<=ST5; END IF; WHEN ST5=>ALE<='0';START<='0';OE<='0';LOCK<='0'; IF(EOC='0')THEN NEXT_STATE<=ST5; ELSE NEXT_STATE<=ST6; END IF; WHEN ST6=>ALE<='0';START<='0';OE<='1';LOCK<='0'; NEXT_STATE<=ST7; WHEN ST7=>ALE<='0';START<='0';OE<='1';LOCK<='1'; NEXT_STATE<=ST0; WHEN OTHERS=>ALE<='0';START<='0';OE<='0';LOCK<='0'; NEXT_STATE<=ST0; END CASE; END PROCESS ; ------------------------------------------------------------------ process(s,qat,qbt,qct,qdt) begin case s is when "00" =>digit<=qdt(3 downto 0); when "01" =>digit<=qct(3 downto 0); when "10" =>digit<=qbt(3 downto 0); when "11" =>digit<=qat(3 downto 0); when others =>null; end case; end process; -------------------------------------------------------------------------- process(digit) begin case digit is when x"0" => seg7 <= "1111110";--"0000001"; when x"1" => seg7 <= "0110000";--"1001111"; when x"2" => seg7 <= "1101101";--"0010010"; when x"3" => seg7 <= "1111001";--"0000110"; when x"4" => seg7 <= "0110011";--"1001100"; when x"5" => seg7 <= "1011011";--"0100100"; when x"6" => seg7 <= "1011111";--"0100000"; when x"7" => seg7 <= "1110000";--"0001111"; when x"8" => seg7 <= "1111111";--"0000000"; when x"9" => seg7 <= "1111011";--"0000100"; when x"A" => seg7 <= "1110111";--"0001000"; when x"B" => seg7 <= "0011111";--"1100000"; when x"C" => seg7 <= "1001110";--"0110001"; when x"D" => seg7 <= "0111101";--"1000010"; when x"E" => seg7 <= "1001111";--"0110000"; when others => seg7 <= "1000111";--"0111000"; end case; end process; -------------------------------------------------------------------------- process(aen,s) begin an<="0000"; if(aen(conv_integer(s))='1') then an(conv_integer(s))<='1'; end if; end process; -------------------------------------------------------------------------- process(clkseg) begin if(rising_edge(clkseg)) then s<=s+"01"; end if; end process; end Behavioral; --引脚配置文件 #PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "CLK" LOC = "p80" ; NET "ADDA<0>" LOC = "p147" ; NET "ADDA<1>" LOC = "p145" ; NET "ADDA<2>" LOC = "p140" ; NET "ALE" LOC = "p146" ; NET "clockout" LOC = "p119" ; NET "D<0>" LOC = "p132" ; NET "D<1>" LOC = "p128" ; NET "D<2>" LOC = "p126" ; NET "D<3>" LOC = "p122" ; NET "D<4>" LOC = "p133" ; NET "D<5>" LOC = "p129" ; NET "D<6>" LOC = "p127" ; NET "D<7>" LOC = "p123" ; NET "EOC" LOC = "p150" ; NET "OE" LOC = "p138" ; NET "Q<0>" LOC = "p33" ; NET "Q<1>" LOC = "p31" ; NET "Q<2>" LOC = "p30" ; NET "Q<3>" LOC = "p29" ; NET "Q<4>" LOC = "p28" ; NET "Q<5>" LOC = "p25" ; NET "Q<6>" LOC = "p24" ; NET "Q<7>" LOC = "p23" ; NET "START" LOC = "p139" ; NET "an<0>" LOC = "p39" ; NET "an<1>" LOC = "p36" ; NET "an<2>" LOC = "p35" ; NET "an<3>" LOC = "p34" ; NET "dp" LOC = "p40" ; NET "seg7<0>" LOC = "p49" ; NET "seg7<1>" LOC = "p42" ; NET "seg7<2>" LOC = "p45" ; NET "seg7<3>" LOC = "p41" ; NET "seg7<4>" LOC = "p48" ; NET "seg7<5>" LOC = "p50" ; NET "seg7<6>" LOC = "p47" ; #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE