五人表决器.全加器.四位全加器. 16进制数码显示.60进制计数器.

五人表决器.全加器.四位全加器. 16进制数码显示.60进制计数器. 五人表决器.全加器.四位全加器. 16进制数码显示.60进制计 数器. 实验一:五人表决器 1-编程: library ieee; use ieee.std_logic_1164.all; entity vote5 is port(a,b,c,d,e:in std_logic; f:out std_logic); end; architecture vo of vote5 is begin f<=(a and b and c) or (a and b and d) or (a and b and e) or (a and c and d) or (a and c and e) or (a and d and e) or (b and c and d) or (b and c and e) or (b and d and e) or (c and d and e); end; 方案2-作图: 实验二一位全加器 一种方法: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT (a, b, ci : IN STD_LOGIC; S, co : OUT STD_LOGIC); END fulladder; --以下是一位全加器结构体数据流描述 ARCHITECTURE Dataflow OF fulladder IS BEGIN S <= a XOR b XOR ci; co <= (a AND b) OR (b AND ci) OR (a AND ci); END Dataflow; 二种方法 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY fulladder IS PORT (a, b, ci: IN STD_LOGIC; s, co: OUT STD_LOGIC); END fulladder; ARCHITECTURE behavioral OF fulladder IS BEGIN s <= '1' WHEN (a= '0' AND b= '1' AND ci= '0') ELSE '1' WHEN (a= '1' AND b= '0' AND ci= '0') ELSE '1' WHEN (a= '0' AND b= '0' AND ci= '1') ELSE '1' WHEN (a= '1' AND b= '1' AND ci= '1') ELSE '0'; co <= '1' WHEN (a= '1' AND b= '1' AND ci= '0') ELSE '1' WHEN (a= '0' AND b= '1' AND ci= '1') ELSE '1' WHEN (a= '1' AND b= '0' AND ci= '1') ELSE '1' WHEN (a= '1' AND b= '1' AND ci= '1') ELSE '0'; END behavioral; 实验三四位全加器 第一种方法:顶层文件为原理图 第二种方法 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add4 is port(a3,a2,a1,a0,b3,b2,b1,b0:in std_logic; f:out std_logic_vector(4 downto 0)); end; architecture add of add4 is begin process(a3,a2,a1,a0,b3,b2,b1,b0) variable c,d:std_logic_vector(4 downto 0):="00000"; begin c:=('0',a3,a2,a1,a0); d:=('0',b3,b2,b1,b0); f<=c+d; end process; end; 实验四 16进制数码显示 library ieee; use ieee.std_logic_1164.all; entity tran is port(a:in std_logic_vector(3 downto 0); s:out std_logic_vector(2 downto 0); f:out std_logic_vector(6 downto 0)); end; architecture tt of tran is begin process(a) begin s<="111"; case a is when "0000" => f <= "0111111"; --0 when "0001" => f <= "0110000"; --1 when "0010" => f <= "1011011"; --2 when "0011" => f <= "1001111"; --3 when "0100" => f <= "1100110"; --4 when "0101" => f <= "1101101"; --5 when "0110" => f <= "1111101"; --6 when "0111" => f <= "0000111"; --7 when "1000" => f <= "1111111"; --8 when "1001" => f <= "1100111"; --9 when "1010" => f <= "1110111"; --a when "1011" => f <= "1111100"; --b when "1100" => f <= "0111001"; --c when "1101" => f <= "1011110"; --d when "1110" => f <= "1111001"; --e when others => f <= "1110001"; --f end case; end process; end; 实验六 60进制计数器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; entity con60 is port(clk3,clk5,rst,en:in std_logic; seg_sel:out std_logic_vector(2 downto 0); seg_da:out std_logic_vector(7 downto 0); co:out std_logic); end; architecture cc of con60 is COMPONENT CNT10 PORT(CLK,rst,cin:IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT :OUT STD_LOGIC); END COMPONENT; COMPONENT CNT6 PORT(CLK,rst,cin :IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC); END COMPONENT; SIGNAL SEG_BUF1,SEG_BUF2:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL SEG_CNT :STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL SEG_TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL COUT:STD_LOGIC_VECTOR(5 DOWNTO 0); SIGNAL CLK:STD_LOGIC; BEGIN PROCESS (CLK3) BEGIN IF CLK3'EVENT AND CLK3='1' THEN CLK<=NOT CLK ; END IF; END PROCESS; PROCESS (CLK) BEGIN IF CLK'EVENT AND CLK='1' THEN IF seg_cnt="001" THEN SEG_CNT<="000"; ELSE SEG_CNT<=SEG_CNT+1; END IF; END IF; END PROCESS; SEG_SEL<=SEG_CNT; PROCESS(SEG_CNT,SEG_BUF1,SEG_BUF2) BEGIN CASE SEG_CNT IS WHEN "000" => SEG_TEMP<=SEG_BUF1; WHEN "001" => SEG_TEMP<=SEG_BUF2; WHEN OTHERS => NULL; END CASE; END PROCESS; PROCESS (SEG_TEMP) BEGIN CASE SEG_TEMP IS WHEN "0000" => SEG_DA<=x"3F"; WHEN "0001" => SEG_DA<=x"06"; WHEN "0010" => SEG_DA<=x"5B"; WHEN "0011" => SEG_DA<=x"4F"; WHEN "0100" => SEG_DA<=x"66"; WHEN "0101" => SEG_DA<=x"6D"; WHEN "0110" => SEG_DA<=x"7D"; WHEN "0111" => SEG_DA<=x"07"; WHEN "1000" => SEG_DA<=x"7F"; WHEN others => SEG_DA<=x"6F"; END CASE; END PROCESS; U1 : CNT10 PORT MAP (CLK5,RST,'1',SEG_BUF1,COUT(0)); U2 : CNT6 PORT MAP (CLK5,RST,COUT(0),SEG_BUF2,co); END ; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY CNT10 IS PORT(CLK :IN STD_LOGIC; RST :IN STD_LOGIC; CIN :IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC ); END CNT10; ARCHITECTURE BEHAVE OF CNT10 IS SIGNAL CNT_T:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK) BEGIN IF RST='1' THEN CNT_T<="0000"; ELSIF CLK'EVENT AND CLK='1' THEN IF CIN='1' THEN IF CNT_T/= 9 THEN CNT_T<=CNT_T+1; ELSE CNT_T<="0000"; END IF; END IF; ELSE CNT_T<=CNT_T; END IF; END PROCESS; COUT<='1' WHEN CNT_T=9 AND CIN='1' ELSE '0' ; CNT_VAL<=CNT_T; END BEHAVE; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY cnt6 IS PORT(CLK :IN STD_LOGIC; RST :IN STD_LOGIC; CIN :IN STD_LOGIC; CNT_VAL:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT:OUT STD_LOGIC ); END CNT6; ARCHITECTURE ADO2 OF CNT6 IS SIGNAL CNT_T :STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL COUTD :STD_LOGIC; BEGIN PROCESS (CLK,RST) BEGIN IF RST='1' THEN CNT_T<="0000"; ELSIF CLK'EVENT AND CLK='1' THEN IF CIN='1' THEN IF CNT_T< 5 THEN CNT_T<=CNT_T+1; ELSE CNT_T<=x"0"; END IF; END IF; ELSE CNT_T<=CNT_T; END IF; END PROCESS; COUT<='1' WHEN CNT_T=5 AND CIN='1' ELSE '0'; CNT_VAL<=CNT_T; END ADO2;