Integrated_Circuits(集成电路)电子信息类专业英语、计算机类专业英语文章

Integrated Circuits(集成电路) Integrated Circuits(集成电路) 英文原稿: The Integrated Circuit Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.They are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differing electrical properties can be accurately controlled by mixing the semiconductor with small amounts of other elements. This mixing is called doping. A semiconductor can be doped to contain more electrons (N-type) or fewer electrons (P-type). Examples of commonly used semiconductors are silicon and germanium. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively. A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common types of transistors, the bipolar-junction transistor (BJT) and the field-effect transistor (FET) are schematically illustrated in Figure 2.1.This figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P-N doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.The FET shown is an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. When a voltage is applied to the insulated gate terminal, a current is enabled to flow from the drain to the source. It is called N-channel, because the gate voltage induces an N-channel within the substrate, enabling current to flow between the N-regions. Another basic semiconductor structure is a diode, which is formed simply by a junction of N-type and P-type silicon. Diodes act like one-way valves by conducting current only from P to N. Special diodes can be created that emit light when a voltage is applied. Appropriately enough, these components are called light emitting diodes, or LEDs. These small lights are manufactured by the millions and are found in diverse applications from telephones to traffic lights. The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the out­side world.Small wires are connected within this package between the semiconductor sandwich and pins that protrude from the package to make electrical contact with other parts of the intended circuit. Once you have several discrete transistors, digital logic can be built by directly wiring these components together. The circuit will function, but any substantial amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates. At the time of the invention of the transistor in 1947 by John Bardeen, Walter Brattain, and William Shockley, the only way to assemble multiple transistors into a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a means of fabricating multiple transistors on a single slab of semiconductor material. Their invention would come to be known as the integrated circuit, or IC, which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors and diodes onto the same small semiconductor chip. Instead of having to solder individual wires between discrete components, an IC contains many small components that are already wired together in the desired topology to form a circuit. A typical IC, without its plastic or ceramic package, is a square or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used to manufacture the IC, there may be anywhere from a dozen to tens of millions of individual transistors on this small chip. This amazing density of electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in units of micrometers, with one micrometer (1mm) being one millionth of a meter. To serve as a reference point, a human hair is roughly 100mm in diameter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm! Each year, researchers and engineers have been finding new ways to steadily reduce these feature sizes to pack more transistors into the same silicon area, as indicated in Figure 2.2. When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes create BJTs, whereas MOS processes create FETs. Bipolar logic was more common before the 1980s, but MOS technologies have since accounted the great majority of digital logic ICs. N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, complementary-MOS, or CMOS, became the dominant process technology and remains so to this day. CMOS ICs incorporate both NMOS and PMOS transistors. Application Specific Integrated Circuit An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications. As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs. History The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies include RAM elements. Standard cell design In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost. By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice. These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process. A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis. *The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register transfer level) design. *Suitability for purpose is verified by simulation. A virtual system created in software, using a tool such as Virtutech’s Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second. *A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist. *The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement. *The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling semiconductor fabrication to produce physical ICs. *Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication. These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturer’s cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design. Gate array design Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.The physical design process then defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic blocks. Full-custom design The benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip. The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any performance limiting aspect of the design. Structured design Structured ASIC design is an ambiguous expression, with different meanings in different contexts. This is a relatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a structured ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers and pre-characterization of what is on the silicon.One definition states that, in a structured ASIC design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Structured ASIC technology is seen as bridging the gap between field-programmable gate arrays and “standard-cell” ASIC designs. What makes a structured ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a structured ASIC the predefined metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well.Likewise, the design tools used for structured ASIC can substantially lower cost, and are easier to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. One other important aspect about structured ASIC is that it allows IP that is common to certain applications to be “built in”, rather than “designed in”. By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC. 中文翻译： 集成电路 集成电路 数字逻辑和电子电路由称为晶体管的电子开关得到它们的（各种）功能。粗略地说，晶体管好似一种电子控制阀，由此加在阀一端的能量可以使能量在另外两个连接端之间流动。通过多个晶体管的组合就可以构成数字逻辑模块，如与门和触发电路等。而晶体管是由半导体构成的。查阅大学化学中的元素周期表，你会查到半导体是介于金属与非金属之间的一类元素。它们之所以被叫做半导体是由于它们表现出来的性质类似于金属和非金属。可使半导体像金属那样导电，或者像非金属那样绝缘。通过半导体和少量其它元素的混合可以精确地控制这些不同的电特性，这种混合技术称之为“半导体掺杂”。半导体通过掺杂可以包含更多的电子（N型）或更少的电子（P型）。常用的半导体是硅和锗，N型硅半导体掺入磷元素，而P型硅半导体掺入硼元素。 不同掺杂的半导体层形成的三明治状夹层结构可以构成一个晶体管，最常见的两类晶体管是双极型晶体管（BJT）和场效应晶体管（FET），图2.1给出了它们的图示。图中给出了这些晶体管的硅结构，以及它们用于电路图中的符号。BJT是NPN晶体管，因为由N—P—N掺杂硅三层构成。当小电流注入基极时，可使较大的电流从集电极流向发射极。图示的FET是N沟道的场效应型晶体管，它由两块被P型基底分离的N型组成。将电压加在绝缘的栅极上时，可使电流由漏极流向源极。它被叫做N沟道是因为栅极电压诱导基底上的N通道，使电流能在两个N区域之间流动。 另一个基本的半导体结构是二极管，由N型和P型硅连接而成的结组成。二极管的作用就像一个单向阀门，由于电流只能从P流向N。可以构建一些特殊二极管，在加电压时可以发光，这些器件非常合适地被叫做发光二极管或LED。这种小灯泡数以百万计地被制造出来，有各种各样的应用，从电话机到交通灯。 半导体材料上制作晶体管或二极管所形成的小芯片用塑料封装以防损伤和被外界污染。在这封装里一些短线连接半导体夹层和从封装内伸出的插脚以便与（使用该晶体管的）电路其余部分连接。一旦你有了一些分立的晶体管，直接用电线将这些器件连线在一起就可以构建数字逻辑（电路）。电路会工作，但任何实质性的数字逻辑（电路）都将十分庞大，因为要在各种逻辑门中每实现一种都需要多个晶体管。 1947年，John Bardeen、Walter Brattain和and William Shockley发明晶体管的时候。将多个晶体管组装在一个电路上的唯一方法就是购买多个分离的晶体管，将它们连在一起。1959年，Jack Kilby 和 Robert Noyce各自独立地发明了一种将多个晶体管做在同一片半导体材料上的方法。这个发明就是集成电路，或IC，是我们现代电脑化世界的基础。集成电路之所以被这样命名，是因为它将多个晶体管和二极管集成到同一块小的半导体芯片上。IC包含按照形成电路所要求的拓扑结构连在一起的许多小元件，而无需再将分立元件的导线焊接起来。 去除了塑料或陶瓷封装后，一个典型的集成电路就是每一边2mm至15mm的方形或矩形硅片。根据制造集成电路的技术水平的不同，在这种小片上可能有几十个到几百万个晶体管，电子器件这种令人惊异的密度表明那些晶体管以及连接它们线是极其微小的。集成电路的尺寸是以微米为单位测量的，1微米是1米的百万分之一。作为参照，一根人的头发其直径大约为100微米。一些现代集成电路包含的元件和连线，是以小到0.1微米的增量来测量的。每年研究人员和工程师都在寻找新的方法来不断减小这些元件的大小，以便在同样面积的硅片上集成更多的晶体管，如图2.2所示。 在集成电路的设计和制造过程中，常用两种主要晶体管技术是：双极和金属氧化物半导体（MOS）。双极工艺生产出来的是BJT（双极型晶体管），而MOS工艺生产出来的是FET（场效应晶体管）。在20世纪80年代以前更常用的集成电路是双极逻辑，但是此后MOS技术在数字逻辑集成电路中占据了大多数。N沟道FET是采用NMOS工艺生产的，而P沟道FET是采用PMOS工艺生产的。到了20世纪80年代，互补MOS即CMOS成为占主导地位的加工技术，并且延续至今。CMOS集成电路包含了NMOS和PMOS两种晶体管。 专用集成电路（ASIC） 专用集成电路（ASIC）是为了特殊应用而定制的集成电路，而不是通用的。比如，一片仅被设计用于运行蜂窝式电话的芯片是专用集成电路（ASIC）。相比之下，7400与4000系列集成电路是可以用导线连接的逻辑构建模块，适用于各种不同的应用。 随着逐年来特征尺寸的缩小和设计工具的改进，ASIC中的最大复杂度从5000个门电路增长到了1亿个门电路，因而功能也有极大的提高。现代ASIC常包含32位处理器，包括ROM、RAM、EEPROM、Flash等存储器，以及其它大规模组件。这样的ASIC经常被称为SoC（片上系统）。数字ASIC的设计者们使用硬件描述语言（HDL），比如Verilog或VHDL语言来描述ASIC的功能。 现场可编程门阵列（FPGA）是7400系列和面包板的现代版，它包括可编程逻辑块和可编程的模块之间的相互连接，使得相同的FPGA能够用于许多不同的场合。对于较小规模的设计或（与）小批量生产，FPGA可能比ASIC设计有更高的成本效率。不能循坏的工程费用（建立工厂生产特定ASIC的成本）可能会达到数十万美元。 专用集成电路这一通用名词也包括FPGA，但是大多数设计者仅将ASIC用于非现场可编程的器件，将ASIC和FPGA两者区别开来。 历史 最初的ASIC使用门阵列技术。Ferranti在1980年左右制作了也许是第一片门阵列，ULA（自由逻辑阵列）。通过改变金属互相连接掩模产生了定制。ULA有多至几千个门电路的复杂度。之后的版本变得更通用，有适应用户的包含金属和多层硅的不同基底，有些基底包括RAM单元。 单元设计 在20世纪80年代中期，一个设计者要选择一家ASIC制造商，并用制造商提供的设计工具完成他们的设计工作。尽管有第三方设计工具，但第三方设计工具和不同的ASIC制造商的布线以及实际半导体工艺过程的性能之间却缺乏有效的联系。大多数的设计者最终使用工厂特制的工具来完成他们的设计。解决这个问题的一个方法是实现标准元件，这一问题也带来了更高密度的器件。每个ASIC制造商都可创造他们自己的具有已知电性能的功能块，如传播延迟器、电容、电感，这些都可以用第三方工具来表示（实现）。标准单元设计就是利用这些功能块来实现很高的门密度以及良好的电性能。标准单元设计使门阵列和全定制设计之间在一次性投入的工程费用和循环元件成本方面相互适应。 直到80年代后期，逻辑综合工具，比如设计编译器，开始向广大设计者提供。这些工具能够将HDL描述语言编译成门级的网表。这就使得称作标准单元设计的设计方法成为可能。标准单元集成电路的设计过程在概念上需经过以下几个过程，但事实上在实际生产中这些工序都有较大的重叠。 以工业界普通的熟练水平实现的这些步骤几乎总是产生能正确实现原设计的最终器件，除非后来在物理制造过程中引入了缺陷。 设计工程师团队开始工作于对新的ASIC所要求功能的非正式理解，这通常来自于需求分析。 *设计团队构建对ASIC芯片的描述并使用HDL语言实现这些目标。这一过程可类比于用高级语言编写计算机程序。这一过程常被称为RTL（寄存器传送级）设计。 *仿真验证目标的合适性。利用例如Virtutech’s Simics工具，用软件构建的虚拟系统能以高达每秒数十亿条模拟指令的速度来模拟ASIC的功能。 *逻辑综合工具，比如设计编译器，将RTL设计转换成称为标准单元的较低层结构的集合。这些构成的元素是从一个标准单元库中得到的，这个库由事先规定好的门电路集合构成，例如2输入或非门，2输入与非门，非门等等。有计划的ASIC制造商有其特定的标准单元。所产生的所有标准单元，加上连接他们所需要的导线称为门级网表。 *接着，门级网表由布局工具进行处理，将标准单元布局在代表最终ASIC的区域。努力寻找一种标准单元的布局服从各种规定的约束。有时，先进的技术比如模拟退火被用来优化布局。 *路由工具获取标准单元的物理布局，并利用网表来创建它们之间的电连接。由于搜索空间很大，该过程将产生满足充分条件的解，而不是全局最优解。这个过程的输出是一套光掩模使半导体制造产生实物的IC。 *接下来是对最终延时、寄生电阻和电容以及能量消耗的周全的评估。对于数字电路，这将被进一步对应为延迟信息，这些评估将用于最后一轮的测试。这一测试表明器件将在所有极端的过程、电压、温度下正常工作。当这项测试完成时，光掩模信息将被公布用于芯片制造。 这些设计步骤（或流程）对于标准产品设计同样适用。重要的差别在于标准单元设计使用制造商的单元库，这些库已用于数以百计的其它设计实现，因而比起全定制设计来风险小得多。 门阵列设计 门阵列设计是一种制造方法，事先定义好扩散层（晶体管和其它有源器件），包含这些器件的晶片在金属化之前被库存，就是说先不进行联接。然后在物理设计过程中定义最终设计的连接。对设计者来说重要的是，ASIC相比在市场上可提供的FPGA解决方案，能达到最小的传播延时。门阵列ASIC是一种折中方案，因为将某一给定的设计与制造商库存的晶片相对应总是不可能达到100%利用率的。 现在电路设计者已经很少采用纯粹的逻辑门阵列设计，而几乎都代之以FPGA之类的现场可编程器件了。这些器件可由用户编程，使工具作业费用最低，以略为提高的零件价格获得可比的性能。现在门阵列正在发展为结构化ASIC，其中包含很大的IP内核，如处理器、DSP单元、外围设备、标准接口、集成SRAM存储器、以及一组可重新设置的未确定功能的逻辑单元。这种转变很大程度上是因为ASIC器件能够集成大量的系统功能模块，以及片上系统所要求的（功能）比仅仅逻辑单元多得多。 全定制设计 全定制设计的优点通常包括减小的面积，性能的改进，以及能集成模拟元件和其它预先设计的元件比如构成片上系统的微处理器核。缺点包括增加的制造和设计时间，增加的不可循环工程成本，更复杂的CAD系统，和对设计团队熟练程度高得多的要求。但对于纯数字设计来说，“标准单元”库与现代