DELL 4010独立显卡 UM8B

1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : BLOCK DIAGRAM 1A Wednesday, February 10, 2010 UM8B DIS 1 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : BLOCK DIAGRAM 1A Wednesday, February 10, 2010 UM8B DIS 1 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : BLOCK DIAGRAM 1A Wednesday, February 10, 2010 UM8B DIS 1 46 PG.27 eSATA LANE5 SN75LVCP412 USB2.0 X1 PORT0,1,7 DB2 FAN & THERMAL GMT G990/ EMC1422-1-AIZL-TR PG.30 LANEO WWAN USB 2.0PORT5 PCI-E x 1 PG.26PG.28PG.28 PORT11 PORT4 PG.13 PG.12 PG.25 ALC269-GR PG.25 RTS5138 PG.31PG.23 PG.22 USB2.0 X1 PORT8 USB 2.0 Combo port PG.2 KBC FDI DDR3 Channel B UM8B DIS SYSTEM DIAGRAM Ibex Peak-m SODIMM1 27mm X 25mm DMI INTEL KB TP 1M ROM SODIMM2 Arrandale INTEL PCH 1071pin FCBGA TDP 35W TDP 5W Max. 4GB Max. 4GB DDR3 Channel A 37.5mm X 37.5mm LPC 989pin PGA CODEC AUDIO Webcam HP/MIC Speaker Analog MIC Card Reader BT BT365 USB 2.0 14.318MHz CLOCK GEN PORT12 PORT0,1,7 PG.34+3V/+5V PG.36 +1.05V/+1.8V PG.39CPU Core PG.38 VGA Core/+1.1V PG.35 +1.5V/+0.75V PG.37+1.05VTT PG.3~6 PG.7~11 PG.28 PG.28 SATA1 ODD HDDSATA0 LANE1LANE6 PCI-E x 1 USB 2.0LAN 10/100 WLANAtheros/AR8152 UMA VGACORE PG.33Charger Stackup TOP GND IN1 IN2 VCC BOT PORT9 Azalia ITE 8502 PG.22 PG.24 PG.19,20 PG.14~21 HDMIATI Madison 29mm X 29mm DDR3 700MHz VRAM 64Mx16x4,64bit PCI-E x16 CRT HDMI LVDS CRT LVDS DB1 PG.26 4M ROM IN3 GND 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D CLK_BUF_BCLKP_R CLK_BUF_BCLKN_R CLK_BUF_PCIE_3GPLLN_R CLK_BUF_PCIE_3GPLLP_R CLK_BUF_DREFCLKP_R CLK_BUF_DREFCLKN_R CLK_BUF_DREFSSCLKP_R CLK_BUF_DREFSSCLKN_R CLK_VGA_27M_SS XTAL_IN XTAL_OUT CPU_SELCLK_PCH_14M CK_PWRGD_R CPU_SEL XTAL_IN XTAL_OUT CK_PWRGD_R CLK_VGA_27M_NOSS +3.3V_RUN +VDDIO_CLK+1.05V_PCH +VDDIO_CLK +VDDSE_CLK +VDDSE_CLK+3.3V_RUN +3.3V_RUN +3.3V_RUN CLK_BUF_BCLKP 8 CLK_BUF_BCLKN 8 CLK_BUF_DREFCLKN 8 CLK_BUF_DREFCLKP 8 CLK_BUF_PCIE_3GPLLN 8 CLK_BUF_PCIE_3GPLLP 8 CLK_BUF_DREFSSCLKP 8 CLK_BUF_DREFSSCLKN 8 EVGA-XTALI 15 CLK_27M_SS 15 CLK_PCH_14M8 SMBCLK218,25,30 SMBDAT218,25,30 VR_PWRGD_CLKEN#39 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : Clock Gen(9LRS3197)/HOLES 1A Wednesday, February 10, 2010 UM8B DIS 2 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : Clock Gen(9LRS3197)/HOLES 1A Wednesday, February 10, 2010 UM8B DIS 2 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : Clock Gen(9LRS3197)/HOLES 1A Wednesday, February 10, 2010 UM8B DIS 2 46 02 Place each 0.1uF cap close to pin 25mA 300mA Place each 0.1uF cap close to pin Place within 0.5" of C/G Place R8044 within 0.5" of C/G Discrete only CPU_SEL 0 1 CPU0/1=133MHz (default) CPU0/1=100MHz 8/20 Wait Victor check PDC (Power Cap quantities follow UM3) BOM check Check CLK P/N and footprint SLG: SLG8SP590VTR Seligo QPN: AL8SP590000 SLG: SLG8SP585VTR Seligo QPN: AL8SP585000 RSC: RTM875N-632-VB-GRT Realtek QPN: AL000875002 58 R217 33/J_4R217 33/J_4 RP8 0X2RP8 0X22 4 1 3 RP7 0X2RP7 0X22 4 1 3 C320 0.1U/ 10V/X7RC320 0.1U/ 10V/X7R C330 33P/50V_4/NPO C330 33P/50V_4/NPO 1 2 C353 0.1U/ 10V/X7RC353 0.1U/ 10V/X7R C351 *10P/50V_4_NC/COG C351 *10P/50V_4_NC/COG R199 1K/J_4 R199 1K/J_4 C323 10U/6.3V_8/X5RC323 10U/6.3V_8/X5R Y1 14.318MHZ Y1 14.318MHZ 1 2 RP5 0X2RP5 0X2 2 4 1 3 R196 10KR196 10K R209 10K R209 10K R213 33/J_4R213 33/J_4 C328 33P/50V_4/NPO C328 33P/50V_4/NPO 1 2 C354 0.1U/ 10V/X7RC354 0.1U/ 10V/X7R 9LRS3197 QFN32 U10 9LRS3197 9LRS3197 QFN32 U10 9LRS3197 VDD_CPU_IO18 SATA 10 VDD_SRC_IO15 VSS_USB2 27MHz_SS 7 DOT96C_LPR 4 SRC-1 13 SRC-1# 14 SATA# 11 27MHz_nonSS 6 DOT96T_LPR 3 VSS_CPU 21 CPU-1 20 CPU-0# 22 CPU-0 23VDD_LCD5 VDD_SRC17 VDD_CPU24 VDD_USB1 VSS_LCD8 VSS_SRC 12 REF_0/CPU_SEL30 CPU_STOP#16 CPU-1# 19 VSS_REF 26 VDD_REF29 XOUT27 XIN28 SCLK32 SDATA31 CK_PWRGD/PD#_3.325 GND 33 VSS_SATA9 RP6 0X2RP6 0X22 4 1 3 C322 0.1U/ 10V/X7RC322 0.1U/ 10V/X7R L27 HCB1608KF-181T15_6 L27 HCB1608KF-181T15_6 1 2 L25 HCB1608KF-181T15_6 L25 HCB1608KF-181T15_6 1 2 C327 0.1U/ 10V/X7RC327 0.1U/ 10V/X7R R212 *10K_NC R212 *10K_NC R216 *33/J_4_NCR216 *33/J_4_NC C338 *10P/50V_4_NC/COGC338 *10P/50V_4_NC/COG C336 0.1U/ 10V/X7RC336 0.1U/ 10V/X7R R201 *100K/F_4_NC R201 *100K/F_4_NC Q13 FDN357N Q13 FDN357N 3 2 1 C352 10U/6.3V_8/X5RC352 10U/6.3V_8/X5R C321 0.1U/ 10V/X7RC321 0.1U/ 10V/X7R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D PEG_RBIAS PEG_COMP H_VTTPWRGD CPU_PLTRST# SM_RCOMP_2 SM_RCOMP_0 SM_RCOMP_1 FDI_INT FDI_LSYNC1 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 CLK_DREFSSCLKN_R CLK_DREFSSCLKP_R XDP_TDO_M XDP_TDI_M XDP_TRST# H_COMP1 H_COMP2 H_COMP3 H_COMP0 H_CPURST# CPU_PLTRST# H_CATERR# DDR3_DRAMRST# FDI_LSYNC1 FDI_LSYNC0 FDI_FSYNC1 FDI_FSYNC0 FDI_INT H_CPURST# H_CATERR# H_PROCHOT# PM_DRAM_PWRGD XDP_TRST# XDP_TCLK XDP_TDO XDP_TDI_M XDP_TDO_M XDP_TDI XDP_TMS PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_TXN15_C PEG_TXN15 PEG_TXN14_C PEG_TXN14 PEG_TXN13_C PEG_TXN13 PEG_TXN12PEG_TXN12_C PEG_TXN11_C PEG_TXN11 PEG_TXN10_C PEG_TXN10 PEG_TXN9_C PEG_TXN9 PEG_TXN8PEG_TXN8_C PEG_TXN7_C PEG_TXN7 PEG_TXN6PEG_TXN6_C PEG_TXN5_C PEG_TXN5 PEG_TXN4_C PEG_TXN4 PEG_TXN3PEG_TXN3_C PEG_TXN2PEG_TXN2_C PEG_TXN1PEG_TXN1_C PEG_TXN0PEG_TXN0_C PEG_TXP15PEG_TXP15_C PEG_TXP14PEG_TXP14_C PEG_TXP13PEG_TXP13_C PEG_TXP12PEG_TXP12_C PEG_TXP11PEG_TXP11_C PEG_TXP10PEG_TXP10_C PEG_TXP9PEG_TXP9_C PEG_TXP8_C PEG_TXP8 PEG_TXP7_C PEG_TXP7 PEG_TXP6_C PEG_TXP6 PEG_TXP5PEG_TXP5_C PEG_TXP4PEG_TXP4_C PEG_TXP3PEG_TXP3_C PEG_TXP2PEG_TXP2_C PEG_TXP1PEG_TXP1_C PEG_TXP0PEG_TXP0_C H_PROCHOT# H_THERM +1.05V_VTT +1.05V_VTT +1.05V_VTT +1.5V_SUS +3.3V_RUN DMI_RXP09 DMI_TXP19 DMI_TXP29 DMI_TXP39 DMI_RXP19 DMI_TXN09 DMI_RXP29 DMI_RXP39 DMI_RXN09 DMI_TXN19 DMI_TXN29 DMI_TXN39 DMI_TXP09 DMI_RXN19 DMI_RXN29 DMI_RXN39 H_PWRGOOD10 PM_DRAM_PWRGD9 H_THERM10 H_PECI10 PLTRST#9,14,25,31 H_VTTPWRGD32 CLK_CPU_BCLKP 10 CLK_CPU_BCLKN 10 CLK_PCIE_3GPLLN 8 CLK_PCIE_3GPLLP 8 DDR3_DRAMRST# 12,13 PM_EXTTS#0 12 PM_EXTTS#1 13 H_CPUDET#25 PM_SYNC9 PEG_RXN15 14 PEG_RXN14 14 PEG_RXN13 14 PEG_RXN12 14 PEG_RXN11 14 PEG_RXN10 14 PEG_RXN9 14 PEG_RXN8 14 PEG_RXN7 14 PEG_RXN6 14 PEG_RXN5 14 PEG_RXN4 14 PEG_RXN3 14 PEG_RXN2 14 PEG_RXN1 14 PEG_RXN0 14 PEG_RXP15 14 PEG_RXP14 14 PEG_RXP13 14 PEG_RXP12 14 PEG_RXP11 14 PEG_RXP10 14 PEG_RXP9 14 PEG_RXP8 14 PEG_RXP7 14 PEG_RXP6 14 PEG_RXP5 14 PEG_RXP4 14 PEG_RXP3 14 PEG_RXP2 14 PEG_RXP1 14 PEG_RXP0 14 PEG_TXN15 14 PEG_TXN14 14 PEG_TXN13 14 PEG_TXN12 14 PEG_TXN11 14 PEG_TXN10 14 PEG_TXN9 14 PEG_TXN8 14 PEG_TXN7 14 PEG_TXN6 14 PEG_TXN5 14 PEG_TXN4 14 PEG_TXN3 14 PEG_TXN2 14 PEG_TXN1 14 PEG_TXN0 14 PEG_TXP15 14 PEG_TXP14 14 PEG_TXP13 14 PEG_TXP12 14 PEG_TXP11 14 PEG_TXP10 14 PEG_TXP9 14 PEG_TXP8 14 PEG_TXP7 14 PEG_TXP6 14 PEG_TXP5 14 PEG_TXP4 14 PEG_TXP3 14 PEG_TXP2 14 PEG_TXP1 14 PEG_TXP0 14 PM_THRMTRIP# 34 XDP_DBRESET# 9 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 1/4(HOST&PEX) 1A Wednesday, February 10, 2010 UM8B DIS 3 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 1/4(HOST&PEX) 1A Wednesday, February 10, 2010 UM8B DIS 3 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 1/4(HOST&PEX) 1A Wednesday, February 10, 2010 UM8B DIS 3 46 03 FDI_FSYNC can gang all these 4 signals together and tie them with only one 1K resistor to GND ( Check list 1.0 ). Discrete Only For ITP CLk GND GND DPLL_REF_SSCLK DPLL_REF_SSCLK# DIS UMA PCH PCH JTAG MAPPING Use a voltage divider with VDDQ (1.5 V) rail (ON in S3) and resistor combination of 1.1K ± (to VDDQ)/3K ± (to GND) to convert to processor VTT level. DPLL_REF_SSCLK/DPLL_REF_SSCLK#: Embedded Display Port PLL Differential Clock in. Intel Suggest to reserve 0 ohm below for CPU AP29 and AR29 pins. (DS 403777 Page 81) DG(V1.0),P79: should be tied to GND (through 1K ±5% resistors), if these signals are left floating, there are nofunctional impacts but a small amount of power (~15 mW) maybe wasted. DG(V1.1) P83: FDI_FSYNC[0], FDI_FSYNC[1],FDI_LSYN[0],FDI_LSYN[1] can be ganged together with one resistor. CPU THERMTRIP TP22TP22 C473 0.1U/ 10V/X7RC473 0.1U/ 10V/X7R C449 0.1U/ 10V/X7RC449 0.1U/ 10V/X7R R318 *0_NCR318 *0_NC C463 0.1U/ 10V/X7RC463 0.1U/ 10V/X7R C484 0.1U/ 10V/X7RC484 0.1U/ 10V/X7R R131 3K/F R131 3K/F R315 750/F_4R315 750/F_4 TP5TP5 C467 0.1U/ 10V/X7RC467 0.1U/ 10V/X7R R137 49.9/F_4R137 49.9/F_4 R114 49.9/F_4R114 49.9/F_4 R185*2.2K/J_4_NC R185*2.2K/J_4_NC TP13TP13 TP30TP30 R68 24.9/F_4R68 24.9/F_4 CLOCKS MISC THERMAL DDR3 MISC JTAG & BPM PWR MANAGEMENT U14B IC,AUB_CFD_rPGA,R1P0 CLOCKS MISC THERMAL DDR3 MISC JTAG & BPM PWR MANAGEMENT U14B IC,AUB_CFD_rPGA,R1P0 SM_RCOMP[1] AM1 SM_RCOMP[2] AN1 SM_DRAMRST# F6 SM_RCOMP[0] AL1 BCLK# B16 BCLK A16 BCLK_ITP# AT30 BCLK_ITP AR30 PEG_CLK# D16 PEG_CLK E16 DPLL_REF_SSCLK# A17 DPLL_REF_SSCLK A18 CATERR#AK14 COMP3AT23 PECIAT15 PROCHOT#AN26 THERMTRIP#AK15 RESET_OBS#AP26 VCCPWRGOOD_1AN14 VCCPWRGOOD_0AN27 SM_DRAMPWROKAK13 VTTPWRGOODAM15 RSTIN#AL14 PM_EXT_TS#[0] AN15 PM_EXT_TS#[1] AP15 PRDY# AT28 PREQ# AP27 TCK AN28 TMS AP28 TRST# AT27 TDI AT29 TDO AR27 TDI_M AR29 TDO_M AP29 DBR# AN25 BPM#[0]AJ22 BPM#[1]AK22 BPM#[2]AK24 BPM#[3]AJ24 BPM#[4]AJ25 BPM#[5]AH22 BPM#[6]AK23 BPM#[7]AH23 COMP2AT24 PM_SYNCAL15 TAPPWRGOODAM26 COMP1G16 COMP0AT26 SKTOCC#AH24 C455 0.1U/ 10V/X7RC455 0.1U/ 10V/X7R C452 0.1U/ 10V/X7RC452 0.1U/ 10V/X7R TP11TP11 R19 1K/F_4R19 1K/F_4 C509 0.1U/ 10V/X7RC509 0.1U/ 10V/X7R C447 0.1U/ 10V/X7RC447 0.1U/ 10V/X7R R126 20/F_4R126 20/F_4 C471 0.1U/ 10V/X7RC471 0.1U/ 10V/X7R R98 51/J_4 R98 51/J_4 TP12TP12 C474 0.1U/ 10V/X7RC474 0.1U/ 10V/X7R TP18TP18 C459 0.1U/ 10V/X7RC459 0.1U/ 10V/X7R R134 1.5K/F_4R134 1.5K/F_4 R110 *68/J_4_NCR110 *68/J_4_NC C510 0.1U/ 10V/X7RC510 0.1U/ 10V/X7R C464 0.1U/ 10V/X7RC464 0.1U/ 10V/X7R R70 130/F_4R70 130/F_4 P C I E X P R E S S - - G R A P H I C S DMI I n t e l ( R ) F D I U14A IC,AUB_CFD_rPGA,R1P0 P C I E X P R E S S - - G R A P H I C S DMI I n t e l ( R ) F D I U14A IC,AUB_CFD_rPGA,R1P0 DMI_RX#[0]A24 DMI_RX#[1]C23 DMI_RX#[2]B22 DMI_RX#[3]A21 DMI_RX[0]B24 DMI_RX[1]D23 DMI_RX[2]B23 DMI_RX[3]A22 DMI_TX#[0]D24 DMI_TX#[1]G24 DMI_TX#[2]F23 DMI_TX#[3]H23 DMI_TX[0]D25 DMI_TX[1]F24 DMI_TX[3]G23 DMI_TX[2]E23 FDI_TX#[0]E22 FDI_TX#[1]D21 FDI_TX#[2]D19 FDI_TX#[3]D18 FDI_TX#[4]G21 FDI_TX#[5]E19 FDI_TX#[6]F21 FDI_TX#[7]G18 FDI_TX[0]D22 FDI_TX[1]C21 FDI_TX[2]D20 FDI_TX[3]C18 FDI_TX[4]G22 FDI_TX[5]E20 FDI_TX[6]F20 FDI_TX[7]G19 FDI_FSYNC[0]F17 FDI_FSYNC[1]E17 FDI_INTC17 FDI_LSYNC[0]F18 FDI_LSYNC[1]D17 PEG_ICOMPI B26 PEG_ICOMPO A26 PEG_RBIAS A25 PEG_RCOMPO B27 PEG_RX#[0] K35 PEG_RX#[1] J34 PEG_RX#[2] J33 PEG_RX#[3] G35 PEG_RX#[4] G32 PEG_RX#[5] F34 PEG_RX#[6] F31 PEG_RX#[7] D35 PEG_RX#[8] E33 PEG_RX#[9] C33 PEG_RX#[10] D32 PEG_RX#[11] B32 PEG_RX#[12] C31 PEG_RX#[13] B28 PEG_RX#[14] B30 PEG_RX#[15] A31 PEG_RX[0] J35 PEG_RX[1] H34 PEG_RX[2] H33 PEG_RX[3] F35 PEG_RX[4] G33 PEG_RX[5] E34 PEG_RX[6] F32 PEG_RX[7] D34 PEG_RX[8] F33 PEG_RX[9] B33 PEG_RX[10] D31 PEG_RX[11] A32 PEG_RX[12] C30 PEG_RX[13] A28 PEG_RX[14] B29 PEG_RX[15] A30 PEG_TX#[0] L33 PEG_TX#[1] M35 PEG_TX#[2] M33 PEG_TX#[3] M30 PEG_TX#[4] L31 PEG_TX#[5] K32 PEG_TX#[6] M29 PEG_TX#[7] J31 PEG_TX#[8] K29 PEG_TX#[9] H30 PEG_TX#[10] H29 PEG_TX#[11] F29 PEG_TX#[12] E28 PEG_TX#[13] D29 PEG_TX#[14] D27 PEG_TX#[15] C26 PEG_TX[0] L34 PEG_TX[1] M34 PEG_TX[2] M32 PEG_TX[3] L30 PEG_TX[4] M31 PEG_TX[5] K31 PEG_TX[6] M28 PEG_TX[7] H31 PEG_TX[8] K28 PEG_TX[9] G30 PEG_TX[10] G29 PEG_TX[11] F28 PEG_TX[12] E27 PEG_TX[13] D28 PEG_TX[14] C27 PEG_TX[15] C25 TP24TP24 R86 0 R86 0 R66 750/F_4R66 750/F_4 C380 *0.1U_NC 10 C380 *0.1U_NC 10 1 2 Q11 *MMST3904-7-F_NC Q11 *MMST3904-7-F_NC 2 1 3 R128 10K/J_4R128 10K/J_4 C450 0.1U/ 10V/X7RC450 0.1U/ 10V/X7R C485 0.1U/ 10V/X7RC485 0.1U/ 10V/X7R C453 0.1U/ 10V/X7RC453 0.1U/ 10V/X7R R130 1.1K/F R130 1.1K/F R319 *0_NCR319 *0_NC TP7TP7 TP14TP14 R107 *0_NCR107 *0_NC Q12 *2N7002W-7-F_NC Q12 *2N7002W-7-F_NC2 3 1 C469 0.1U/ 10V/X7RC469 0.1U/ 10V/X7R TP21TP21 C493 0.1U/ 10V/X7RC493 0.1U/ 10V/X7R TP9TP9 R69 100/F_4R69 100/F_4 C472 0.1U/ 10V/X7RC472 0.1U/ 10V/X7R C456 0.1U/ 10V/X7RC456 0.1U/ 10V/X7R TP2TP2 C460 0.1U/ 10V/X7RC460 0.1U/ 10V/X7R C448 0.1U/ 10V/X7RC448 0.1U/ 10V/X7R TP29TP29 C497 0.1U/ 10V/X7RC497 0.1U/ 10V/X7R R59 49.9/F_4R59 49.9/F_4 TP17TP17 TP3TP3 R129 *12.4K/F_NCR129 *12.4K/F_NC TP8TP8 C480 0.1U/ 10V/X7RC480 0.1U/ 10V/X7R C451 0.1U/ 10V/X7RC451 0.1U/ 10V/X7R R279 *10M_NC R279 *10M_NC R127 10K/J_4R127 10K/J_4 C483 0.1U/ 10V/X7RC483 0.1U/ 10V/X7R TP25TP25 C466 0.1U/ 10V/X7RC466 0.1U/ 10V/X7R R20 1K/F_4R20 1K/F_4 R58 *68/J_4_NCR58 *68/J_4_NC C470 0.1U/ 10V/X7RC470 0.1U/ 10V/X7R C454 0.1U/ 10V/X7RC454 0.1U/ 10V/X7R R125 20/F_4R125 20/F_4 TP19TP19 C457 0.1U/ 10V/X7RC457 0.1U/ 10V/X7R TP10TP10 R18 49.9/F_4R18 49.9/F_4 R314 49.9/F_4R314 49.9/F_4 TP16TP16 TP15TP15 C487 0.1U/ 10V/X7RC487 0.1U/ 10V/X7R 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 8 A A B B C C D D M_A_DM1 M_A_DM0 M_A_DM3 M_A_DM2 M_A_DM5 M_A_DM6 M_A_DM4 M_A_DM7 M_A_DQSP0 M_A_A1 M_A_A9 M_A_A10 M_A_A11 M_A_A8 M_A_A12 M_A_A15 M_A_A14 M_A_A13 M_A_A2 M_A_A3 M_A_A0 M_A_A5 M_A_A6 M_A_A7 M_A_A4 M_B_DQ2 M_B_DQ3 M_B_DQ34 M_B_DQ35 M_B_DQ37 M_B_DQ36 M_B_DQ39 M_B_DQ38 M_B_DQ32 M_B_DQ41 M_B_DQ40 M_B_DQ46 M_B_DQ47 M_B_DQ44 M_B_DQ45 M_B_DQ43 M_B_DQ42 M_B_DQ33 M_B_DQ53 M_B_DQ51 M_B_DQ50 M_B_DQ63 M_B_DQ62 M_B_DQ56 M_B_DQ57 M_B_DQ48 M_B_DQ54 M_B_DQ55 M_B_DQ52 M_B_DQ49 M_B_DQ58 M_B_DQ59 M_B_DQ61 M_B_DQ60 M_B_DQ6 M_B_DQ7 M_B_DQ4 M_B_DQ5 M_B_DQ0 M_B_DQ10 M_B_DQ11 M_B_DQ13 M_B_DQ12 M_B_DQ15 M_B_DQ14 M_B_DQ8 M_B_DQ9 M_B_DQ1 M_B_DQ18 M_B_DQ19 M_B_DQ21 M_B_DQ20 M_B_DQ23 M_B_DQ22 M_B_DQ16 M_B_DQ25 M_B_DQ24 M_B_DQ30 M_B_DQ31 M_B_DQ28 M_B_DQ29 M_B_DQ27 M_B_DQ26 M_B_DQ17 M_B_DQSN0 M_B_DQSP0 M_B_A1 M_B_A9 M_B_A10 M_B_A11 M_B_A8 M_B_A12 M_B_A15 M_B_A14 M_B_A13 M_B_A2 M_B_A3 M_B_A0 M_B_A5 M_B_A6 M_A_DQ2 M_B_A7 M_B_A4 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_B_DM1 M_B_DM0 M_B_DM3 M_B_DM2 M_B_DM5 M_B_DM6 M_B_DM4 M_B_DM7 M_A_DQ7 M_A_DQ10 M_A_DQ11 M_A_DQ13 M_A_DQ12 M_A_DQ14 M_A_DQ15 M_A_DQ8 M_A_DQ9 M_A_DQ0 M_A_DQ18 M_A_DQ19 M_A_DQ21 M_A_DQ20 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ31 M_A_DQ30 M_A_DQ28 M_A_DQ29 M_A_DQ27 M_A_DQ26 M_A_DQ25 M_A_DQ16 M_A_DQ17 M_A_DQ1 M_A_DQ34 M_A_DQ35 M_A_DQ37 M_A_DQ36 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ47 M_A_DQ46 M_A_DQ44 M_A_DQ45 M_A_DQ43 M_A_DQ42 M_A_DQ41 M_A_DQ32 M_A_DQ54 M_A_DQ52 M_A_DQ53 M_A_DQ51 M_A_DQ50 M_A_DQ58 M_A_DQ59 M_A_DQ61 M_A_DQ60 M_A_DQ62 M_A_DQ63 M_A_DQ56 M_A_DQ55 M_A_DQ49 M_A_DQ48 M_A_DQ57 M_A_DQ33 M_A_DQSN6 M_A_DQSN0 M_A_DQSN7 M_A_DQSN1 M_A_DQSN2 M_A_DQSN3 M_A_DQSN4 M_A_DQSN5 M_A_DQSP1 M_A_DQSP2 M_A_DQSP3 M_A_DQSP4 M_A_DQSP5 M_A_DQSP6 M_A_DQSP7 M_B_DQSN1 M_B_DQSN2 M_B_DQSN3 M_B_DQSN4 M_B_DQSN5 M_B_DQSN6 M_B_DQSN7 M_B_DQSP1 M_B_DQSP2 M_B_DQSP3 M_B_DQSP4 M_B_DQSP5 M_B_DQSP6 M_B_DQSP7 M_A_DQ[0..63]12 M_A_BS#112 M_A_BS#212 M_A_RAS#12 M_A_WE#12 M_A_CAS#12 M_A_BS#012 M_A_CLKP1 12 M_A_CKE1 12 M_A_CLKN1 12 M_A_CLKN0 12 M_A_CKE0 12 M_A_CLKP0 12 M_A_ODT0 12 M_A_CS#1 12 M_A_CS#0 12 M_A_ODT1 12 M_A_DM[0..7] 12 M_A_A[0..15] 12 M_A_DQSN[0..7] 12 M_A_DQSP[0..7] 12 M_B_DQ[0..63]13 M_B_RAS#13 M_B_WE#13 M_B_CAS#13 M_B_BS#013 M_B_BS#113 M_B_BS#213 M_B_CLKP1 13 M_B_CKE1 13 M_B_CLKN1 13 M_B_CLKN0 13 M_B_CKE0 13 M_B_CLKP0 13 M_B_ODT0 13 M_B_CS#1 13 M_B_CS#0 13 M_B_ODT1 13 M_B_DM[0..7] 13 M_B_A[0..15] 13 M_B_DQSN[0..7] 13 M_B_DQSP[0..7] 13 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 2/4(DDR) 1A Wednesday, February 10, 2010 UM8B DIS 4 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 2/4(DDR) 1A Wednesday, February 10, 2010 UM8B DIS 4 46 Size Document Number Rev Date: Sheet of Quanta Computer Inc. PROJECT : PROCESSER 2/4(DDR) 1A Wednesday, February 10, 2010 UM8B DIS 4 46 04 DM signals are not present on Clarkfield processor. All DM signal can be left as NC on Clarkfield and connect directly to GND on So-DIMM side for Clarkfield design only AUBURNDALE/CLARKSFIELD PROCESSOR (DDR3) Channel A DQ[15,32,48,54], DM[5] Requires minimum 12mils spacing with all other signals, including data signals. Channel B DQ[16,18,36,42,56,57,60,61,62] Requires minimum 12mils spacing with all other signals, including data signals. D D R S Y S T E M M E M O R Y B U14D IC,AUB_CFD_rPGA,R1P0 D D R S Y S T E M M E M O R Y B U14D IC,AUB_CFD_rPGA,R1P0 SB_BS[0]AB1 SB_BS[1]W5 SB_BS[2]R7 SB_CAS#AC5 SB_RAS#Y7 SB_WE#AC6 SB_CK[0] W8 SB_CK[1] V7 SB_CK#[0] W9 SB_CK#[1] V6 SB_CKE[0] M3 SB_CKE[1] M2 SB_CS#[0] AB8 SB_CS#[1] AD6 SB_ODT[0] AC7 SB_ODT[1] AD1 SB_DM[0] D4 SB_DM[1] E1 SB_DM[2] H3 SB_DM[3] K1 SB_DM[4] AH1 SB_DM[5] AL2 SB_DM[6] AR4 SB_DM[7] AT8 SB_DQS[4] AG2 SB_DQS#[4] AH2 SB_DQS[5] AL5 SB_DQS#[5] AL4 SB_DQS[6] AP5 SB_DQS#[6] AR5 SB_DQS[7] AR7 SB_DQS#[7] AR8 SB_DQS[0] C5 SB_DQS#[0] D5 SB_DQS[1] E3 SB_DQS#[1] F4 SB_DQS[2] H4 SB_DQS#[2] J4 SB_DQS[3] M5 SB_DQS#[3] L4 SB_MA[0] U5 SB_MA[1] V2 SB_MA[2] T5 SB_MA[3] V3 SB_MA[4] R1 SB_MA[5] T8 SB_MA[6] R2 SB_MA[7] R6 SB_MA[8] R4 SB_MA[9] R5 SB_MA[10] AB5 SB_MA[11] P3 SB_MA[12] R3 SB_MA[13] AF7 SB_MA[14] P5 SB_MA[15] N1 SB_DQ[0]B5 SB_DQ[1]A5 SB_DQ[2]C3 SB_DQ[3]B3 SB_DQ[4]E4 SB_DQ[5]A6 SB_DQ[6]A4 SB_DQ[7]C4 SB_DQ[8]D1 SB_DQ[9]D2 SB_DQ[10]F2 SB_DQ[11]F1 SB_DQ[12]C2 SB_DQ[13]F5 SB_DQ[14]F3 SB_DQ[15]G4 SB_DQ[16]H6 SB_DQ[17]G2 SB_DQ[18]J6 SB_DQ[19]J3 SB_DQ[20]G1 SB_DQ[21]G5 SB_DQ[22]J2 SB_DQ[23]J1 SB_DQ[24]J5 SB_DQ[25]K2 SB_DQ[26]L3 SB_DQ[27]M1 SB_DQ[28]K5 SB_DQ[29]K4 SB_DQ[30]M4 SB_DQ[31]N5 SB_DQ[32]AF3 SB_DQ[33]AG1 SB_DQ[34]AJ3 SB_DQ[35]AK1 SB_DQ[36]AG4 SB_DQ[37]AG3 SB_DQ[38]AJ4 SB_DQ[39]AH4 SB_DQ[40]AK3 SB_DQ[41]AK4 SB_DQ[42]AM6 SB_DQ[43]AN2 SB_DQ[44]AK5 SB_DQ[45]AK2 SB_DQ[46]AM4 SB_DQ[47]AM3 SB_DQ[48]AP3 SB_DQ[49]AN5 SB_DQ[50]AT4 SB_DQ[51]AN6 SB_DQ[52]AN4 SB_DQ[53]AN3 SB_DQ[54]AT5 SB_DQ[55]AT6 SB_DQ[56]AN7 SB_DQ[57]AP6 SB_DQ[58]AP8 SB_DQ[59]AT9 SB_DQ[60]AT7 SB_DQ[61]AP9 SB_DQ[62]AR10 SB_DQ[63]AT10 D D R S Y S T E M M E M O R Y A U14C IC,AUB_CFD_rPGA,R1P0 D D R S Y S T E M M E M O R Y A U14C IC,AUB_CFD_rPGA,R1P0 SA_BS[0]AC3 SA_BS[1]AB2 SA_BS[2]U7 SA_CAS#AE1 SA_RAS#AB3 SA_WE#AE9 SA_CK[0] AA6 SA_CK[1] Y6 SA_CK#[0] AA7 SA_CK#[1] Y5 SA_CKE[0] P7 SA_CKE[1] P6 SA_CS#[0] AE2 SA_CS#[1] AE8 SA_ODT[0] AD8 SA_ODT[1] AF9 SA_DM[0] B9 SA_DM[1] D7 SA_DM[2] H7 SA_DM[3] M7 SA_DM[4] AG6 SA_DM[5] AM7 SA_DM[6] AN10 SA_DM[7] AN13 SA_DQS[0] C8 SA_DQS#[0] C9 SA_DQS[1] F9 SA_DQS#[1] F8 SA_DQS[2] H9 SA_DQS#[2] J9 SA_DQS[3] M9 SA_DQS#[3] N9 SA_DQS[4] AH8 SA_DQS#[4] AH7 SA_DQS[5] AK10 SA_DQS#[5] AK9 SA_DQS[6] AN11 SA_DQS#[6] AP11 SA_DQS[7] AR13 SA_DQS#[7] AT13 SA_MA[0] Y3 SA_MA[1] W1 SA_MA[2] AA8 SA_MA[3] AA3 SA_MA[4] V1 SA_MA[5] AA9 SA_MA[6] V8 SA_MA[7] T1 SA_MA[8] Y9 SA_MA[9] U6 SA_MA[10] AD4 SA_MA[11] T2 SA_MA[12] U3 SA_MA[13] AG8 SA_MA[14] T3 SA_MA[15] V9 SA_DQ[0]A10 SA_DQ[1]C10 SA_DQ[2]C7 SA_DQ[3]A7 SA_DQ[4]B10 SA_DQ[5]D10 SA_DQ[6]E10 SA_DQ[7]A8 SA_DQ[8]D8 SA_DQ[9]F10 SA_DQ[10]E6 SA_DQ[11]F7 SA_DQ[12]E9 SA_DQ[13]B7 SA_DQ[14]E7 SA_DQ[15]C6 SA_