60进制仿真 中文版60进制仿真 中文版
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Sequential logic circuit design
60进制计数器是从0开始到59循环,
图1
图1是没有运行的状态
I design 60 binary counter circuit as shown above
The frequency of the input voltage to the 5Hz frequency processing, and then to 74...
60进制仿真 中文版
Answer Sheet Assignment
Page of Student’s name:
Sequential logic circuit design
60进制计数器是从0开始到59循环,
图1
图1是没有运行的状态
I design 60 binary counter circuit as shown above
The frequency of the input voltage to the 5Hz frequency processing, and then to 74LS47 decoder 74LS161 counter chip. 4 74LS47 decoder input to eight outputs of the seven-segment LED display numbers (74LS47 high electrical frequency).
In order to realize the digital display 0-59 cycles, and I was added in the circuit of the Not gate.
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图2
图2是工作状态显示31
Answer Sheet Assignment
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CLK
RCO
图3
图3是The 74LS161 pulse waveform
Q1
Q2
Q3
Q4
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结论:
我的60进制计数器能正常从00到59运行,然后从59到00,所以我的仿真成功。
Physical structures
Build the actual circuit use decoder 74LS47 and counter 74LS161 and chip 74LS00 This circuit variously realizes the digital display 0-59 cycles is a 60 binary counter. Conclusion:
Build this circuit is very successful.
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