四输入与非门版图

四输入与非门版图 作业报告 作业目:画一个4输入与非门的版图，w=5~20. L =2~10. 作业要求:(1)画出版图并进行规则检查，提取T-spice 网文件 (2)根据从版图中提取的参数，用T-space软件进行仿真，观测器输出波形。 (3)采用CMOS 2 um工艺。 (4)撰写设计报告，设计报告如有雷同均视为不及格，请各位妥善保管好自己的设计文档。 (5)提交报告的最后截止日期位6月10号。 一 四输入与非门电路图如下图所示: 四输入与非门的工作原理为: 四输入端CMOS与非门电路，其中包括四个串联的N沟道增强型MOS管和四个并联的P沟道增强型MOS管。每 个输入端连到一个N沟道和一个P沟道MOS管的栅极。当输入端A、B、C、D中只要有一个为低电平时，就会使与它相连的NMOS管截止，与它相 连的PMOS管导通，输出为高电平;仅当A、B、C、D全为高电平时，才会使四个串联的NMOS管都导通，使四个并联的 PMOS管都截止，输出为低电平。 真值表如下所示 : 二 版图的绘制 这次作业要求四输入与非门的宽和长的范围是w=5~20. L =2~10。我绘制的版图选取 W=16 um L=2um ，绘制的过程为: (1)绘制接合端口Abut (2)绘制电源Vdd和Gnd，以及相应端口 (3)绘制Nwell层 (4)绘制N阱节点 (5)绘制衬底节点 (6)绘制Nselect区和Pselect区 (7)绘制NMOS有源区和PMOS有源区 (8)绘制多晶硅层 (9)绘制NAND 4 的输入口 (10)绘制NAND 4 的输出口 (11)绘制NMOS有源区和PMOS的源极 三 T-spice仿真 在绘制完版图之后，经过设计规则检查无误后就可以提取网表进行仿真了。 (1)版图的网表提取结果为: * Circuit Extracted by Tanner Research's L-Edit Version 13.00 / Extract Version 13.00 ; * TDB File: D:\20113250\youwenhao-NAND4.tdb * Cell: Cell0 Version 1.03 * Extract Definition File: D:\Tanner EDA\Tanner Tools v13.0\ExampleSetup\lights.ext * Extract Date and Time: 06/10/2014 - 01:20 .include "C:\Users\Administrator\Desktop\ml5_20.md" V1 Vdd Gnd 5 va A Gnd PULSE (0 2.5 100n 2.5n 2.5n 100n 200n) vb B Gnd PULSE (0 2.5 50n 2.5n 2.5n 50n 100n) vc C Gnd PULSE (0 2.5 25n 2.5n 2.5n 25n 50n) vd D Gnd PULSE (0 2.5 12.5n 2.5n 2.5n 12.5n 25n) .tran 1n 400n .print tran v(A) v(B) v(C) v(D) v(Out) * Warning: Layers with Unassigned FRINGE Capacitance. * * * NODE NAME ALIASES * 1 = GND (34.5 , -41.5) * 2 = vdd (32, 15) * 3 = OUT (47.5 , 9) * 4 = D (84 , -6) * 5 = C (70.5 , -5.5) * 6 = B (59.5 , -6) * 7 = A (38 , -5) V1 Vdd Gnd 5 va A Gnd PULSE (0 12.5 500n 12.5n 12.5n 5100n 1000n) vb B Gnd PULSE (0 12.5 250n 12.5n 12.5n 250n 500n) vc C Gnd PULSE (0 12.5 125n 12.5n 12.5n 125n 250n) vd D Gnd PULSE (0 12.5 62.5n 12.5n 12.5n 62.5n 125n) .tran 1n 1000n .print tran v(D) v(C) v(B) v(A) v(Out)M1 Vdd 4 Out Vdd PMOS L=2u W=16u AD=88p PD=47u AS=60p PS=23.5u $ (44 37 46 53) M2 Out 5 Vdd Vdd PMOS L=2u W=16u AD=60p PD=23.5u AS=56p PS=23u $ (34.5 37 36.5 53) M3 Vdd 6 Out Vdd PMOS L=2u W=16u AD=56p PD=23u AS=112p PS=30u $ (25.5 37 27.5 53) M4 Out 7 Vdd Vdd PMOS L=2u W=16u AD=112p PD=30u AS=88p PS=47u $ (9.5 37 11.5 53) M5 Out 4 Out Gnd NMOS L=2u W=16u AD=120p PD=47u AS=60p PS=23.5u $ (44 0 46 16) M6 Out 5 Out Gnd NMOS L=2u W=16u AD=60p PD=23.5u AS=56p PS=23u $ (34.5 0 36.5 16) M7 Out 6 Out Gnd NMOS L=2u W=16u AD=56p PD=23u AS=112p PS=30u $ (25.5 0 27.5 16) M8 Out 7 Gnd Gnd NMOS L=2u W=16u AD=112p PD=30u AS=92p PS=47u $ (9.5 0 11.5 16) * Pins of element D1 are shorted: * D1 vdd vdd D_lateral $ (88 18.5 91 26.5) * Pins of element D2 are shorted: * D2 vdd vdd D_lateral $ (36 18.5 39.5 26.5) * Total Nodes: 11 * Total Elements: 10 * Total Number of Shorted Elements not written to the SPICE file: 0 * Output Generation Elapsed Time: 0.001 sec * Total Extract Elapsed Time: 0.746 sec .END (2)提取的网表经过T-spice运行后的文件为: T-Spice - Tanner SPICE T-Spice - Tanner SPICE Version 13.00 Standalone hardware lock Product Release ID: T-Spice Win32 13.00.20080321.01:01:33 Copyright ?1993-2008 Tanner EDA Opening output file "C:\Users\Administrator\Desktop\游文浩 20113250\youwenhao-NAND4.out" Parsing "C:\Users\Administrator\Desktop\游文浩 20113250\youwenhao-NAND4.spc" Initializing parser from header file "C:\Users\Administrator\Desktop\游文浩 20113250\header.sp" Including "C:\Users\Administrator\Desktop\ml5_20.md" Loaded MOSLevel2 model library, SPICE Level 2 MOSFET revision 1.0 Warning : Pulse period is too small, reset to rt + ft + pw = 5.125e-006 Accuracy and Convergence options: numndset|dchold = 100 Timestep and Integration options: relq|relchgtol = 0.0005 Model Evaluation options: dcap = 2 defnrb = 0 [sq] defnrd = 0 [sq] defnrs = 0 [sq] tnom = 25 [deg C] General options: search = C:\Users\Administrator\Desktop temp = 25 [deg C] threads = 4 Output options: acout = 1 ingold = 0 Device and node counts: MOSFETs - 8 MOSFET geometries - 8 BJTs - 0 JFETs - 0 MESFETs - 0 Diodes - 0 Capacitors - 0 Resistors - 0 Inductors - 0 Mutual inductors - 0 Transmission lines - 0 Coupled transmission lines - 0 Voltage sources - 5 Current sources - 0 VCVS - 0 VCCS - 0 CCVS - 0 CCCS - 0 V-control switch - 0 I-control switch - 0 Macro devices - 0 External C model instances - 0 HDL devices - 0 Subcircuits - 0 Subcircuit instances - 0 Independent nodes - 5 Boundary nodes - 6 Total nodes - 11 *** 1 WARNING MESSAGE GENERATED DURING SETUP Parsing 0.00 seconds Setup 0.01 seconds DC operating point 0.00 seconds Transient Analysis 0.11 seconds Overhead 1.50 seconds ----------------------------------------- Total 1.62 seconds Simulation completed with 1 Warning (3)仿真结果为: 四 作业

总结

初级经济法重点总结下载党员个人总结TXt高中句型全总结.doc高中句型全总结.doc理论力学知识点总结pdf

: 完成这次作业之后，我对于集成电路版图的绘制有了一个全新的认识，初步掌握了Tunner软件的使用以及T-spice仿真软件的使用。在这次完成作业的过程中遇到了很多的困难，在此还要特别感谢易助教的帮助，正是在易助教的耐心帮助下，我才能最终完成这次作业。这次版图的仿真的结果说明这次版图的绘制是正确的。