8080 汇编（8080 assembly）

8080 汇编（8080 assembly） 8080 汇编(8080 assembly) (long transfer) JMP transfer instructions unconditionally CALL procedure CALL RET/RETF process returns. 2 > conditional transfer instructions (short transfer, -128 to + 127) When and only if (SF XOR OF) = 1, OP1 < OP2) JA/JNBE is not less than or not equal to. JAE/JNB is greater than or equal to transfer. JB/JNAE is less than the transfer. JBE/JNA is less than or equal to transfer. The above four, test the result of unsigned integer arithmetic (mark C and Z). JG/JNLE is greater than the transfer. JGE/JNL is greater than or equal to transfer. JL/JNGE is less than the transfer. JLE/JNG is less than or equal to transfer. The above four, the test band symbol integer arithmetic result (sign S, O and Z). JE/JZ is the transfer. JNE/JNZ does not equal time transfer. JC is transferred when it is in. When JNC is not entered, it is transferred. When JNO does not overflow, transfer. The JNP/JPO parity is shifted when odd. The JNS symbol bit is moved when "0". JO overflow. The JP/JPE parity is transferred when the evenness is even. The JS symbol is moved when "1". 3 > loop control instruction (short shift) LOOP CX is not a zero cycle. LOOPE/LOOPZ CX is not zero and marks Z = 1. LOOPNE/LOOPNZ CX is not zero and marks Z = 0. PUSH and POP Function: press the operands into or out of the stack Syntax: PUSH operand POP operands Format: PUSH r PUSH data POP r POP M PUSHF POPF, PUSHA POPA Function: stack instruction group Format: PUSHF POPF PUSHA POPA LEA, typical vmlinux.lds, LES Function: take the address to register Grammar: LEA r, m LDS r, m LES r, m XLAT (XLATB) Function: check table instruction Syntax: XLAT XLAT m Arithmetic instruction ADD, ADC Function: add instruction Syntax: ADD OP1, OP2 ADC OP1, OP2 Format: ADD r1, r2 ADD r, m ADD m, r ADD r, data Impact signs: C, P, A, Z, S, O SUB, SBB Function: subtraction instruction Syntax: SUB OP1, OP2 SBB OP1, OP2 Format: SUB r1, r2 SUB r, m SUB m, r SUB r, data SUB m, data Impact signs: C, P, A, Z, S, O INC and DEC Function: add or subtract the value of the OP Syntax: INC OP DEC OP Format: INC r/m DEC r/m Impact signs: P, A, Z, S, O NEG Function: reverse symbol of OP (binary complement) Grammar: NEG OP Format: NEG r/m Impact signs: C, P, A, Z, S, O The MUL, IMUL Function: multiplication instructions Grammar: MUL OP IMUL OP Format: MUL r/m IMUL r/m Impact sign: C, P, A, Z, S, O (only IMUL will affect S logo) DIV, IDIV Function: division instruction Syntax: DIV OP IDIV OP Format: DIV r/m IDIV r/m CBW, CWD Function: symbol number extension instruction Grammar: CBW CWD AAA, AAS, AAM, AAD Function: non-pressure BCD code operation adjustment instruction Grammar: AAA AAS AAM AAD Impact signs: A, C (AAA, AAS) S, Z, P (AAM, AAD) DAA, DAS Function: compressed BCD code tuning instructions Syntax: DAA DAS Impact signs: C, P, A, Z, S Bit operation instruction set AND, OR, XOR, NOT TEST Function: performs the logical operation between BIT and BIT Grammar: AND r/m, r/m/data OR r/m, r/m/data XOR r/m, r/m/data TEST r/m, r/m/data NOT r/m The impact sign: C, O, P, Z, S (where C and O are set to 0) NOT command does NOT affect any flag bit SHR, SHL, SAR, SAL Function: shift instruction Syntax: SHR/m, data/CL SHL r/m, data/CL SAR r/m, data/CL SAL r/m, data/CL Impact signs: C, P, Z, S, O ROR, ROL, RCR, RCL Function: loop shift instruction Syntax: ROR r/m, data/CL ROL r/m, data/CL RCR r/m, data/CL RCL r/m, data/CL Impact signs: C, P, Z, S, O Program process control instruction set CLC, on STC, CMC Function: sets the carry flag Grammar: CLC STC CMC Mark bit: C CLD, STD Function: setting the direction sign Syntax: CLD STD Mark position: D CLI, STI Function: sets interrupt flag Syntax: CLI STI Mark bit: I CMP Function: compare OP1 and OP2 values Syntax: CMP r/m, r/m/data Mark bit: C, P, A, Z, O JMP Function: jump to the specified address to execute Syntax: JMP address JXX Function: jump to the specified address when a specific condition is established Syntax: JXX address Note: A: ABOVE, when C = 0, Z = 0 B: BELOW, when C = 1 C: CARRY, when the CXZ: CXZ: the value of the CX register is 0 (ZERO) E: EQUAL, when Z is EQUAL to 1 G: GREATER (GREATER than), when Z = 0 and S = 0 L: LESS than) when S is not zero N: NOT (on the contrary) need to be used in conjunction with other symbols O: OVERFLOW, O = 1 P: PARITY, P = 1 PE: PARITY EVEN, P = 1 is established PO: PARITY ODD, P = 0 S: SIGN, S = 1 Z: ZERO, Z = 1 LOOP Function: circular instruction set Syntax: LOOP address LOOPE (Z) Address: LOOPNE (Z) address Flag position: no CALL, RET Function: subroutine call, return instruction Grammar: CALL address RET RET Flag bit: no INT, IRET Function: interrupt call and return instructions Grammar: INT n IRET Flag position: when executing INT, the CPU will automatically push the value of the flag register to the stack, and when IRET is executed, the flag value in the stack will be bounced back to the register String operation instruction set MOVSB MOVSW, MOVSD Function: string transfer instruction MOVSB MOVSW MOVSD Flag bit: no CMPSB CMPSW, CMPSD Function: string comparison instruction Syntax: CMPSB CMPSW CMPSD Mark bit: C, P, Z, S, O SCASB, SCASW Function: string search instruction Grammar: SCASB SCASW Mark bit: C, P, Z, S, O LODSB LODSW, STOSB STOSW Function: string load or storage instruction Grammar: LODSB LODSW stosstosw Flag position: no REP. REPE, REPNE Function: repeat the prefix instruction set Syntax: the REP command S REPE instruction S Mark position: according to order S Method 1: switch up and down Method two: equivalent substitution method The most difficult to master is a part of assembly knowledge Push - pop push eax to pop eax Je - JNZ je 41000 changed JNZ 41000 Add -- sub add ecx, 2, sub ecx, minus 2 JE to JMP Change the TEST XOR JLE change JL NOP. JMP address MOV and XOR transposition The ADD transposition JE to JMP 75 to 74 The TEST to the OR Jbe to jb 38 to 37 CALL and MOV transposition JA to JG Change JNZ JMP Change the TEST AND Find a new directive equivalent to JNZ The general change is JNZ -- ja You can also change it to JNZ -- jno Data transfer instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? They transmit data between the memory and the register, the register, and the input and output ports. 1. General data transfer instructions. MOV sends word or byte. The MOVSX first symbol expands, then transmits. MOVZX starts with zero extension and then transfers. PUSH the word into the stack. POP puts the word up on the stack. PUSHA puts AX, CX, DX, BX, SP, BP, SI, and DI on the stack. POPA pops up the stack of DI, SI, BP, SP, BX, DX, CX and AX. PUSHAD puts EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI on the stack in turn. POPAD pops up the stack of EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX. BSWAP swap the order of bytes in 32-bit registers XCHG exchange word or byte. (at least one operand is a register and the segment register is not operable.) CMPXCHG compares and exchanges operands. (the second operand must be the accumulator AL/AX/EAX) The XADD first exchanges and then accumulates. (the result is in the first operand) XLAT byte lookup table transformation. ? ? BX point to the starting point of a 256 - byte list, AL for the table index value (0-255, namely 0 - FFH); Returns AL to check the results of the table. ([BX + AL] - > AL) 2. Input and output port instructions. IN I/O port input. (syntax: IN accumulator, {port ? DX}) OUT I/O port output. (syntax: OUT ? DX} {port, the accumulator) When the input output port is specified in an immediate way, the range is 0-255; When specified by register DX, The range is 0 minus 65535. 3. Destination address transfer instruction. LEA loads the valid address. Example: LEA DX, string; Save the offset address to DX. LDS passes the target pointer and loads the pointer contents into DS. Example: LDS SI, string; Save the address: offset address to DS: SI. LES passes the target pointer and loads the pointer contents into ES. Example: LES DI, string; Take the segment address: offset address to ES: DI. LFS passes the target pointer and loads the pointer content into FS. Example: LFS DI, string; Save the address: offset address to FS: DI. LGS passes the target pointer and loads the pointer content into GS. Example: LGS DI, string; Address: offset address to GS: DI. LSS passes the target pointer and loads the pointer contents into SS. Example: LSS DI, string; Save the address: offset address to SS: DI. 4. Flag transfer instruction. LAHF flag register transmission, load the mark into AH. The SAHF flag register is transmitted and the AH content is loaded into the flag register. PUSHF marks the stack. POPF marks the stack. PUSHD 32-bit marks are on the stack. POPD 32 bit marks out of the stack. Arithmetic operation instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? The ADD addition. ADC brings in addition. INC. ASCII adjustment of AAA addition. The decimal adjustment of DAA addition. SUB subtraction. SBB takes the borrowing and subtraction. DEC 1. NEC asks for the reverse. CMP. (the two operands are subtracted, and only the mark bits are modified and the results are not returned.) AAS subtraction of ASCII code adjustment. The decimal adjustment of DAS subtraction. MUL without symbol multiplication. IMUL integer multiplication. So these two things are going to return AH and AL (byte arithmetic), or DX and AX (word arithmetic), ASCII adjustment for AAM multiplication. DIV unsigned division. IDIV integer division. The above two results are sent back: Return the AL, the remainder of the return to AH, (byte arithmetic); Or the quotient back to AX, and the remainder to the DX, (word operation). The ASCII code adjustment of AAD division. CBW bytes are converted into words. Extend the symbol of the byte in the AL to AH The CWD word is converted into a double word. (expand the symbol in AX to the DX) CWDE is translated into two words. (expand the number of characters in AX to EAX) CDQ double word extension. (expand the symbol in EAX to EDX) 3. Logical operation instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? AND operations. OR OR operation. XOR. NOT to take back. The TEST TEST. (two operation Numbers and operation, only modify the mark bit, do not return the result). SHL logic moves to the left. SAL arithmetic left. (= SHL) SHR logic moves to the right. SAR arithmetic moves to the right. (= SHR) The ROL cycle moves to the left. The ROR cycle moves to the right. RCL moves to the left through the carry cycle. The RCR moves to the right through the carry cycle. The above eight shift instructions can be shifted up to 255 times. When displaced, you can use the operation code directly. Like SHL AX, 1. When shifted > 1, the register CL gives the number of shifts. Like MOV CL, 04 SHL AX, CL Iv. String instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DS: SI source string segment register: source string change address. ES: DI target string segment register: target string change address. CX repetition times counter. AL/AX scan value. D mark 0 indicates that SI and DI should be incrementally changed in repetitive operation; 1 represents the automatic reduction. The Z flag is used to control the end of the scan or comparison operation. MOVS string transmission. (MOVSB transmits character. MOVSW transmits word. MOVSD delivers double word.) CMPS comparison. (CMPSB comparison character. CMPSW comparison word. ) SCAS string scan. Compare the content of AL or AX with the target string, and the comparison results are reflected in the mark bit. LODS load string. The elements in the source string (words or bytes) are loaded into AL or AX. (LODSB transfer character. LODSW transmits word. LODSD delivers double word.) STOS save the string. It's the inverse of LODS. REP repeats when CX/ECX < > 0. REPE/REPZ when ZF = 1 or the result is equal, and CX/ECX < > 0 is repeated. REPNE/REPNZ when ZF = 0 or compare results are not equal, and CX/ECX < > 0 is repeated. REPC is repeated when CF = 1 and CX/ECX < > 0. REPNC is repeated when CF = 0 and CX/ECX < > 0. 5. Program transfer instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 > unconditional transfer instruction (long transfer) JMP transfer instructions unconditionally CALL procedure CALL RET/RETF process returns. 2 > conditional transfer instructions (short transitions, -128 to + 127) When and only if (SF XOR OF) = 1, OP1 JA/JNBE is not less than or equal to transfer. JAE/JNB is greater than or equal to transfer. JB/JNAE is less than the transfer. JBE/JNA is less than or equal to transfer. The above four, test the result of unsigned integer arithmetic (mark C and Z). JG/JNLE is greater than the transfer. JGE/JNL is greater than or equal to transfer. JL/JNGE is less than the transfer. JLE/JNG is less than or equal to transfer. The above four, the test band symbol integer arithmetic result (sign S, O and Z). JE/JZ is equal to transfer. JNE/JNZ does not equal time transfer. JC is moved when it is in. When JNC is not entered, it is transferred. When JNO does not overflow, transfer. The JNP/JPO parity is shifted when the odd is odd. The JNS symbol bit is moved when "0". JO overflow. JP/JPE parity is transferred even when the parity is even. The JS symbol is moved when "1". 3 > loop control instruction (short shift) LOOP CX is not a zero cycle. LOOPE/LOOPZ CX is not a zero and the Z = 1 cycle. The LOOPNE/LOOPNZ CX is not zero and the Z = 0 cycle. JCXZ CX is a zero time shift. JECXZ ECX is transferred at zero time. 4 > interrupt instructions INT interrupt instruction INTO overflow interrupt IRET interrupt returns 5 > processor control instructions The HLT processor pauses until an interrupt or reset signal continues. WAIT when the chip lead TEST is high, the CPU enters the WAIT state. ESC to external processor. LOCK locks the bus. NOP empty operation. STC sets carry flag bit. CLC clear carry flag bit. The CMC's carry flag is reversed. STD position marker. Clear direction of the CLD. The STI interrupt allows the bit. CLI clear interrupt allow bit. Vi. Pseudo-instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DW definition word (2 bytes). PROC definition process. ENDP process ends. SEGMENT definition SEGMENT. To build segment register addressing. ENDS of ENDS. END program ends. One. Mechanical code, also called machine code. Ultraedit opens, and you'll see it when editing the exe file Lots and lots of 0, 1, 2,3,4,5,6,7,8,9, A, B, C, D, E, F of digital, the digital That's the machine code. The exe file must be modified by modifying the machine code. 2. The total assembly knowledge needed to be mastered (only so many) It is not easy to understand, but first force back, to be familiar with, slowly understanding CMP a, b compares a to b Mov a, b gives a to b Ret returns to the main program Nop has no effect. The abbreviation of "no operation" means "do nothing" (machine code 90) * * * machine code (interpretation: ultraedit opens editing exe file when you see 90, equivalent to assembly statement nop) Call subroutine Je or jz if equal (machine code 74 or 0F84) Jne or JNZ jump if not equal (machine code 75 or 0F85) JMP unconditional jump (machine code EB) Jb will jump if it is less than that Ja if it's bigger than jump If jg is greater than jump Jge is greater than or equal to jump If jl is less than, jump Jle is less than or equal to jump Pop out of the stack Push pressure stack Iii. Common modification (machine code) 74 = 75 74 74 = 74 = > > > EB 75 = 74 75 75 = 75 = > > > EB JNZ - > the nop 75 - > 90 (corresponding machine code modification) JNZ - > JMP 75 - BBB 0 EB (corresponding machine code modification) JNZ - > jz 75 - > 74 (normal) 0F 85 - > 0F 84 (special case, sometimes corresponding machine code modification) Four. Two different ways of modifying the situation Change to JMP Jne (jne, jz, JNZ) = > JMP corresponding machine code EB (the first jump to be found in the error message) JMP's role is to jump unconditionally and skip the following error message XXXXXXXXXX error information, such as: incorrect registration code, sorry, unregistered version cannot... , "Function Not Avaible in Demo" or "Command Not Avaible" or "Can & # 39; t save in Shareware/Demo", etc. (we hope to skip it and Not let it appear) ... ... The correct route of XXXXXXXXXX 2. Modify to nop Je (developed, jz, JNZ) = > the nop corresponding machine code 90 (correct information to find the first jump up) the nop role is to erase the jump, make this jump is invalid, not work, so as to make the program to follow the correct infoshop smoothly XXXXXXXXXXXX correct information, such as: registered successfully, thank you for your support, etc. (we hope that it will not be skipped, let it appear, the program must be successfully brought here). ... ... The XXXXXXXXXXXXXXXX error message (we want to not jump here, not let it appear) they transfer data between the storage and the register, the register, and the input and output port. 1. General data transfer instructions. MOV transmission word or byte. The MOVSX first symbol expands, then transmits. MOVZX starts with zero extension and then transfers. PUSH the word into the stack. POP puts the word up on the stack. PUSHA puts AX, CX, DX, BX, SP, BP, SI, and DI on the stack. POPA pops up the stack of DI, SI, BP, SP, BX, DX, CX and AX. PUSHAD EAX, ECX, EDX and EBX, ESP, EBP, ESI, EDI in turn onto the stack. POPAD EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX pop-up stack in turn. BSWAP swap the order of bytes in 32-bit registers XCHG exchange word or byte. (at least one operation number is a register and the segment register is not operable.) CMPXCHG compares and exchanges operands. (the second operand must be the accumulator AL/AX/EAX) XADD is first switched and then accumulative. (results in the first operand) XLAT byte lookup table transformation. ? ? BX point to the starting point of a 256 - byte list, AL for the table index value (0-255, namely 0 - FFH); Return AL to check the result of the table. 2. Input and output port instructions. IN the I/O port input. (grammar: IN accumulator, {port ? DX}) OUT the I/O port output. (grammar: OUT ? DX} {port, the accumulator) When the input output port is specified in an immediate manner, its range is 0-255; When specified by register DX, The range is 0 minus 65535. 3. Destination address transfer instruction. LEA loads the valid address. Example: LEA DX, string; Save the offset address to DX. LDS passes the target pointer and loads the pointer content to DS. Example: LDS SI, string; Save the address: offset address to DS: SI. LES passes the target pointer and loads the pointer content into ES. Example: LES DI, string; Save the segment address: offset address to ESI. LFS passes the target pointer and loads the pointer content into FS. Example: LFS DI, string; Address: offset address to FSI. LGS passes the target pointer and loads the pointer content into GS. Example: LGS DI, string; Address: offset address to GSI. LSS passes the target pointer and loads the pointer contents into SS. Example: LSS DI, string; Save the segment address: offset address to SSI. Sign transfer instructions. LAHF flag register transmission, load the mark into AH. The SAHF flag register is transmitted and the AH content is loaded into the flag register. PUSHF marks the stack. POPF marks the stack. PUSHD 32 bit marks on the stack. POPD 32 bit marks out of the stack. Arithmetic operation instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? The ADD addition. ADC brings in addition. INC. ASCII adjustment of AAA addition. The decimal adjustment of DAA addition. SUB subtraction. SBB takes the borrowing and subtraction. DEC 1. NEC asks for the reverse. CMP comparison. (two operands to subtraction, only modify the mark bit, do not return the result). AAS subtraction of ASCII code adjustment. The decimal adjustment of DAS subtraction. MUL without symbol multiplication. IMUL integer multiplication. So these two things are going to return AH and AL (byte arithmetic), or DX and AX (word arithmetic), ASCII adjustment for AAM multiplication. DIV without symbol division. IDIV integer division. The above two results are sent back: The business returns the AL, the remainder returns AH, (byte arithmetic); Or the quotient back to AX, and the remainder to the DX, (word operation). The ASCII code adjustment of AAD division. The CBW bytes are translated into words. The CWD character is transformed into a double word. The CWDE is converted into two words. (the character number in AX is extended to EAX.) CDQ double word extension (to extend the symbol of the word in EAX to EDX) 3. Logical operation instructions ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? AND operations. OR OR operation. XOR x or x. NOT to take back. TEST TEST. (two operands and operations, only modify the mark bit, not return the result). SHL logic moves to the left. SAL arithmetic left. (= SHL) SHR logic moves to the right. (= SHR). The ROL circulates to the left. The ROR cycle moves to the right. RCL moves to the left through the carry cycle. The RCR moves to the right through the carry cycle. The above eight shift instructions can be shifted up to 255 times. When displaced, you can directly use the operation code, such as SHL AX, 1. When the shift > is 1 time, the shift number is given by the register CL. Such as MOV CL, 04 SHL AX, CL Iv. String instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DS: SI source string segment register: source crosstalk address. ESI target string segment register: target string change address. CX repetition times counter. AL/AX scan value. D mark 0 indicates that SI and DI should be incrementally changed in repetitive operation; 1 represents the automatic reduction. The Z flag is used to control the end of the scan or comparison operation. MOVS string transmission. (MOVSB transmits character. MOVSW transmits word. MOVSD delivers double word.) The CMPS comparison. (CMPSB comparison character. CMPSW comparison word.) SCAS string scan. Compare the content of AL or AX with the target string, and the comparison results are reflected in the mark bit. LODS load string. The elements in the source string (words or bytes) are loaded into AL or AX. (LODSB transfer character. LODSW transmits word. LODSD delivers double word.) STOS save the string. It's the inverse of LODS. REP when CX/ECX < > 0. REPE/REPZ when ZF = 1 or the result is equal, and CX/ECX < > 0 is repeated. REPNE/REPNZ when ZF = 0 or compare results are not equal, and CX/ECX < > 0 is repeated. REPC is repeated when CF = 1 and CX/ECX < > 0. REPNC is repeated when CF = 0 and CX/ECX < > 0. 5. Program transfer instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 > unconditional transfer instruction (long transfer) JMP transfer instructions unconditionally CALL procedure CALL RET/RETF process returns. 2 > conditional transfer instructions (short transfer, -128 to + 127) When and only if (SF XOR OF) = 1, OP1 < OP2) JA/JNBE is not less than or not equal to. JAE/JNB is greater than or equal to transfer. JB/JNAE is less than the transfer. JBE/JNA is less than or equal to transfer. The above four, test the result of unsigned integer arithmetic (mark C and Z). JG/JNLE is greater than the transfer. JGE/JNL is greater than or equal to transfer. JL/JNGE is less than the transfer. JLE/JNG is less than or equal to transfer. The above four, the test band symbol integer arithmetic result (sign S, O and Z). JE/JZ is equal to transfer. JNE/JNZ does not equal time transfer. JC is transferred when it is in. When JNC is not entered, it is transferred. When JNO does not overflow, transfer. The JNP/JPO parity is shifted when odd. The JNS symbol bit is moved when "0". JO overflow. The JP/JPE parity is transferred when the evenness is even. The JS symbol is moved when "1". 3 > loop control instruction (short shift) LOOP CX is not a zero cycle. LOOPE/LOOPZ CX is not zero and marks Z = 1. The LOOPNE/LOOPNZ CX is not zero and the Z = 0 cycle. JCXZ CX is a zero time shift. JECXZ ECX is transferred at zero time. 4 > interrupt instructions INT interrupt instruction INTO overflow interrupt IRET interrupt returns 5 > processor control instructions The HLT processor pauses until an interrupt or reset signal continues. WAIT when the chip lead TEST is high, the CPU enters the WAIT state. ESC to external processor. LOCK locks the bus. NOP empty operation. STC sets carry flag bit. CLC clear carry flag bit. The CMC carry flag is reversed. STD position marker. Clear direction of the CLD. The STI interrupt allows the bit. CLI clear interrupt allow bit. Vi. Pseudo-instruction ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DW definition word (2 bytes). PROC definition process. The ENDP process is over. SEGMENT definition SEGMENT. To establish a section register addressing. ENDS of ENDS. END program ends.