0.5 V ANALOG INTEGRATED CIRCUITS

0.5 V ANALOG INTEGRATED CIRCUITS Peter Kinget, Shouri Chatterjee, and Yannis Tsividis Columbia University New York, NY, USA Abstract Semiconductor technology scaling has enabled function density increases and cost reductions by orders of magnitudes, but for shrinking device sizes the operating voltages have to be reduced. As we move into the nanoscale semiconductor technologies, power supply voltages well below 1 V are projected. The design of MOS analog circuits operating from a power supply voltage of 0.5 V is discussed in this paper. The scaling of traditional circuit topolo- gies is not possible anymore and new circuit topologies and bias- ing strategies have to developed. Several design examples are pre- sented. The circuit implementations of gate and body-input 0.5 V operational transconductance amplifiers and their robust biasing are discussed. These building blocks are combined for the realiza- tion of active varactor-tuned RC filters operating from 0.5 V using standard devices with a |VT | of 0.5V in a standard 0.18 µm CMOS technology. 1 Introduction Analog circuits provide the connection of digital computing signal process- ing systems to the physical world. As such the true power of digital signal and information processing can only be exploited if analog interfaces with corre- sponding performance are available. Cost and size considerations push towards a co-integration of the analog interfaces and the digital computing/signal pro- cessing on a single die, thus in the same technology. The International Technology Roadmap for Semiconductors (ITRS) [1] gives us a unique opportunity to look into the projected future of semiconductor tech- nology and identify design challenges early (Fig. 1). The linewidth of CMOS 329 M. Steyaert et al. (eds), Analog Circuit Design, 329–350. © 2006 Springer. Printed in the Netherlands. 1000 500 250 130 90 65 45 32 22 Technology Node [nm] 1995 2000 2005 2010 2015 0 1 2 3 4 5 [V ] Digital Supply Voltage Analog Supply Voltage (thick oxide device) Threshold Voltage (a) 130 90 65 45 32 22 Technology Node [nm] 1995 2000 2005 2010 2015 0 5 10 15 20 25 30 [G Hz ] On−chip Clock Frequency (b) Figure 1: (a) Supply voltage and threshold voltage scaling and (b) on-chip clock frequency scaling according to [1] technologies is projected to keep scaling deeper into nanoscale dimensions for the next two decades so the functionality density, the intrinsic speed of the de- vices and thus the signal processing capability will keep increasing. However, in order to maintain reliability, to reduce power density and to avoid thermal problems, the maximum supply voltage has to be scaled down appropriately. Fig. 1 shows the projections for the supply voltage and on-chip clock frequen- cies. The supply voltage scaling is beneficial for digital circuits since it reduces the power consumption quadratically. To maintain good ON/OFF characteris- tics of the MOS transistors for digital logic the transistor’s threshold voltageVT cannot be reduced as aggressively because static leakage levels would become too large. A minimum standard VT of about 0.2 to 0.3 V is foreseen. By about the year 2013 at the 32 nm node a power supply voltage of 0.5 V is projected for high performance digital circuits. Also important to note is the fact that the scaling of the supply voltage for nanometer technologies is mainly driven by re- liability and breakdown concerns. Consequently any internal voltage boosting of the external low voltage may not be possible. These low power supply voltages and the relatively high device threshold voltages are a major obstacle for the realization and performance of analog cir- cuits. Smaller supply voltages result in smaller available signal swings. The reduction of circuit errors due to thermal noise or offset voltages often leads to higher power consumption [2–6]. In addition, devices used in high speed linear circuits need to be biased in moderate or strong inversion with a mini- mum voltage overdrive (VGS−VT) (approx. 0.15 to 0.2 V) resulting in a VDS,sat requirement of about 0.15 V. Typical analog building blocks require a supply voltage which is severalVDS,sat plus the signal swing, or aVT plus severalVDS,sat 330 plus the signal swing. At supply voltages below 1 V the design of analog cir- cuits becomes very challenging since the traditional circuit techniques run out of voltage headroom (see e.g., [5–10]). These challenges can be addressed with technology modifications or with circuit design solutions. A straightforward technology solution is to add thick oxide devices that are less aggressively scaled; these are slower but can operate with larger supply voltages (see Fig. 1(a)). They allow a resizing or sometimes even a reuse of I/O and analog building blocks. Another technology option is to include low VT [11] or native devices (zero VT). These offer some extra headroom in circuits [12], but low VT devices typically require an extra mask; native devices are typically less well characterized or modeled and sometimes have less reproducible characteristics. Extra semiconductor processing steps and masks result in extra cost and turn-around time. Since the analog interfaces typically occupy only 5 to 30% of the die area on large system-on-a-chip (SoC) circuits, the increased cost is hard to justify economically in large volume ap- plications. In the past decade we have witnessed significant design innovations to re- duce the supply voltage of analog circuits from 5 V to 3.3 V, to 2.5 V, and recently to 1.8 V and even 1.3 V. Clock voltage boosting [13,14], the switched- opamp circuit technique [15], back-gate driven circuits [16–18], rail-to-rail input stages [19, 20], multi-stage amplifiers with nested-Miller compensation [19, 21, 22], and level-shift techniques [23] are a few examples. Several am- plifiers operating at 1 V [18], [24], [25] and down to 0.9 V [26] have been demonstrated. Sub-1V analog-to-digital converters [27–30] have also been re- cently demonstrated. 2 Low voltage analog circuit design challenges and opportunities Operating a MOS device at low voltages For applications requiring high bandwidths or high clock and sampling rates, MOS devices are biased in the strong inversion region, i.e., (VGS−VT) ≥ 0.2 V [31]. The device acts as a voltage controlled current source or transconductor as long as VDS ≥ VDS,sat with VDS,sat = (VGS−VT)/α so that it operates in saturation. Typical values for α are between 1 and 1.5 and a good estimate for VDS,sat at the edge of strong inversion is about 0.15 V [31]. A MOS transistor can also be operated in its weak inversion region for (VGS−VT) ≤ -0.05 V or −0.1 V. This offers very high transconductance/current efficiencies and low power operation but the bandwidth is limited. The minimal VDS to maintain the device in saturation is now about 4kT/q to 5kT/q, or 0.1 to 0.125 V [31]. So, in any region of operation, we need to maintain a drain-source bias of about 0.15 V . It is im- 331 portant to remark that this requirement is independent of the threshold voltage VT of the device. On the other hand, the gate-source bias for the device VGS is VT +(VGS−VT) and is thus strongly dependent on theVT of the devices as well as the region of operation. Challenges at 0.5 V The most basic way to achieve amplification with aMOS transistor is the common source configuration with an active load1 as shown in Fig. 2. The required input (gate) bias isVT +(VGS−VT) and the optimal output (drain) bias is VDD/2 for an output swing of VDD−2VDS,sat. At 0.5 V VDD two limitations can occur: the output bias is typically smaller than the input bias2; and, the input swing is very limited. Clearly, it becomes very difficult to design circuits with large input and output swings. However, as long as a sufficiently large gain exists between input and output, this is not a strong limitation. With a 0.5 V supply, it is very difficult to use a common drain configuration (Fig. 2). The output can swing sufficiently but since there is no gain between the input and the output, the input bias and signal swing would require voltage levels above the supply. In a common gate configuration the input signal, output signal and 3VDS,sat are stacked; even if we assume a large voltage gain for the stage, the available output swing is too small for most applications. A common gate stage (or folded cascode) can be embedded in an amplifier if followed by sufficient gain so that no significant swings are needed at the common gate output. Similarly, cascode topologies with all devices in saturation3 are excluded at 0.5 V since they require a stack of the output swing and 4VDS,sat (about 0.6 V). Of the basic transistor configurations only the common source configuration has the potential to operate at supply voltages of 0.5 V. It is again important to remark that this limitation stems from the required VDS,sat of about 0.15 V and is independent of the value of VT . Feedback and virtual grounds The input and output bias level differences can be accommodated by using feedback topologies which keep the amplifiers inputs at virtual ground and allow for a level-shift between the output and the virtual ground notes as illustrated in Fig. 3 [5, 23]. Similar level shifts can be accommodated in switched capacitor circuits. 1We assume the active load is implemented with a single transistor biased as a current source. 2Only if VT is very small or negative, or if the (VGS−VT) is kept very small – which implies the device goes into weak inversion, – equal input and output bias can be achieved. 3To get the full benefit of a cascode topology we need to use cascode devices in the signal device and active load device, resulting in a stack of 4 devices. 332 VDS,sat VDS,sat VDS,sat VDS,sat VDS,sat VDS,sat VDS,sat (a) (b) (c) Vout,pp Vin,pp Vout,pp Vin,pp VT +(VGS−VT) Vout,pp Vin,p +VDS,sat VT +(VGS−VT)+ Vin,pp Vin,p +VDS,sat VT +(VGS−VT)+ Figure 2: Voltage ranges in (a) common source, (b) common drain, and (c) common gate configurations. VDD VDD Ipush Ipush Vcm,vg Vcm,i Vcm,o R1 R1 R2 R2 VDD VDD Vcm,vg Vcm,i Vcm,o R1 R1 R2 R2 Rb Rb Figure 3: The injection of DC currents into the virtual ground nodes allows a level shift between the virtual ground and amplifier outputs. As long as the loop gain is large, the signal swing at the virtual ground remains very small and large output swings can be achieved [5, 23]. 333 Opportunities at 0.5 V: the body terminal Operation from a small supply voltage (≤ 0.5V ) offers the advantage that the risk of turning on any of the par- asitic bipolar devices in the circuit is largely eliminated, provided that supply transient overvoltages are adequately kept under control. This enables the use of forward biasing for the body-source junction which results in a reduction of the threshold voltage VT [32–35]. Traditionally only the body terminal of pMOS devices could be accessed in n-well processes, but modern MOS pro- cesses offer the availability of nMOS devices in a separate well so that their body terminal can be biased independently. Forward body bias has been used in digital applications to tune the VT so that a more consistent circuit performance over process and temperature and thus a higher yield is obtained [32–34, 36]. Interestingly, a Low-Voltage- Swapped-Body-Bias (LVSB) design style has been proposed [37] where the body of the nMOS is tied to the positive supply and the body of the pMOS is tied to the negative supply. High speed or low power consumption is ob- tained and correct functionality for an operating temperature up to 75oC has been demonstrated [37]. As mentioned, forward body bias also allows to adjust and reduce the threshold voltage of the device. In [38,39] e.g., we typically use a forward bias of 0.25 V which results in a reduction of the VT by 50 mV for a standard device in a 0.18 µm CMOS technology. The availability of the body terminal thus offers two opportunities. The signal can be applied to the body (back-gate) of the device [16–18,38] whereas the gate is used to bias the device; or, when we apply the signal to the gate, we can use the body (back-gate) to control the bias of the device [39]. Both techniques will be illustrated in the subsequent sections. Bipolar devices The built-in potential of silicon PN junction is about 0.7 V which excludes bipolar devices for true low voltage circuits at 0.5 V. 3 Fully Differential Operational Transconductance Amplifiers Fully differential circuits [40, 41] are standard in contemporary analog in- tegrated circuits due to their large signal swing and better supply and substrate interference robustness. At 0.5 V, we have to rely on those properties even more and fully differential topologies are a must. It is important to point out that the correct operation of differential topologies relies on the availability of good common-mode rejection; not only needs the differential-mode gain to be significantly larger than the common-mode gain, but also the common-mode 334 Vout− Vin+Vin− VBn VBp VBn VBp Vout+ VB VB Vout+ CMFB Figure 4: Folded cascode operational transconductance amplifier VT +(VGS−VT)+ VDS,sat VDS,sat Vin,se,ppVin,se,pp VT +(VGS−VT)+ VDS,sat Vout,se,pp VDS,sat VDS,sat VDS,satVDS,sat Figure 5: Bias and signal ranges in a differential pair. gain needs to be sufficiently smaller than 1 in the presence of positive feedback loops in the common-mode signal path. Two stage, folded cascode transconductance amplifiers, shown in Fig. 4, are often used for low voltage applications (see e.g., [6, 23, 42]). The differential pair is the standard input structure for an operational (transconductance) ampli- fier. For a differential input signal, the differential signal current is proportional to the gm of the input pair; for a common-mode input signal, the common-mode output current is determined by the conductance of the tail current source and is thus very small; the small response to common-mode signals in combination with a wide-band common-mode feedback (CMFB) provide a small common- mode gain and strong common-mode rejection [40, 41]. The signal ranges and biasing in a differential pair are illustrated in Fig. 5. 335 Due to the stacking of three devices, its output swing is very limited; how- ever, by adding a second gain stage after the input stage this limitation can be overcome as shown in Fig. 4. The main challenge is the required input bias of VT +(VGS−VT) +VDS,sat; supposing the inputs can be biased at 0.5 V, the resulting maximum allowed VT is only 0.15 V for strong inversion operation. Even when such a low VT is available, in practice the inputs of the OTA will need to be about 0.15 V below the supply – see, e.g., Fig. 3 – so that strong inversion operation of this stage becomes impractical with a 0.5 V supply. So, for any technology where VT is larger than 0.15 V there is a need to develop differential input structures with good common-mode rejection. The design of wide-band common-mode feedback loops is also very chal- lenging at 0.5 V. The output common-mode is set at 0.25 V (VDD/2) for max- imum swing so that it is very difficult to develop a wide-band error amplifier. We will discuss local common-mode feedback as an alternative solution in sub- sequent sections. Telescopic amplifiers [40,41] are also widely used for analog integrated cir- cuits thanks to their relative simplicity and intrinsic high operation speed. High gain is achieved in these configurations by using (folded) cascode topologies and is further enhanced with gain boosting. None of these topologies can be easily used at 0.5 V due to required device stacks and limited output swing. At 0.5 V we have to rely on multi-stage topologies to achieve sufficient gain. Due to the unavailability of the common drain stage the realization of a low output impedance required for the implementation of an operational amplifier also becomes very difficult and we are limited to operational transconductance amplifiers. For most on-chip applications the loads are capacitive or the load impedances can be kept sufficiently large that this is not a very significant limi- tation, especially in feedback circuits where the loop gain reduces the effective output impedance. In the subsequent paragraphs two OTA designs will be introduced that can operate from a 0.5 V supply. We will also briefly discuss the application of such OTAs in a larger analog signal processing function. 3.1 Body-input OTA Single-ended body-input operational amplifiers have been investigated for low voltage applications down to 0.7 V [16], [18], [24], [25], [26]. At supply voltages of 0.5 V or below, there is low risk for latchup in the circuit (assuming that supply transient overvoltages are limited) and the signals can be connected to the body node of the MOS devices without restrictions. For an input common mode at VDD/2 (0.25 V), a small forward bias for the body-source junction is also introduced; this lowers the VT and further increases the inversion level. Operation near the weak-moderate inversion boundary is preferred, in order to 336 +Vin -Vin Vout- Vout+ biasi biasn Vdd RA RB M4 M1A M1B M2A M2B M3A M3B Figure 6: Fully differential gain stage with local common-mode feedback attain a relatively large gmb. A very low voltage basic body-input stage is shown in Fig. 6 [38]. The two inputs are at the bodies of pMOS transistors M1A and M1B and the gmb of these devices provides the input transconductance. These devices are loaded by the nMOS transistors M2A and M2B which act as current sources. Transistors M1A and M1B are a pseudo-differential pair and do not provide any common-mode rejection. Therefore, local common-mode feedback is used. Resistors RA and RB detect the stage’s output common-mode voltage which is fed back to the gates of the pMOS devices M1A, M1B, M3A and M3B for common-mode rejection. A DC level shift between the output common- mode voltage at 0.25 V and the gate bias at 0.1 V is created by pulling a small current through RA and RB with M4. To further improve the differential gain devices M3A and M3B are added; the body-inputs of M3A and M3B are a cross coupled pair that adds a negative resistance to the output and boosts the differential DC gain; the gate inputs are used to further decrease the common- mode gain. In the following gmbN is the body transconductance, gmN is the gate transcon- ductance, and gdsN is the output conductance, of device MN. The differential DC gain is: Adiff = gmb1 gds1 +gds3 +gds2 +1/RA,B−gmb3 (1) The common-mode DC gain is given by: Acm =− gmb1gds1 +gds3 +gds2 +gmb3 +gm1 +gm3 (2) Note that Adiff is of the order of gmb/gds and is thus large, whereas Acm is of the order of gmb/gm and thus intrinsically smaller than 1. M3A and M3B are sized conservatively so that gmb3 cancels out 60% of gds1 + gds3 + gds2 + 1/R. This gives us a gain boost of 8 dB. 337 +Vin -Vin biasi biasn Vdd RA RB M4 M1A M1B M2A M2B M3A M3B Vout- Vout+ RC RCCCCC M2 M4 RA’ RB’ M1A’ M2A’ M3A’ M4’ M1B’ M2B’ M3B’ Figure 7: Two-stage fully differential body-input OTA with Miller compensation In [38] an implementation of this input stage in a 0.18 µm CMOS process is presented. Standard devices with a |VT | of about 0.5 V were used. A differential gain Adiff of 25 dB and a common-mode gain Acm of −11 dB is obtained for this stage resulting in a common-mode rejection of 36 dB. An important advantage of the local feedback is the rejection of common mode signals up to high frequencies without the need for a fast error amplifier. To obtain adequate gain, identical gain blocks can be cascaded so that a two stage OTA is obtained as shown in Fig. 7. The amplifier is stabilized by adding Miller compensation capacitors CC with series resistors for right half- plane zero cancellation [40, 41]. The frequency response has a gain-bandwidth product approx