dsp2812 官网参考设计 XINTF

TMS320x281x DSP External Interface (XINTF) Reference Guide Literature Number: SPRU067C May 2002 Revised November 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. 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Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright  2004, Texas Instruments Incorporated Contents 5 �������� 1 Functional Description 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Accessing XINTF Zones 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Write-Followed-by-Read Pipeline Protection 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 XINTF Configuration Overview 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Procedure to Change the XINTF Configuration and Timing Registers 15. . . . . . . . . . . . . . . 2.2 XINTF Clocking 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Write Buffer 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 XINTF Access Lead/Active/Trail Wait-State Timing Per Zone 18. . . . . . . . . . . . . . . . . . . . . . 2.5 XREADY Sampling For Each Zone 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Bank Switching 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Effects of the XMP/MC Signal on the XINTF 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Configuring Lead, Active, and Trail Wait States 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 XINTF Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 XINTF Timing Registers 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 XINTF Configuration Register 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 XBANK Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 XREVISION Register 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Signal Descriptions 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Waveforms 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 External DMA Support (XHOLD, XHOLDA) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Revision History A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.1 Changes Made in This Revision A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures 6 �� ��� 1. External Interface Block Diagram 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Zone 0/Zone 1 Chip-Enable Logic 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3. Zone 7 Memory Map 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4. Access Flow Diagram 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. Relationship Between XTIMCLK and SYSCLKOUT 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. XTIMING0/1/2/6/7 Register Layout 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7. XINTCNF2 Register 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8. XBANK Register 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9. XREVISION Register Layout 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10. XTIMCLK and XCLKOUT Mode Waveforms 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11. Generic Read Cycle (XTIMCLK = SYSCLKOUT mode) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12. Generic Read Cycle (XTIMCLK = 1/2 SYSCLKOUT mode) 41. . . . . . . . . . . . . . . . . . . . . . . . . 13. Generic Write Cycle (XTIMCLK = SYSCLKOUT mode) 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tables 7 � ���� 1. Pulse Duration in Terms of XTIMCLK Cycles 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Relationship Between Lead/Trail Values and the XTIMCLK/X2TIMING Modes 23. . . . . . . . . 3. Relationship Between Active Values and the XTIMCLK/X2TIMING Modes 24. . . . . . . . . . . . 4. XINTF Configuration and Control Register Mapping 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5. XINTF Signal Descriptions 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 This page is intentionally left blank. 9 ������� �������� ����������� The external interface (XINTF) is a nonmultiplexed asynchronous bus, similar to the C240x external interface. This reference guide is applicable for the XINTF found on the TMS320x281x family of processors. This includes all Flash-based, ROM-based, and RAM- based devices within the 281x family. 1 Functional Description The XINTF on the 2812 is mapped into five fixed memory-mapped zones as defined in Figure 1. Each of the 28x XINTF zones has a chip-select signal that is toggled when an access is made to that particular zone. On some devices the chip-select sig- nals for two zones may be internally ANDed together to form a single shared chip select. In this manner, the same memory is connected to both zones or external decode logic can be used to separate the two. Each of the five zones can also be programmed with a specified number of wait states, strobe signal set-up and hold timing. The number of wait states, set-up and hold timing is separately specified for a read access and a write access. In addition, each zone can be programmed for extending wait states externally using the XREADY signal or not. The programmable wait-state, chip-select and programmable strobe timing enables glueless interface to external memo- ries and peripherals. You specify the set-up/hold and access wait states for each XINTF zone by configuring the associated XTIMINGx registers. The access timing is based on an internal clock called XTIMCLK. XTIMCLK can be set to the same rate as the SYSCLKOUT or to one-half of SYSCLKOUT. The rate of XTIMCLK ap- plies to all of the XINTF zones. XINTF bus cycles begin on the rising edge of XCLKOUT and all timings and events are generated with respect to the rising edge of XTIMCLK. Functional Description External Interface (XINTF)10 SPRU067C Figure 1. External Interface Block Diagram (See Note A) XD(15:0) XA(18:0) XZCS0 XZCS6 XZCS7 XZCS1 XZCS2 XWE XRNW XREADY XMP/MC XHOLD XHOLDA XCLKOUT (see Note D) XRD XINTF Zone 0 (8K × 16) XINTF Zone 1 (8K × 16) (See Note B) XINTF Zone 6 (512K × 16) XINTF Zone 7 (16K × 16) ( mapped here if MP/MC =1) See Note C 0x0040−0000 0x003F−C000 0x0020−0000 0x0010−0000 0x0000−6000 0x0000−4000 0x0000−2000 0x0000−0000 Data Space Prog Space XINTF Zone 2 (512K × 16) 0x0008−0000 NOTES: A. Each zone can be programmed with different wait states, setup and hold timings, and is supported by zone chip selects (XZCS0AND1, XZCS2, XZCS6AND7), that toggle when an access to a particular zone is performed. These features enable glueless connection to many external memories and peripherals. B. Zones 3 − 5 are reserved for future expansion. C. The mapping of XINTF Zone 7 is dependent on the XMP/MC device input signal and the MP/MC mode bit (bit 8 of XINTCNF2 register). Zones 0, 1, 2, and 6 are always enabled. D. XCLKOUT is also pinned out on the devices without the rest of the XINTF. Functional Description 11 External Interface (XINTF)SPRU067C 1.1 Accessing XINTF Zones As shown in Figure 1, an XINTF zone is a region in the 28x memory map that is directly connected to the external interface. Memory or peripheral registers within each of these zones can be accessed directly with the 28x CPU or Code Composer Studio. Each XINTF zone can be individually configured with unique read and write access timing and each has an associated zone chip-select signal. This chip- select signal is pulled low so that an access to that zone is currently taking place. On the 2812 devices, some zone chip-select signals are shared between zones. Zone 0 and Zone 1 share XZCS0AND1 and Zone 6 and Zone 7 share XZCS6AND7. The external address bus, XA, on the 281x is 19 bits wide and is shared by all of the zones. What external addresses are generated depends on which zones are being accessed, as follow: � Zone 2 and Zone 6 Zone 2 and Zone 6 share identical external addresses. The external ad- dress bus is 0x00000 when the CPU accesses the first location in either Zone 2 or Zone 6. Likewise, XA is 0x7FFFF when the CPU accesses the last location of Zone 2 or Zone 6. The only difference between accesses to these two zones is which zone chip-select signal goes low: XZCS2 or XZCS6AND7. Since Zone 2 and Zone 6 use distinct chip-select signals, these two zones can be easily used to access memories with different timing requirements. In this case, you can use just the chip-select signal to distinguish between an access to Zone 2 and Zone 6 and additional address decoding is not required. � Zone 0 and Zone 1 Zone 0 and Zone 1 share the same chip-select signal, but use distinct ex- ternal addresses. Zone 0 uses XA addresses 0x2000h - 0x3FFF and Zone 1 uses XA addresses of 0x4000 - 0x5FFF. In this case, additional logic can be used, if required, to distinguish between an access to Zone 0 and one to Zone 1. XA[13] is high for all Zone 0 accesses and low for all Zone 1 accesses. Likewise, XA[14] is low for all Zone 0 accesses and high for all Zone 1 accesses. Using this information, the logic in Figure 2 can be used to generate separate chip enable signals for memory or peripherals attached to Zone 0 and Zone 1. Functional Description External Interface (XINTF)12 SPRU067C Figure 2. Zone 0/Zone 1 Chip-Enable Logic XA[13] XA[14] XZCS0AND1 Chip enable (CE) for zone 0 Zone 0 chip enable logic Zone 1 chip enable logic XA[14] XA[13] XZCS0AND1 for zone 1 Chip enable (CE) Accesses to Zone 1 are also affected by an additional feature called the write-followed-by-read pipeline protection. This feature, which is detailed in section 1.2, makes Zone 1 especially well suited for attaching external peripheral devices instead of external memory. � Zone 7 Zone 7 is a unique zone. This XINTF zone is only memory mapped at 0x3FC000 when the XMP/MC input signal is pulled high at reset. Software can enable or disable the mapping of this zone after reset by modifying the MP/MC mode bit in the XINTCNF2 register. When Zone 7 is not mapped, the internal boot ROM is mapped in its place. Zone 7 is the only XINTF zone that is dependent on MP/MC. Zones 0, 1, 2, and 6 are always memory mapped. Zone 7 is typically used to boot from external memory where a customer has created their own custom boot routines and stored them in the memory attached to Zone 7. After booting, the software may enable the internal boot ROM in order to access the math tables included in the ROM. With the boot ROM mapped in place of Zone 7, the contents of the memory attached to Zone 7 can still be accessed from within Zone 6. This is be- cause the Zone 6 and Zone 7 share the same chip-select signal XCZS6AND7 and accesses to Zone 7 use external address values 0x7C000 - 0x7FFFF that are also used by Zone 6. This has the effect of mirroring Zone 7 within the lower 16K portion of Zone 6 as shown in Figure 3. Functional Description 13 External Interface (XINTF)SPRU067C Figure 3. Zone 7 Memory Map 0x10 0000 0x17 C000 0x17 FFFF CPU address Zone 6 Zone 7 mirror Zone 7 0x3F C000 0x3F FFFF CPU address 1.2 Write-Followed-by-Read Pipeline Protection In the 28x CPU pipeline, the read phase of an operation occurs before the write phase. Due to this ordering, a write followed by a read access can actually oc- cur in the opposite order: read followed by write. For example, the following lines of code perform a write to one location fol- lowed by a read from another. Due to the 28x CPU pipeline, the read operation will be issued before the write as shown: MOV TBIT @REG1,AL @REG2,#BIT_X Read Write On 28x devices, regions of memory where peripheral registers are common are protected from this order reversal by hardware. These regions of memory are said to be read-followed-by-write pipeline protected. On the 2812 devices, XINTF Zone 1 is by default read-followed-by-write pipeline protected. Write and read accesses to Zone 1 get executed in the same order they are written. For example, a write followed by a read is executed in the same order it was written as shown below: MOV TBIT @REG1,AL @REG2,#BIT_X Read Write The 28x CPU automatically protects writes followed by reads to the same memory location. The protection mechanism described above is for cases where the address is not the same, but within a given region of protected memory. In this case, the order of execution is preserved by the CPU Functional Description External Interface (XINTF)14 SPRU067C automatically inserting enough NOP cycles for the write to complete before the read occurs. This execution ordering becomes a concern only when peripherals are mapped to the XINTF. A write to one register may update status bits in another register. In this case, the write to the first register needs to be complete before the read to the second register takes place. If the write and read operations are performed in the natural pipeline order, the wrong status may be read since the write would happen after the read. This reversal is not a concern when memory is mapped to the XINTF. XINTF Zone 1 includes the write-followed-by-read protection by default and the CPU automatically adds required cycles between writes followed by reads. Thus, Zone 1 would typically not be used to access memory but instead would be used only to access external peripherals. If other zones other then Zone 1 are used to access peripherals that require the order write-followed-by-read instructions to be preserved, the following solutions can be used: � Add up to 3 NOP assembly instructions between a write and read instruc- tions. Fewer then 3 can be used if the code is analyzed and it is found that the pipeline stalls for other reasons. � Move other instructions before the read to make sure that the write and read are at least three CPU cycles apart. � Use the -mv compiler option to automatically insert NOP assembly instruc- tions between write and read accesses. This option should be used with caution because this out-of-order execution is a concern only when ac- cessing peripherals mapped to XINTF and not normal memory accesses. XINTF Configuration Overview 15 External Interface (XINTF)SPRU067C 2 XINTF Configuration Overview The following gives an overview of the various XINTF parameters that can be configured to fit particular system requirements. The exact configuration used depends on the operating frequency of the 28x device, switching characteris- tics of the XINTF, and the timing requirements of the external devices to which it is being interfaced. Detailed information on each of these parameters is giv- en in the following sections. Because a change to many of the XINTF configuration parameters will cause a change to the access timing, code that configures these parameters should not execute from the XINTF itself. 2.1 Procedure to Change the XINTF Configuration and Timing Registers During an XINTF configuration or timing change, no accesses to the XINTF can be in progress. This includes instructions still in the CPU pipeline, write accesses in the XINTF write buffer, data reads or writes, and instruction pre-fetch operations. To be sure that no acc