LLC 原理

©� Semiconductor Components Industries, LLC, 2008 January, 2008 - Rev. 0 1 Publication Order Number: AND8311/D AND8311/D Understanding the LLC Structure in Resonant Applications Prepared By: Christophe Basso ON Semiconductor The resonant LLC topology, member of the Series Resonant Converters (SRC) begins to be widely used in consumer applications such as LCD TVs or plasma display panels. In these applications, a high level of safety and reliability is required to avoid catastrophic failures once products are shipped and operated in the consumer field. To face these new challenges, ON Semiconductor has recently released to new controllers, the NCP1395 (low-voltage) and the NCP1396 (high-voltage) dedicated to driving resonant power supplies, usually of LLC type. However, before rushing to design a converter of this type, it is important to understand the resonant structure alone, object of the present application note. The LLC converter The LLC converter implies the series association of two inductors (LL) and one capacitor (C). Figure 1 shows a simplified representation of the resonant circuit where: Ls is the series inductor Lm is the magnetizing inductor Cs represents the series capacitor 0 ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ 0 ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ ÏÏÏÏÏÏÏÏÏÏ Figure 1. The LLC Topology Uses a Half-Bridge Configuration to Drive the Resonant Circuit Vbulk CS D1 D2 Cout + Rload Lm Vbulk QA QB HB N:1 Vout http://onsemi.com AND8311/D http://onsemi.com 2 The operating principle is rather simple: a constant 50% duty-cycle switching pattern drives QA - QB gates and a high-voltage square wave appears on node HB. By adjusting the switching frequency, the controller can control the power flow depending on the output demand. As a transformer is needed for isolation purposes, its magnetizing inductance plays the role of the second inductor Lm. The series inductor, Ls, can either be a separated element or physically lump into the transformer. In this case, a voluntary degradation of both primary and secondary coupling naturally increases the leakage inductance which can act as the series element. There are pros and cons to include the leakage element in the transformer. The cost and the absence of saturation play in favor of the integration but the difficulty to keep a precise value from lots to lots associated with leaky transformers (radiated noise) has to be kept in mind when selecting the final configuration. When studying the resonant converter, it is convenient to reduce the architecture to a passive element arrangement such as presented on Figure 2. The high-voltage square signal is replaced by its fundamental content thanks to the first harmonic approximation (the so-called FHA in the literature): because we operate a tuned LC filter, all harmonics can be considered as rejected and only the fundamental passes through. Of course, this statement holds as long the controller drives the resonating work in the vicinity of its resonant frequency. Figure 2 offers such a simplified representation of the resonant cell, actually pointing out a series impedance (Ls and Cs) with a parallel impedance (Lm and the reflected load). Figure 2. The Impedance Representation Makes the LCC Operation Easier to Understand Depending on the loading, the network resonant frequency varies between two different values: • RL = 0, short-circuit, Lm disappears and Zseries becomes a short. The series resonant point for Zseries is thus Fmax � FS � 1 2� LSCS� (eq. 1) At Fsw = FS, Zseries becomes a short and the ac transfer function drops to 1 or 0 dB. • RL = ∞, light or no load condition, Lm appears in series with Ls and the whole network resonates to Fmin � 1 2� �LS � Lm�CS� (eq. 2) • 0 < RL < ∞, the resonance which combines Lm and Ls, shifts depending on the total quality coefficient. AND8311/D http://onsemi.com 3 10k 20k 50k 200k -24.0 -12.0 0 12.0 24.0 FREQUENCY (Hz) Figure 3. The AC Response of Figure 2 Circuit with Various Load Conditions Pout = 10 W, Q = 60 Pout = 50 W, Q = 13 Pout = 100 W, Q = 6.7 Pout = 200 W, Q = 3 Lm = 600 �H LS = 100 �H Vout = 24 V CS = 33 nF N = 8 Pout = 300 W, Q = 2 20log10 Vout(s) Vin(s) � dB Fmin � 1 2� LS� Lm)CS� Fmax � FS 1 2� LSCS� This is actually what Figure 3 plots suggest by showing the ac transfer function of Figure 2 as the load changes. If we now study the impedance seen from the half-bridge node, we have an expression showing a series association of inductors and a capacitor. Sticking to Figure 2 sketch and writing the impedance seen between ground and Node 3, we have: Zin � ZLS � ZCS � ZLin �Rac (eq. 3) Zin �� (�Lm)4Rac�2 �Rac�2 � �2Lm�2� 2 ���LS 1 �CS � �Lm Rac�2 Rac�2� ��2Lm�2 � 2 2 (eq. 4) In the low frequency portion, the terms associated with inductors are of less importance and Cs dominates. The impedance is thus capacitive. As the frequency increases, the inductive portion starts to kick-in and the impedance goes up. This is what Figure 4 describes. As one can see, all the curves go through point A whose value is independent from the resistive loading. For the sake of a friendly exercise, we can solve Equation 4 with two different Rac values and find the frequency at which input impedances equal. We obtain: �A � 2 LmCS � 2LSCS � (eq. 5) If we substitute this value into Equation 4, the impedance at point A is: ZA � Lm 2LS LS�S Lm 2LS � 1� (eq. 6) If we define the ratio R by Lm/Ls, we can re-arrange equation 6: ZA � R 2(R � 2)� LS CS � � R 2(R � 2)� ZO (eq. 7) Where Z0 represents the characteristic impedance of the series resonant network. Using the numerical values noted in the graphs, we obtain a frequency of 43.8 kHz and an impedance of 38.3 dB� (82.6 �). AND8311/D http://onsemi.com 4 10k 20k 50k 200k 14.0 26.0 38.0 50.0 62.0 43215 A 43215 A Figure 4. Impedance Plots at Various Power Levels Pout = 10 W, Q = 60 Pout = 50 W, Q = 13 Pout = 100 W, Q = 6.7 Pout = 200 W, Q = 3 Lm = 600 �H LS = 100 �H Vout = 24 V CS = 33 nF N = 8 Pout = 300 W, Q = 2 dB� Capacitive Region Inductive Region FREQUENCY (Hz) Fmin 1 2� LS� Lin)CS� If we now observe the resonant current waveforms in a LLC converter working below or above the series resonance Fs, we have different types of operation: • Capacitive mode: in this mode, where the current leads the voltage, the bridge MOSFETs operate in zero current switching (ZCS). ZCS means that power MOSFETs are turned-off at zero current. Back to figure 3, we can see that the output level goes up as the frequency increases. • Inductive mode: in this mode, the current lags the voltage and the power switches are turned-on at zero volt (ZVS), virtually eliminating all capacitive losses. This operating way implies that a certain delay exists before operating the concerned MOSFET so that its body diode turns on first. Observing figure 3, the output level goes down as the frequency increases. Most of the LLC converters operate in the inductive region for the second bullet reason. Also, given the feedback polarity, if by mistake the closed-loop LLC enters the left side of the resonance, the control law reverses and a power runaway obviously occurs. It is thus extremely important to clamp down the lower frequency excursion in fault condition or during the startup sequence to avoid falling on the other slope of the characteristics. The inductive region can be split into two other regions, depending where you operate compared to the resonant series frequency Fs, as defined by Equation 1. Figure 5 represents the classical set of curves often found in the dedicated literature: AND8311/D http://onsemi.com 5 200m 600m 1.00 1.40 1.80 0 1.00 2.00 3.00 4.00 12 3 4 5 Q = 10 Q = 1 Q = 0.5 Region 1 Region 2 Region 3 F sw = F s F sw > F sF sw < F s 12 3 4 5 Region 1 Region 2 Region 3 F sw = F s F sw > F sF sw < F s Figure 5. Typical Transmittance Curves with Various Loading Conditions, Highlighting Three Distinct Regions Vf/FS (V) Q = 5 Q = 2 Region 3 is the capacitive mode where you do not want to operate since ZVS is a wanted feature for the power switches. In regions 1 and 2, you still have ZVS on the power MOSFET's and the output diodes are operated in Zero Current Switching (ZCS), cancelling all associated losses at turn-off. Before discussing the benefits of a particular solution, let us have a look at the various operating phases the LLC converter is made of. Operating Waveforms Below the Series Resonance, Fsw < Fs For this example, we have selected a set of elements which operate the converter below the series resonance defined by Equation 1. The following value have been used: Lm = 700 �H Ls = 116 �H Cs = 28 nF N = 8 Fmax � FS � 1 2� LSCS� � 1 6.28 � 116�� 28n� � 88.3�kHz Fmin � 1 2� (LS � Lm)CS� � 1 6.28� (116�� 700�) � 28n� � 33�kHz Fsw = 70 kHz at full load and nominal input voltage. The converter delivers 24 V@10 A from a 380 Vdc input source and a simulation has been performed using the above values. Figure 6 shows the main waveforms obtained from the simulator. Let us study the switching events step by step to learn about the LLC behavior in this region. AND8311/D http://onsemi.com 6 -2.00 2.00 6.00 10.0 14.0 vg sl, vg su in v ol ts pl ot 1 22 23 0 100 200 300 400 vb rid ge in v ol ts -4.00 -2.00 0 2.00 4.00 ils ,i lm ag in a m pe re s pl ot 2 25 26 24 478u 482u 486u 490u 494u time in seconds -10.0 0 10.0 20.0 30.0 id (d3 a), id io de in a m pe re s pl ot 3 27 28 V GS,upperV GS,lower I mag I L I d2 Diode current Gate voltages Resonant currents I L = I mag I d,peak I out DT Q B is on Q A is off Q B is off Q A is on I d1 V HB -2.00 2.00 6.00 10.0 14.0 vg sl, vg su in v ol ts pl ot 1 22 23 0 100 200 300 400 vb rid ge in v ol ts -4.00 -2.00 0 2.00 4.00 ils ,i lm ag in a m pe re s pl ot 2 25 26 24 478u 482u 486u 490u 494u time in seconds -10.0 0 10.0 20.0 30.0 id (d3 a), id io de in a m pe re s pl ot 3 27 28 V GS,upperV GS,lower I mag I L I d2 Diode current Gate voltages Resonant currents I L = I mag I d,peak I out DT Q B is on Q A is off Q B is off Q A is on I d1 V HB Figure 6. Waveforms Obtained for a Converter Operated Below the Series Resonant Frequency QA is off, QB is on, D2 is conducting : The low-side MOSFET QB imposes a 0 V potential on the half-bridge node and the current circulates from its drain to source (first quadrant). The upper parasitic capacitor CossA is fully charged to the input voltage Vbulk since the HB node is grounded by QB. The secondary diode D2 is conducting and imposes a voltage reflection -NVout over the magnetizing inductor Lm. Its current linearly decreases with a slope of -NVout/Lin. As this inductor is dynamically shorted by the voltage reflection, it does not participate to the on-going resonance between Ls and Cs which deliver the output energy (the input source is out of the picture). The current flowing into the transformer primary side (given its theoretical representation, Lm associated to a perfect transformer) is the main current IL minus the magnetizing current Imag. D1 is blocked and undergoes twice the output voltage given the transformer coupling. The circuit resonates to Fs as Lm is shorted. Figure 7 depicts the situation during this period of time. QA is off, QB is on, D2 turns off: As the network current IL resonates in a sinusoidal manner, its amplitude peaks and then starts to dip towards 0. When it reaches a level equal to that of the magnetizing current, no current circulates in the transformer anymore: D2 blocks and the voltage reflection over Lm disappears. The magnetizing inductor now comes back in series with Ls and Cs and changes the resonant frequency from Fs to Fmin: the LLC converter is really a multi-resonant structure and the plateau - actually a small arch of a lower sinewave oscillation - in the current as it appears on figure 6 testifies for it. Both diodes are now blocked and this moment lasts until QB opens. Figure 8 represents the circuit during this time. As one can see, the output capacitor alone supplies the energy to the load. AND8311/D http://onsemi.com 7 Figure 7. QA is Off, QB is On and Diode D2 Conducts Current. Lm is Off the Picture as it is Dynamically Shorted by the Output Voltage Reflection. Figure 8. QA is Off, QB is On and Diode D2 Blocked. Lm Comes Back Again in the Resonating Network and Changes the Resonant Frequency to Fmin. Vbulk D1 + N:1 VoutIout VoutVLm Iout IL-Imag IL-Imag Lm Iout D2 CS CossA VbulkQA QB IL IL LS Vout Vbulk D1 + N:1 Vout VLm IL-Imag IL-Imag Lm D2 CS CossAQA QB IL IL LS Imag Imag IL Imag Imag IL IL QA is off, QB is Off, Both Secondary Diodes are Blocked Both transistors are now open, this is the dead-time period (DT on Figure 6). The dead-time is placed here to avoid cross-conduction between both MOSFETs but also to favor Zero Voltage Switching as we will see in a moment. Because the current was circulating from drain to source in QB, the circuit no longer sees an ohmic path when this transistor opens. The current strives to find a way through the parasitic drain-source capacitors Coss of both QA and QB: CossB starts to charge (it was previously discharged by QB being on) and given the rise of VHB towards the high voltage rail, CossA sees its terminals voltage going down to zero and then reversing (Figure 9). At this moment, when the HB node reaches Vbulk + Vf, the body-diode of QA conducts and ensures energy re-cycling through the input source (Figure 10). You understand that this dead-time period must last a time long enough to allow for the complete discharge of CossA before re-activating QA so that its body-diode turns on first. If not, hard switching occurs and efficiency suffers. As currents are oscillating, a time is reached where IL and Imag are no longer equal (end of the plateau) and a current circulates again in the primary side. D1 starts to conduct and NVout appears across Lm :the resonant frequency goes back from Fs to Fmin. Figure 10 describes this moment. Figure 9. QA is Off, QB is Off. The Current Finds a Circulating Path Through Both Transistors Coss, Both Secondary-Side Diodes are Off. Figure 10. QA and QB are Still Off. The Current Finds a Circulating Path through the Upper-side Body Diode. D1 Starts Conducting at the End of the Plateau when IL � Imag. Vbulk D1 + N:1 VoutIout VLm IL-Imag Lm D2 CS CossA The Voltage is Falling QA IL IL LS Imag Imag CossBQB The Voltage is Rising Vbulk D1 + N:1 Vout VLm Lm D2 CS IL IL LS Imag Imag CossBQB Reaches (Vin + Vf) when QA Body-Diode Conducts The Voltage is Rising QA Vf QA is on, QB is off, D1 is on Now that QA body-diode is conducting, we have a negligible voltage across its drain and source terminals: we can therefore safely turn it on and benefit from Zero Voltage Conditions. As we have a sinusoidal waveform in the network, the resonating current reaches zero and reverses. AND8311/D http://onsemi.com 8 Lm is still dynamically shorted as D1 is conducting. The energy is delivered by the source to the output load. This is illustrated by Figure 11. QA is on, QB is off, D1 turns off The current IL is moving down and reaches the magnetizing current level, we are the second plateau on Figure 6. At this point, no current circulates in the transformer and D1 naturally blocks. As explained before, the magnetizing inductor re-appears in the circuit since the output voltage reflection is gone. The resonant frequency changes from Fmin to Fs and the energy to the load is delivered by the output capacitor alone. Figure 12 shows the circuit state during this event. Figure 11. The Current is Now Flowing from the Source to the Output Via the Upper-Side Transistor QA. Figure 12. As Both Diodes are Off, the Network Includes the Magnetizing Inductance which Changes the Resonant Frequency. Vbulk D1 + N:1 Vout VLm IL-Imag Lm D2 CS QA IL IL LS Imag Imag CossBQB Vout Vout + IL-Imag Vbulk + N:1 Vout VLm Lm CS QA IL IL LS Imag Imag CossBQB + QA is of, QB is off, both secondary diodes are blocked At a certain time, both transistors block and only their drain-source capacitors remain in the circuit. The current keeps circulating in the same direction but CossA starts to charge: the voltage on the HB node drops and CossB depletes towards ground. The drain falls down in a resonating manner, involving both Coss in parallel and the equivalent inductor made of Ls + Lm. Figure 13 represents the circuit during this event. Figure 13. The Current is Still Flowing through the Source and Contributes to Discharge CossB. Figure 14. When the Voltage on the Node HB Swings Below Ground, QB Body-Diode Conducts. Vbulk D1 + N:1 Vout VLm Lm D2 CS CossA The Voltage is Rising QA IL IL LS Imag Imag CossBQB The Voltage is Falling + Vbulk D1 + N:1 Vout VLm Lm D2 CS CossAQA IL IL LS Imag Imag QB + The bridge voltage further dips and becomes negative until the body-diode of QB conducts. This is what Figure 14 suggests. At the end of the plateau, where IL = Imag, D2 will start conducting, reflecting -NVout over the primary inductance. The energy comes from Cs and Ls, as the source is not playing any role here. The controller now activates QB in ZVS and the transistor conducts in its 3rd quadrant for a few moments, until the current reaches zero and swings negative: we are back at the beginning of the first phase. AND8311/D http://onsemi.com 9 Zero Voltage Switching Figure 15 zooms on these ZVS events and show the various signals in play. The MOSFET current starts to be negative before the appearance of its gate-source bias: this is the body-diode conduction period. Then the MOSFET turns-on at a Vf across its drain-source terminals but the current is still negative: we are in the 3rd quadrant conduction. Finally, the current becomes positive and flows from drain to source, back to the 1st quadrant. -400 -200 0 200 400 26 8 485u 488u 491u 494u 497u TIME (s) -400 -200 0 200 400 3 7 9V GS,upper V GS,lower V HB V HB Body diode 3rd quadrant ID,lower ID,upper 1st quadrant Body Diode 3rd 1st quadrant Q B Q A 26 8 3 7 9V GS,upper V GS,lower V HB HB ID,lower ID,upper 3rd Q B Figure 15. Simulation Results Zooming on the MOSFET Variables quadrant Vb rid ge (V ) Vb rid ge (V ) V gsA V gsB V bridge I L(t) ZVS B ZVS A V gsA V gsB V bridge I L(t) ZVS B ZVS A Figure 16. Measured Signals on a Demonstration Board Showing the ZVS Operation on QA. The selection of a controller where the dead-time is adjustable therefore represents an important selection argument to fine tune the behavior and ensure a minimum conduction period of both body-diodes. Zero Current Switching By the term ZCS, we assume a natural blocking event when the current in the semiconductor is zero. When operating the LLC converter below Fs, as it is the case in this AND8311/D http://onsemi.com 10 example, both secondary-side diodes are operated in ZCS. The current in the concerned diode (D1 or D2) naturally reaches 0 when the magnetizing current Imag equals the main resonating current IL. This is the plateau on figure 6. Observing the diode curren