AN1177-Op Amp Precision Design DC Errors精密运放电路设计之直流误差

AN1177 INTRODUCTION Engineers that use op amps in their circuits; especially those new to analog or op amp circuit design. Also intended for engineers that want to understand op amp DC specifications. Description This application note covers the essential background information and design theory needed to design a precision DC circuit using op amps. Topics include: • Op Amp DC Specifications • Circuit Analysis • Circuit Optimization • Advanced Topics • References This application note is limited to voltage feedback (traditional) op amps. Those interested in current feed- back op amps will benefit from the information here; the DC specifications and op amp DC model have many similarities. For those that are interested, a simple circuit for measuring input offset voltage has been included in Appendix A: “Input Offset Measurement Circuit”. DC SPECIFICATIONS There are a small number of DC specifications that describe errors at the input of an op amp. This section organizes these specifications into those related to the input offset and the others related to input bias currents. Ideal Op Amp Figure 1 shows the ideal, DC model for op amps (the external circuitry is not shown). All error sources are ignored and the open-loop gain (AOL) is infinite. The output voltage is related to the input voltages as shown in Equation 1. FIGURE 1: Ideal, DC Op Amp Model. EQUATION 1: When negative feedback is applied, the ideal op amp’s infinite gain forces VN and VI to be exactly equal; this is the virtual short that some authors talk about. [ 1, 2] When positive feedback is applied (e.g., when used as a comparator), VOUT swings as far negative or positive as it can (to the rails), depending on the sign of the dif- ference (VN – VI). Op Amp Model with DC Errors Figure 2 shows a physically based, DC model for op amps. VPLUS and VMINUS are the external input volt- ages, while VN and VI are the internal input voltages. VOST represents the total input offset voltage error. The non-inverting bias current (IBN) and inverting bias cur- rent (IBI) represent the physical currents seen at each Author: Kumen Blake Microchip Technology Inc. AOL VOUT VN VI VOUT AOL VN VI–( )= Op Amp Precision Design: DC Errors © 2008 Microchip Technology Inc. DS01177A-page 1 of the two input pins. AOL is the finite DC open-loop gain. AN1177 FIGURE 2: Physically Biased, DC Op Amp Model. Input Offset Related Specifications A positive VOST creates a positive shift in the output voltage (VOUT). The DC voltages are: EQUATION 2: The total input offset voltage (VOST) collects the following specifications into one, easy to use parameter: • Input Offset Voltage (VOS): - Specified offset - Describes VOST at a specific bias point • DC Open-Loop Gain (AOL): - AOL = ΔVOUT/ΔVOST • Common Mode Rejection Ratio (CMRR): - CMRR = ΔVCM/ΔVOST - VCM is the common mode input voltage (average of VPLUS and VMINUS) • Power Supply Rejection Ratio (PSRR): - PSRR = Δ(VDD – VSS)/ΔVOST • Input Offset Drift with Temperature (ΔVOS/ΔTA): - Describes how VOST changes with TA; actually ΔVOST/ΔTA - TA is the ambient temperature It is important to understand the units for these specifications. An engineer not used to op amp data sheets may be confused by the units shown. The following list should clear up the confusion. • VOS units are: mV or µV • AOL units do not usually report the relationship shown above: - µV/V for 1/AOL = ΔVOST/ΔVOUT - dB for 20log(AOL) • CMRR units are similar to the AOL units: - µV/V for 1/CMRR = ΔVOST/ΔVCM - dB for 20log(CMRR) • PSRR units are similar to the AOL units: - µV/V for 1/PSRR = ΔVOST/Δ(VDD – VSS) - dB for 20log(PSRR) ΔVOS/ΔTA units are: µV/°C or nV/°C Sometimes PSRR is split in two pieces: PSRR+ that is related to changes in VDD (ΔVDD) and PSRR– that is related to changes in VSS (ΔVSS). These quantities are lumped together in the following equation, where the changes in bias voltages are from those specified for VOS (all units are converted to either V or V/V): EQUATION 3: Notice that all of the specifications will give a positive change in VOST when the corresponding changes are positive. Input Current Related Specifications The input bias currents (IBN and IBI) create voltage drops across external resistances, which cause VOUT to shift. By convention, the currents going into the pins VPLUS and VMINUS are positive. Traditionally, these physically based currents have been mathematically transformed into the equivalent pair of currents IB (input bias current) and IOS (input off- set current). These are the average of IBN and IBI, and their difference, respectively: EQUATION 4: AOL VDD VOUT VSS VN VI IBN VPLUS VMINUS VOST IBI VN VPLUS VOST+= VI VMINUS= VOUT AOL VN VI–( )= AOL VPLUS VMINUS–( ) VOST+( )= Note: Notice that the gains AOL, CMRR and PSRR, when reported in µV/V, are actually their reciprocals. This form of the gains is best for statistical analyses; the values tend to have a Gaussian distribution. VOST VOS ΔVOUT AOL -------------------- ΔVCM CMRR ----------------- ΔVDD PSRR ----------------- ΔVSS PSRR --------------- ΔTA ΔVOS ΔTA ----------------⋅+ + + + += IB IBN IBI+( ) 2 --------------------------= IOS IBN IBI–= DS01177A-page 2 © 2008 Microchip Technology Inc. AN1177 This model makes sense for traditional op amps that have IBN and IBI nearly equal. This means that, in this case, IB is much larger than IOS. This happens because these currents are caused by similar physically phenomena (e.g., matched transistor pair with similar input bias currents). Figure 2 shows how these specified currents are modeled in a circuit. FIGURE 3: Equivalent DC Model for Traditional Op Amps. Some newer op amp architectures have IOS near to the same magnitude as IB. This happens because the physical causes of IBN and IBI are not physically related (they are independent or uncorrelated). Most data sheets still use IB and IOS as the specifications. The input currents depend strongly on architecture, type of input transistors, and temperature. As discussed before, traditional parts have IB >> IOS. Some of the newer architectures have IOS and IB of about the same size. Most op amps have ESD diodes at the inputs. PN junction ESD diodes tend to have small reverse leakage at room temperature. These leakage currents increase by a factor of 2 for each 10°C increase in temperature. Since the ESD diodes tend to match well, the differences between leakage currents tend to be small. These leakage currents are a part of the input bias currents. When an input goes outside the supply voltage(s) the ESD diodes are tied to, the forward current can grow to be very large. CMOS inputs transistors have very small input bias currents. Most of these op amps use ESD diodes at the input for protection; the reverse leakage currents of these ESD diodes are the dominant input bias currents. Electrometer grade op amps minimize input currents. They typically use FET transistors at the input that give currents in the femto-ampere (1015A) range. Bipolar inputs have larger input bias currents. They are the input differential pair’s base currents, which do not change much with supply voltage. They will change significantly with temperature (e.g., a 4 × range between -40°C and +125°C). These op amps usually use ESD diodes, which increase the bias currents; especially at high temperatures. CIRCUIT ANALYSIS Using a few simple techniques, it is easy to analyze the DC error performance of op amp circuits. Several common circuits illustrate these techniques. Resistance Seen by the Non-inverting Input Figure 4 is a simple circuit with a source and several impedances attached to the non-inverting input. The process of calculating the equivalent resistance seen by the non-inverting input will be described using this circuit as the starting point. FIGURE 4: Simple Circuit. The first step is to replace all external components with their DC equivalent for a Thevenin analysis: • Voltage sources become 0V (short circuit) • Current sources become 0A (open circuit) • Resistors are left as is • Capacitors become ∞Ω (open circuit) • Inductors become 0Ω (short circuit) Figure 5 shows the resulting circuit when this is done to those components attached to the non-inverting input of the op amp in Figure 4. A test source (VX) has been added to help in the Thevenin analysis. FIGURE 5: Equivalent DC Circuit for Non-inverting Input. The equivalent resistance seen by the non-inverting input, for this example, is: EQUATION 5: This resistance is used in the error calculations for the non-inverting bias current (IBN) source. Figure 6 shows how this is accomplished; the error at the op amp input is calculated at this point of the process. AOL VDD VOUT VSS VN VI IB + IOS/2 VPLUS VMINUS VOST IB – IOS/2 R1 L1 C1 R2V1 VOUT U1 R1 R2 VX IX RNEQ VX IX ------= R1= R2|| © 2008 Microchip Technology Inc. DS01177A-page 3 AN1177 FIGURE 6: Application to Non-inverting Bias Current Error Calculations. The error voltage (VIBN) shown in Figure 6 can be placed in an equivalent circuit diagram that does not explicitly show the current IBN. This will make the analysis easier, and more consistent, in later steps. This new equivalent circuit is shown in Figure 7 (IBN is already included in VIBN). The VIBN source, when it is positive, will produce a positive change in VOUT. FIGURE 7: Application to Non-inverting Bias Current Error Calculations. This equivalent circuit has the same connections as the original one (Figure 4) to simplify the analysis; this will be useful later on as we combine all of the error terms. Resistance Seen by the Inverting Input Figure 8 is a non-inverting gain amplifier. The process discussed in the last section will be used here to calculate the resistance seen by the inverting input. FIGURE 8: Non-inverting Gain Circuit. The same process of generating a Thevenin equivalent applies here, with one short cut: • The op amp’s output (VOUT) is treated as a voltage source - It becomes a short to ground Figure 9 shows the resulting circuit at the inverting input, with the test source (VX). FIGURE 9: Equivalent DC Circuit for the Inverting Input. The equivalent resistance seen by the inverting input, for this example, is: EQUATION 6: This resistance is used in the error calculations for the inverting bias current (IBI) source. Figure 10 shows how this is done for the error at the op amp output, referred to the input. FIGURE 10: Application to Inverting Bias Current Error Calculations. The error voltage (VIB) shown in Figure 10 is placed in an equivalent circuit diagram that does not explicitly show the current IBI; see Figure 11 (IBI is already included in VIBI). The VIBI source, when it is positive, will produce a positive change in VOUT. RNEQ VOUT U1 IBN VIBN = -IBN RNEQ VIBN VOUT U1 VIBN = -IBN RNEQ VIBN 0 R1 L1 C1 R2V1 R2 V1 VOUT U1 R3 Note: Since the op amp’s inverting input voltage must equal its non-inverting input voltage, VIBI is shown as a change in VOUT referred to the input. R2 R3 VX IX RIEQ VX IX ------= R2= R3|| VOUT U1 IBI VIBI = IBI RIEQVIBI RIEQ DS01177A-page 4 © 2008 Microchip Technology Inc. AN1177 FIGURE 11: Application to Inverting Bias Current Error Calculations. The resistors R2 and R3 are shown with the same connections as the original circuit (Figure 8) to simplify the analysis; this will be explained in the next section. Combined Input Voltage Errors and Noise Gain All of the DC errors at an op amp’s input (VOST, VIBN and VIBI) can be combined into one equivalent voltage source (VIE) at the non-inverting input pin (see Figure 12): EQUATION 7: FIGURE 12: Circuit Diagram Illustrating the Concept of Noise Gain. Noise gain (GN) is the DC gain from VIE (at the non- inverting input pin) to VOUT when the op amp operates in a closed-loop condition, when all other (external) energy sources are zero. GN is positive for stable feed- back loops. This gain can be obtained with any reason- able circuit analysis method. In equation form, we have: EQUATION 8: The following examples will show how this concept is applied in common op amp circuits. Output DC Error Now we can quickly calculate the output error of the op amp (VOE) using the information we have developed. The principle of superposition gives: EQUATION 9: Examples UNITY GAIN BUFFER Figure 13 shows a unity gain buffer using an op amp. The op amp’s DC model is shown inside the dashed box. FIGURE 13: Unity Gain Buffer. Because the resistances seen by the op amp inputs are zero and GN = 1 V/V, the output voltage is simply: EQUATION 10: Let’s use Microchip’s MCP601 op amp to illustrate this design. We’ll assume that VCM, VDD and VOUT vary across their complete ranges. We’ll use an arbitrary estimate of the worst-case value for ΔVOS/ΔTA (see the data sheet for the official specifications). R1 and R3 will be 0.1% resistors. VIBI = IBI RIEQ 0 R2 VOUT U1 R3 VIBI VIE VOST VIBN VIBI+ += VOUT U1Feedback and VIE VINk Signal Path Circuitry n GN VOUT VIE -------------= Where: VINk = 0V k = 1 to n Note: The concept of noise gain is central to understanding op amp behavior. For instance, it simplifies op amp bandwidth, noise and stability analyses. Note: Since the MCP601’s common mode input voltage range (VCMR), at +25°C, is limited to the range -0.3V and VDD – 1.2V, there will be large output errors when VCM approaches VDD. VOE GNVIE= GN VOST VIBN VIBI+ +( )= U1 VOUT VIN VOSTIBN IBI VOUT VIN VOST+= © 2008 Microchip Technology Inc. DS01177A-page 5 AN1177 EXAMPLE 1: NON-INVERTING AMPLIFIER Figure 14 shows a non-inverting gain amplifier with an LC low-pass filter at the input. The op amp’s DC model is shown inside the dashed box. FIGURE 14: Non-inverting Gain Amplifier. The output voltage with error is: EQUATION 11: The MCP601 VOST calculations in Example 1 can be used for a gain of +10 V/V example: EXAMPLE 2: INVERTING AMPLIFIER Figure 15 shows an inverting gain amplifier. The op amp’s DC model is shown inside the dashed box. FIGURE 15: Inverting Gain Amplifier. The output voltage with error is: EQUATION 12: Notice that Example 2 is easily modified for an inverting gain of -9 V/V; the resistors and VOE are the same (only the signal gain is changed). Maximum VOE = VOST: VOS < ±2.00 mV ΔVOUT/AOL ≤ (2.65V)/(100 kV/V)≤ 0.03 mV ΔVDD/PSRR ≤ (1.40V)/(10.0 kV/V)≤ 0.14 mV ΔVCM/CMRR ≤ (4.3V – (-0.3V))/(5.62 kV/V)≤ 0.82 mV = ±0.41 mV ΔTA(ΔVOS/ΔTA) ≤ (100°C) (±12 µV/°C)≤ ±1.20 mV VOST ≤ ±3.8 mV VIN R1 L1 C1 U1 VOUT VOSTIBN IBI R3R2 R1 VOE GN VOST VIBN VIBI+ +( )= VOUT GNVIN VOE+= Where: GN = 1 + R3/R2 RNEQ = R1 RIEQ = R2||R3 VIBN = –IBNRNEQ VIBI = IBIRIEQ Maximum VOST = ±3.8 mV Selected Resistors (see Figure 14): Maximum VIBN: Maximum VIBN: Maximum VOE: R3 = 20.0 kΩ R2 = 2.21 kΩ R1 = 2.00 kΩ GN = 10.05 V/V RNEQ = 2.00 kΩ VIBN ≥ -(5 nA + 0.5 nA)(2.00 kΩ) = -11 µV RIEQ = 1.99 kΩ VIBN ≤ (5 nA – 0.5 nA)(1.99 kΩ) = 9 µV VOE ≤ ±38 mV U1 VOUT VIN VOSTIBN IBI R3R2 R1 VOE GN VOST VIBN VIBI+ +( )= VOUT GN 1–( )– VIN VOE+= Where: GN = 1 + R3/R2 RNEQ = R1 RIEQ = R2||R3 VIBN = –IBNRNEQ VIBI = IBIRIEQ DS01177A-page 6 © 2008 Microchip Technology Inc. AN1177 DIFFERENCE AMPLIFIER Figure 16 shows a difference amplifier. The op amp’s DC model is shown inside the dashed box. Notice that this circuit can be analyzed quickly using superposition. FIGURE 16: Difference Amplifier. The output voltage with error is: EQUATION 13: Using the MCP601 in a differential amplifier with gain 10 V/V gives (similar to Example 2): EXAMPLE 3: CIRCUIT OPTIMIZATION There are a few, simple design techniques that can quickly help a designer reach an acceptable accuracy. Gain Selection Set any amplifier next to a signal source (e.g., temper- ature sensor) to the highest reasonable gain. This will cause any later gains to be small; typically they will be at a gain of 1 V/V. This design technique minimizes the impact most of the analog signal processing components have on the overall error. It also allows the designer to reduce cost by specifying more precise components only where they are needed. Minimizing Bias Current Errors For the examples shown in Figure 13 through Figure 16, it is instructive to convert the bias current error voltages to the equivalent form using the specified currents: EQUATION 14: Minimizing the resistances helps minimize these errors for all op amps. Many op amps’ bias current (IB) have a much larger maximum specification than their offset current (IOS). In that case, set RN_EQ = RI_EQ for the best performance. When IOS is much smaller than IB, the resistor toler- ance (RTOL) needs to be good enough to prevent IB from becoming a significant contributor to the error: EQUATION 15: Large input resistances can also cause a significant shift in the input common mode voltage (VCM). In some cases, this can significantly reduce the input common mode voltage range (VCMR): EQUATION 16: U1 VOUT VM VOSTIBN IBI R4R3 VP R2R1 VREF VOE GN VIE VIBN VIBI+ +( )= VOUT GN 1–( ) VP VM–( ) VREF VOE+ += Where: R2 = R1 R4 = R3 GN = 1 + R2/R1 = 1+R4/R3 RNEQ = R1||R2 RIEQ = R3||R4 VIBN = –IBNRNEQ VIBI = IBIRIEQ Maximum VOST = ±3.8 mV Selected Resistors (see Figure 16): Maximum Error Voltages: R1 = R3 = 2.00 kΩ R2 = R4 = 20.0 kΩ GN = 11.00 V/V (GN–1) = 10.00 V/V, the differential gain VIBN ≥ -(5 nA + 0.5 nA)(1.82 kΩ) = -10 µV VIBN ≤ (5 nA – 0.5 nA)(1.82 kΩ) = 8 µV VOE ≤ ±42 mV VIBN VIBI+ IBNRNEQ– IBIRIEQ+= IB RIEQ RNEQ–( ) IOS RIEQ RNEQ+ 2 ---------------------------------⎝ ⎠⎛ ⎞–= RTOL << 4 IOS IB -------- ΔVCM IB– RIEQ RNEQ+ 2 ---------------------------------⎝ ⎠⎛ ⎞= VCMR_EQ VCMR ΔVCM+= © 2008 Microchip Technology Inc. DS01177A-page 7 AN1177 Op Amp Selection The op amp needs to support the level of DC precision required by the design. Table 1 shows four general op amp architectures that give trade-offs between performance, cost and design complexity. TABLE 1: OP AMP CAPABILITIES(1) Process and Environmental Variations Methods to evaluate a design’s variation in performance are commonly understood in the industry. Examples include worst case analysis (all tolerances at minimum or maximum) and RSS (Root Sum of Squares – a statistical approach). The following list gives important op amp behaviors to include when evaluating process and environmental changes (almost all have a Gaussian distribution): • VOS - All VOS values for duals and quads are statistically independent (zero correlation) • 1/AOL, 1/CMRR and 1/PSRR (in units of µV/V) • ΔVOS/ΔTA • Offset Aging - Increases with time - Only specified on auto-zeroed op amp data sheets • IB and IOS - CMOS inputs (with ESD diodes) have an exponential relationship with temperature (double every 10°C increase) - Bipolar inputs typically double at -40°C and are halved at +125°C - Are typically uncorrelated ADVANCED TOPICS PCB Layout Printed Circuit Board (PCB) layout can have a signifi- cant effect on DC precision. Effects that need to be considered include: • Ground Loops – Poor grounding techniques and inattention to current return paths can cause significant shifts in DC voltages • Crosstalk – Other signals on a PCB can find sneak paths through the ground, power supplies and traces Input Common Mode Voltage Range A commonly overlooked error source is allowing the signal to go outside the input voltage range. This most commonly occurs when using a non-rail-to-rail input op amp in unity gain; the input will cause an output error when the VCMR is exceeded; this error grows quickly. Output Voltage Range There will be a significant error, that grows very quick, when the output voltage range is exceeded. The VOL and VOH specifications usually shown in op amp data sheets describe non-linear behavior (i.e., when used as a comparator). When the output approaches either limit, VOST can increase significantl