FPGA可编程逻辑器件芯片XCKU060-1FFVA1156I中文规格书

UltraScaleDevicePackagingandPinoutsUG575(v1.14)March18,2020Chapter1PackagingOverviewUltraScaleDevicePackagingandPinoutsUG575(v1.14)March18,2020Chapter1:PackagingOverviewGigabitTransceiverChannelsbyDevice/PackageTable1-2liststhequantityofgigabittransceiverchannelsfortheUltraScaleandUltraScale+devices.Inalldevices,agigabittransceiverchannelisonesetofMGTRXP,MGTRXN,MGTTXP,andMGTTXNpins.Fortransceiverdataratelimitationsonspecificdevice/packagecombinations,seethespecificUltraScaleandUltraScale+devicedatasheets[Ref4].FSVA3824SSI,flip-chip,fine-pitch,lidlesswithstiffenerringBGA1.065x65FSVB3824SSI,flip-chip,fine-pitch,lidlesswithstiffenerringBGA1.065x65Notes:1.FFV,FLV,andFLGpackagesarefootprintcompatiblewhenthepackagecodeletterdesignatorandpincountareidentical.SeeUltraScaleArchitectureandProductOverview(DS890)[Ref1]forspecificlettercodesandorderingcodeinformation.2.These52.5x52.5packageshavethesamePCBballfootprintasthe47.5x47.5packagesandarefootprintcompatible.Table1-1:PackageSpecifications(Cont’d)Packages(1)DescriptionPackageSpecificationsPackageTypePitch(mm)Size(mm)Table1-2:SerialTransceiverChannels(GTH/GTY)byDevice/PackageDevicePackageGTHChannelsGTYChannelsKintexUltraScaleDevicesXCKU035FBVA676160XCKU040160XCKU035SFVA78480XCKU04080XCKU035FBVA900160XCKU040160XCKU025FFVA1156120XCKU035160XCKU040200XCKU060280XCKU095208XCKU060FFVA1517320XCKU085FLVA1517480XCKU115480XCKU095FFVC15172020XCKU115FLVD1517640XCKU095FFVB17603216UltraScaleDevicePackagingandPinoutsUG575(v1.14)March18,2020Chapter1:PackagingOverviewUltraScaleDevicePackagingandPinoutsUG575(v1.14)March18,2020Chapter1:PackagingOverviewPinDefinitionsTable1-5liststhepindefinitionsusedinUltraScaleandUltraScale+devicepackages.Table1-5:PinDefinitionsPinNameTypeDirectionDescriptionUserI/OPinsIO_L[1to24][PorN]_T[0to3][UorL]_N[0to12]_[multi-function]_[banknumber]orIO_T[0to3][UorL]_N[0to12]_[multi-function]_[banknumber]DedicatedInput/OutputMostuserI/Opinsarecapableofdifferentialsignalingandcanbeimplementedaspairs.EachuserI/Opinnameconsistsofseveralindicatorlabels,where:•IOindicatesauserI/Opin.•L[1to24]indicatesauniquedifferentialpairwithP(positive)andN(negative)sides.UserI/OpinswithouttheLindicatoraresingle-ended.•T[0to3][UorL]indicatestheassignedbytegroupandnibblelocation(upperorlowerportion)withinthatgroupforthepin.•N[0to12]thenumberoftheI/Owithinitsbytegroup.•[multi-function]indicatesanyotherfunctionsthatthepincanprovide.Ifnotusedforthisfunction,thepincanbeauserI/O.•[banknumber]indicatestheassignedbankfortheuserI/Opin.UserI/OMulti-FunctionPinsGCorHDGCMulti-functionInput/OutputFourglobalclock(GC)pinpairsareineachbank.HDGCpinshavedirectaccesstotheglobalclockbuffers.GCpinshavedirectaccesstotheglobalclockbuffers,MMCMs,andPLLsthatareintheclockmanagementtile(CMT)adjacenttothesameI/Obank.GCandHDGCinputsprovidededicated,high-speedaccesstotheinternalglobalandregionalclockresources.GCandHDGCinputsusededicatedroutingandmustbeusedforclockinputswherethetimingofvariousclockingfeaturesisimperative.GCorHDGCpinscanbetreatedasuserI/Owhennotusedasinputclocks.Up-to-dateinformationaboutdesigningwiththeGC(orHDGC)pinisavailableintheUltraScaleArchitectureClockingResourcesUserGuide(UG572)[Ref6].VRP(1)Multi-functionN/AThispinisfortheDCIvoltagereferenceresistorofPtransistor(perbank,tobepulledLowwithareferenceresistor).UltraScaleDevicePackagingandPinoutsUG575(v1.14)March18,2020Chapter1:PackagingOverviewMGTAVTT_[LorR][N,UC,C,LC,orS](5)DedicatedInputAnalogpower-supplypinforthetransmitdriver.MGTVCCAUX_[LorR][N,UC,C,LC,orS](5)DedicatedInputAuxiliaryanalogQuadPLL(QPLL)voltagesupplyforthetransceivers.MGTREFCLK[0or1][PorN]DedicatedInputDifferentialreferenceclockforthetransceivers.MGTAVTTRCAL_[LorR][N,UC,C,LC,orS](5)DedicatedN/APrecisionreferenceresistorpinforinternalcalibrationtermination.MGTRREF_[LorR][N,UC,C,LC,orS](5)DedicatedInputPrecisionreferenceresistorpinforinternalcalibrationtermination.Table1-5:PinDefinitions(Cont’d)PinNameTypeDirectionDescription