FPGA可编程逻辑器件芯片XCKU115-2FLVA1517I中文规格书

KCU1500BoardUserGuideUG1260(v1.4)October12,2018FPGAConfigurationTheKCU1500boardsupportstwoUltraScale™FPGAconfigurationmodes:•QuadSPIflashmemory•JTAGusing:°PlatformcableheaderJ2°USBJTAGconfigurationport(USBJ34/FT2232HU65)Atpowerup,theFPGAisconfiguredbydualQuadSPINORflashdevices(MicronMT25QU512ABB8E12-0SIT)operatingataclockrateof90MHz(EMCCLK)usingthe"MasterSerial"Configurationmode.AnexternalEMCCLKconfigurationclockisusedtoallowforthehighestconfigurationspeedwithSPIflash,andthedualQuadSPIflashmemorydevicesprovideatotaldatapathof8bits.EachoftheQuadSPIflashmemoryNORdeviceshasacapacityof512Mb.ThetwoQuadSPIflashmemorydevicesprovideacombinedconfigurationcapacityof1Gb.TwoconfigurationmodesaresupportedontheKCU1500,aslistedinTable2-4.WhiletheFPGAmodepinsM2,M1,andM0arewiredtotheactive-LowmodeDIPSW5,onlyM2onSW5pin7shouldbetoggledtoselectbetweenM[2:0]=001and101.TheFPGAdefaultmodesettingisM[2:0]=001=SW5[2:4]=(On,On,Off),selectingtheQuadSPIflashmemoryconfigurationmode.ForcompletedetailsonconfiguringtheFPGA,seetheUltraScaleArchitectureConfigurationUserGuide(UG570)[Ref1].Table2-4:ConfigurationModesConfigurationModesM[2:0]BusWidthCCLKDirectionMasterSPI001x1,x2,x4FPGAoutputJTAG101x1N/A找FPGA和CPLD可编程逻辑器件，上深圳宇航军工半导体有限公司KCU1500BoardUserGuideUG1260(v1.4)October12,2018Chapter3:BoardComponentDescriptionsI/OVoltageRailsThereare15I/ObanksavailableontheXCKU115deviceandtheKCU1500board.ThevoltagesappliedtotheXCKU115U1FPGAI/ObanksarelistedinTable3-1.Table3-1:I/OBankVoltageRailsKCU1500BoardUserGuideUG1260(v1.4)October12,2018Chapter3:BoardComponentDescriptionsKCU1500BoardUserGuideUG1260(v1.4)October12,2018Chapter3:BoardComponentDescriptionsForadditionalinformationaboutthequadsmallform-factorpluggable(28Gb/sQSFP+)module,seetheSFF-8663specificationforthe28Gb/sQSFP+attheSFF-8663specificationwebsite[Ref13].I2CBusTheKCU1500boardimplementsasingleI2Cbus(IIC_MAIN_SCL/SDA_LS),wiredthroughlevel-shifterU45andthenroutedtoa1-to-8channelI2CTIPCA9548busswitch(U44).Thebusswitchcanoperateatspeedsupto400kHz.TheKCU1500boardI2CbustopologyisshowninFigure3-8.UserapplicationsthatcommunicatewithdevicesononeofthedownstreamI2CbusesmustfirstsetupapathtothedesiredtargetbusthroughtheU44busswitchatI2Caddress0x74(0b1110100).Table3-3liststheI2CaddressoftheTCA9548U44busswitchtargetdevices.X-RefTarget-Figure3-8Figure3-8:I2CBusTopologyXCKU115-2FLVB2104EU1BANK84PCA9306I2CLevelShifterI2C_MAIN_SCA/SCL_LSSC1SC2TCA9548I2C1-to-8BusSwitchI2CC_MAIN_SDA/SCLU45U44VCC1V8_FPGA3V3_PEXCH0–PMBUS_SDA/SCLCH1–QSFP1_I2C_SDA/SCLCH2–USER_S1570_CLOCK_SDA/SCLCH3–FAN_I2C_SDA/SCLCH4–QSFP0_I2C_SDA/SCLCH5–IIC_SDA/SCL_EEPROMCH6–NCCH7–NCX19434-070517Table3-3:I2CBusAddressesI2CBusI2CSwitchPositionI2CAddressDeviceBinaryFormatHexFormatTCA95488-channelbusswitchN/A0b11101000x74U44TCA9548PMBUS_SDA/SCL00x0A,0x12,0x14,0x72,0x73MAX15301,MAX20751QSFP1_I2C_SDA/SCL10b10100000x50J30QSFP1USER_SI570_CLOCK_SDA/SCL20b10111010x5DU32SI570FAN_I2C_SDA/SCL30b10011000x4CU53LM96063QSFP0_I2C_SDA/SCL40b10100000x50J28QSFP0EEPROM_IIC_SDA/SCL50b10100000x50U119M24C08Notused6N/AN/AN/ANotused7N/AN/AN/AKCU1500BoardUserGuideUG1260(v1.4)October12,2018Chapter3:BoardComponentDescriptionsRailNamePowerSystemRegulatorsU18CurrentSenseSYSMONMultiplexerPortSchematicPageNumberRef.Des.DeviceTypeVout(V)Max.I(A)Addr.Bin.Addr.PortVCCINT_FPGAU20MAX153010.95300x0ANANA22VCC1V8_FPGAU21MAX153011.80100x14001S223VCC1V2_FPGAU25MAX153011.20100x12100S524MGTAVCC_FPGAU28MAX207510.95300x72NANA25MGTAVTT_FPGAU37MAX207511.20300x73111S827Non-PMBusRegulatorsSYS_5V0U34MAX175025.001NANANA26SYS_2V5U27MAX150272.501NANANA26MGTVCCAUXU30MAX8869E1.811NANANA26DDR4_C0_VTTU117TPS512000.603NANANA26DDR4_C1_VTTU32TPS512000.603NANANA26DDR4_C2_VTTU118TPS512000.603NANANA26DDR4_C3_VTTU35TPS512000.603NANANA26