20 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 17, NO. 1, FEBRUARY 2008
A Low-Cost 128 × 128 Uncooled Infrared
Detector Array in CMOS Process
Selim Eminoglu, Member, IEEE, Mahmud Yusuf Tanrikulu, Member, IEEE, and Tayfun Akin, Member, IEEE
Abstract—This paper discusses the implementation of a low-cost
128 × 128 uncooled infrared microbolometer detector array to-
gether with its integrated readout circuit (ROC) using a standard
0.35 µm n-well CMOS and post-CMOS MEMS processes. The
detector array can be created with simple bulk-micromachining
processes after the CMOS fabrication, without the need for any
complicated lithography or deposition steps. The array detectors
are based on suspended p+-active/n-well diode microbolometers
with a pixel size of 40 µm × 40 µm and a fill factor of 44%. The
p+-active/n-well diode detector has a measured dc responsivity
(�) of 4970 V/W and a thermal time constant of 36 ms at
50 mtorr vacuum level. The total measured rms noise of the diode
type detector is 0.69 µV for an 8 kHz bandwidth, resulting in a de-
tectivity (D∗) of 9.7 × 108 cm · Hz1/2/W. The array is scanned
by an integrated 32-channel parallel ROC including low-noise dif-
ferential preamplifiers with an electrical bandwidth of 8 kHz. The
128 × 128 focal plane array (FPA) has one row of infrared-blind
reference detectors that reduces the effect of FPA fixed pattern
noise and variations in the operating temperature relaxing the
requirements for the temperature stabilization. Including the noise
of the reference and array detectors together with the ROC noise,
the fabricated 128 × 128 FPA has an expected noise equivalent
temperature difference (NETD) value of 1 K for f/1 optics at
30 frames/s (fps) scanning rate. This NETD value can be decreased
to 350 mK by improving the post-CMOS fabrication steps and
increasing the number of readout channels. [2007-0157]
Index Terms—CMOS infrared detector, CMOS micromachined
sensor, low-cost infrared detector, microbolometer, microbolome-
ter readout circuit, uncooled infrared detector.
I. INTRODUCTION
UNCOOLED infrared detectors have recently gained wideattention for infrared imaging applications, due to their
advantages, such as low cost, low weight, low power, wide
spectral response, and long-term operation compared to those
of photon detectors. Uncooled technology has great potential
for use in various civilian applications, like driver’s night vision
enhancement, fire detection, security systems, and automotive
Manuscript received July 3, 2007; revised September 16, 2007. This work
was supported in part by NATO’s Scientific Affairs Division in the frame-
work of the Science for Stability Program and in part by the Research and
Development Department of Ministry of Defense (MSB ArGe). Subject Editor
R. Howe.
S. Eminoglu was with the Department of Electrical and Electronics Engi-
neering, Middle East Technical University, Ankara 06531, Turkey. He is now
with Teledyne Scientific LLC, Thosand Oaks, CA 91360 USA.
M. Y. Tanrikulu and T. Akin are with the Department of Electrical and
Electronics Engineering, Middle East Technical University, Ankara 06531,
Turkey (e-mail: tayfuna@metu.edu.tr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JMEMS.2007.910235
safety systems. A worldwide effort is still continuing to im-
plement very large format arrays at low cost. For this, many
researchers are trying to integrate uncooled infrared detectors
with readout electronics monolithically with a CMOS process.
The compatibility of the detectors with CMOS technology, and
therefore, monolithic CMOS integration, is one of the main
issues for achieving low-cost detectors.
One of the most famous approaches for uncooled infrared
imaging is to implement microbolometers using surface micro-
machined bridges on CMOS processed wafers, where infrared
radiation increases the temperature of a material on the ther-
mally isolated and suspended bridge, causing a change in its
resistance [1]–[17]. There are efforts to implement micro-
bolometers using many different materials, such as vanadium
oxide (VOx) [1], [2], [9]–[15], amorphous silicon (a-Si) [3],
[16], [17], polycrystalline silicon−germanium (poly SiGe) [4],
yttrium barium copper oxide (YBaCuO) [5], [6], and metal
films [7], [8]. Outstanding performance has been demonstrated
with surface micromachined microbolometers having focal
plane array (FPA) sizes as large as 640 × 480 and pixel sizes
ranging from 50 µm down to 17 µm, especially using VOx and
a-Si, with performances close to those of cooled infrared detec-
tors at much lower cost [9]–[17]. However, these detectors are
mainly developed for military application, and their costs are
not as low as the required level for many commercial applica-
tions, as all of the surface micromachined resistive bolometers
require post-CMOS material deposition and etching steps, as
well as a number of high-precision lithography steps, limiting
their cost reduction. In addition, some of these approaches are
not compatible with CMOS process lines and require dedicated
fabrication facilities.
Another important microbolometer approach is to use sil-
icon p-n diodes as the temperature sensitive element in mi-
crobolometer arrays [18]–[20]. Array pixels are based on
suspended multiple series diodes fabricated on SOI CMOS
wafers, and successful implementation of 320 × 240 FPAs with
40 µm pixel pitch and 640 × 480 FPAs with 25 µm pixel pitch
have been reported [18]–[20]. Although this approach provides
very uniform arrays with very good potential for low-cost high
performance uncooled detectors, its fabrication is based on a
dedicated in-house SOI CMOS process, where intra-CMOS
MEMS process steps are included. Since these detectors cannot
be implemented in a standard CMOS or SOI CMOS process, it
would be difficult to reduce their costs down to limits that very
low-cost applications require.
A different microbolometer approach is recently proposed
for very low-cost applications, where the detector material is
obtained with very thin Si/SiGe single crystal multilayers [21].
1057-7157/$25.00 © 2008 IEEE
EMINOGLU et al.: LOW-COST 128 × 128 UNCOOLED INFRARED DETECTOR ARRAY IN CMOS PROCESS 21
As this material requires high temperature epitaxial growth,
it cannot be grown on CMOS readout electronics. Instead,
the material is grown on a separate substrate, and then, it is
transferred on top of the CMOS readout electronics using a
3-D bolometer integration process [22]–[24]. Although this
approach aims at low cost detector arrays, it requires a rather
complicated process with unconventional production methods,
where yield might be a problem.
One of CMOS based infrared imager approaches is to
use thermopile arrays implemented with front or back-side
bulk-micromachining of CMOS fabricated wafers [25], [26].
However, thermopile arrays have low responsivity values
(2–15 V/W) and large pixel pitch (100–250 µm), limiting
their use for large detector arrays. In addition, these detectors
also require extra processing steps to form electroplated gold
lines for thermal isolation between the pixels [25] or special
processing steps that results in a custom-made CMOS process
to achieve the required structure [26].
Another unconventional and potentially low-cost approach
is to implement FPAs using thermally tunable thin film filter
membrane pixels [27]–[29]. Each of these pixels acts as a
wavelength translator, converting far infrared radiation signals
into near infrared signals, which are optically detected by off-
the-shelf charge coupled device (CCD) or CMOS cameras. This
optical readout approach introduces some unique difficulties
such as readout complexity, shot noise, and vibration and
thermomechanical noise. In addition to these unique difficul-
ties, this approach has other challenges such as nonuniformity,
sensitivity to critical film properties, and sensitivity to ambient
temperature, limiting its low-cost target. There are still efforts
to overcome these difficulties and fabricate low-cost infrared
imagers with high performance [29].
For ultra low-cost applications, the best approach would be
to implement the detector arrays together with their readout
circuitry fully on a standard CMOS or SOI-CMOS process,
using some simple post-CMOS etching steps where neither any
critical lithography nor any detector material deposition steps
are needed. We have previously demonstrated the implemen-
tation of such low-cost uncooled microbolometer FPAs with
16 × 16 array format, where the n-well layer in a standard
0.8 µm CMOS process is used as the active detector material
[30], [31]. The pixels in these prototype FPAs have a size
of 80 µm × 80 µm with a fill factor of 13%, which is low
due to the limitations of silicon bulk-micromachining used in
detector fabrication. We have also reported fabrication of a
new low-cost small pixel size detector structure, where the
pixel is achieved with a new post-CMOS processing approach
on dies fabricated using a standard 0.35 µm CMOS process
[32], [33] along with its first array implementation [34]. This
paper reports the implementation of a larger FPA with 128 ×
128 pixels based on this detector structure along with improved
readout circuitry [35]. The pixels used in the FPA have a size of
40 µm × 40 µm, while having an increased fill factor of 44%.
Each detector in the FPA is implemented with a suspended
p+-active/n-well diode, which provides very low noise when
biased at low current. This infrared FPA fabrication approach
is very simple and suitable for ultra low-cost infrared imaging
applications.
Fig. 1. Perspective view of the p+/n-well active diode microbolometer that
can be obtained in a standard n-well CMOS process.
II. PIXEL STRUCTURE AND IMPLEMENTATION
Fig. 1 shows a perspective view of the p+-active/n-well
diode microbolometer that can be obtained in a standard
n-well CMOS process after post-CMOS MEMS processes [33].
Infrared radiation heats the absorbing layer on the thermally
isolated n-well, increasing its temperature, which in turn results
in a change in the diode voltage related to its temperature
coefficient. Bulk silicon under the n-well is etched away to
reduce thermal conductance and to increase responsivity of
the detector. To obtain high thermal isolation, the interconnect
material on support arms are implemented using polysilicon.
This thermally isolated suspended structure is obtained by
front-side bulk-etching of fabricated CMOS dies, where the
electrochemical etch-stop technique is used to prevent the etch-
ing of the n-well [36], [37].
The pixel size and fill factor are determined by process limi-
tations, such as the minimum interconnect width and openings
between the arms that allow silicon to be exposed to the solution
during etching. To improve the fill factor, etch openings are
drawn at their minimum possible dimensions, and no initial
oxide openings are created on the CMOS fabricated FPAs. The
required etch openings are created in an optimized selective dry
etch process using a mixture of CHF3 and O2 gases, where
CMOS metal layers are used as protection masks [34], [38].
After the necessary openings are created on the surface to reach
the silicon substrate, the silicon underneath the pixel is removed
in an anisotropic silicon etchant, Tetra-Methyl Ammonium
Hydroxide (TMAH), while the electrochemical etch-stop
process is used to prevent etching of the n-well layer. Fig. 2
shows the post-CMOS fabrication steps and the cross-sections
of the pixel structure after (a) CMOS fabrication, (b) dry-
etch, and (c) anisotropic silicon etch process in TMAH. At
the beginning, the surface of the pixel is covered with oxide.
After dry-etching, all the oxide not protected by metal layers is
etched down to the silicon substrate, and the protected regions
are stopped at particular metallization levels. The silicon un-
derneath the pixel is removed by using a front-side bulk silicon
micromachining technique. Finally, the metal mask layers are
removed by a simple metal etch process [33].
This approach has a number of advantages. First of all, it
does not require any critical lithography step after the CMOS
process, reducing the cost of the process. In addition, the gaps
between the arms can be reduced as the CMOS technology
allows, making it possible to reduce the pixel size while
22 JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL. 17, NO. 1, FEBRUARY 2008
Fig. 2. Post-CMOS fabrication steps and the cross section of the diode pixel
structure (a) after CMOS process, (b) after dry etch, and (c) anisotropic silicon
etch [33].
Fig. 3. (a) Block diagram and (b) layout of the 128 × 128 uncooled infrared
imager chip. The chip measures 6.5 mm × 7.9 mm in a standard 0.35 µm
CMOS process.
increasing the fill factor. Also, there is no need for any
complicated post-CMOS deposition or surface micromachin-
ing process steps that increase the processing cost and that
decreases the yield. Therefore, the detector cost is expected to
be very close to the cost of the CMOS chip.
III. FPA ARCHITECTURE
Fig. 3 shows the block diagram and the layout of the fabri-
cated 128 × 128 uncooled infrared FPA. The array and refer-
ence row pixels are addressed by row and column multiplexers
(Row and Column Mux) controlled by vertical and horizontal
shift register (VSR and HSR) blocks. The array pixels are
read out differentially with respect to reference pixels through
a 32-channel low-noise readout circuit (ROC) composed of
differential transconductance amplifiers, switched capacitor in-
tegrators, and sample-and-hold circuits at 30 frames/s (fps)
with an electrical bandwidth of 8 kHz. Final analog output
is multiplexed through two serial outputs (Ser Out-1, Ser
Out-2) controlled by output shift register (OSR) at a rate of
250 K samples/s. All the blocks are controlled by an on-
chip timing circuit. There are on-chip temperature sensors to
monitor the die temperature, and on-chip etching circuitry to
properly bias the pixels during the silicon etching process. The
chip measures 6.5 mm × 7.9 mm in a standard 0.35 µm CMOS
process.
Pixels in the array are read out with respect to on-chip
infrared-blind reference detectors to minimize the effect of
ambient temperature variations. Fig. 4 shows the simplified
schematics of the 128 × 128 microbolometer array together
with the reference detectors. Gray lines show the current flow
through the array and reference pixels when the row switch
〈0〉 is closed. Vr_pix and Vr_ref are reference voltages for
the array and reference pixels, Rx and Ry are horizontal and
vertical routing resistance values per pixel, and Rz is the routing
resistance per row below a selected row in the vertical routing
structure on the left of the array for both array and reference
pixels. Reference pixels have effectively N times wider vertical
routing lines above the selected row in the routing structure to
match the vertical voltage drops on the upper portion of the
array. An improvement with respect to the previous array [35]
is achieved by using an exact replica of the array row as a ref-
erence row of pixels just above the array pixels, and improving
the vertical routing structure external to the detector area.
To compensate for the horizontal voltage variation, the ref-
erence pixels are placed in a single row above the array pixels.
The electrical property of the reference pixels is identical to
that of the array pixels, with the only difference being in
their thermal conductance values. To reduce any possible self-
heating due to excessively fast addressing of these pixels, they
are connected with metal interconnects on wider oxide support
arms. The corresponding electrical resistance of the reference
pixels is matched by using the same interconnect structure
outside the pixel area on the substrate. Because of the poor
thermal isolation of the reference pixels, they can be consid-
ered to be infrared-blind due to their reduced responsivity by
about three orders of magnitude. The high thermal-conductance
associated with the reference pixels also reduces their thermal
time constant to a very low level, and they can respond to the
self-heating almost immediately. However, due to the increased
thermal conductance value, the self-heating of these detectors
is not as high as the actual detectors, even if they can reach
the steady state very quickly. The disadvantage of having a
short thermal time constant for the reference pixels is that they
cannot be used to compensate for the self-heating occurring
unavoidably for the array pixels. However, this can be solved
by adjusting the current level just prior to the integration in the
circuit level [39].
EMINOGLU et al.: LOW-COST 128 × 128 UNCOOLED INFRARED DETECTOR ARRAY IN CMOS PROCESS 23
Fig. 4. Simplified schematics of the 128 × 128 array with the improved array structure. Gray lines show the current flow through the array and reference pixels
when the row switch 〈0〉 is closed.
To compensate for the vertical voltage variations, the metal
lines in the external vertical routing structure are implemented
in such a way that the vertical voltage drop measured from a
selected row bias voltage is the same both for the reference
and array pixels, which is cancelled by a differential ROC.
Although it is also possible to make the FPA insensitive to
vertical pixel selection, the 128 × 128 FPA is designed so that
the differential reading is compensated both for the horizontal
and vertical voltage variations. The resulting array pixel voltage
(VFPA(m,n)) and reference pixel voltage (VREF(m,n)) in the
FPA are given as
VFPA(m,n) =Vrow(m)−Vpix(m,n)−mI0Ry
−N
K
(K−1−p)I0Rx−KI0Rx
c∑
k=0
(
N
K
−k
)
(1)
VREF(m,n) =Vrow(m)−VREF(n)−mNI0 Ry
N
−N
K
(K−1−p)I0Rx−KI0Rx
c∑
k=0
(
N
K
−k
)
(2)
where, m and n are the row and column of the pixel,
respectively, Vrow is the bias voltage for the selected row, Vpix
and VREF are the voltages of the selected array and reference
pixels, respectively, I0 is the pixel bias current, Rx and Ry are
horizontal and vertical routing resistance values, respectively,
for a single pixel, N is the number of columns and rows in
the FPA (N = 128), K is the number of the parallel readout
channels (K = 32), p is the position index of the pixel in a
selected column group (0 ≤ p ≤ 3), c is the position index of
the corresponding readout channel (0 ≤ c ≤ 31), and Vr_pix
and Vr_ref are the reference bias voltages of the array rows
and reference row, respectively. It should be noted that the total
current carried by the external routing structure is the same on
the left of the array, and the lower portion of the external routing
structure is identical for both array and reference pixels; there-
fore, voltages after row select switches are identical for both
array and reference pixels, denoted by Vrow(m). However, the
current distribution is different in the upper section above the
select switch for a given row, since, the total current inside
the array is divided into as many parallel paths as the number
of parallel readout channels. Corresponding voltage drop in
the upper vertical section is given by the third term in the
above equations. To match the upper vertical voltage drop
in the array and external vertical routing structure, as many
multiple parallel paths as the number of routing channels are
added to the vertical routing structure, so that the product of
the total current and total resistance is kept the same both for
the array and reference pixels. The fourth and fifth terms in the
above equations give the horizontal voltage drop in the array
and reference pixels, respectively, in the nth column, which
corresponds to cth readout channel and pth pixel in the given
channel. Since the pixel row structure for array and reference
pixels are made identical in the design, corresponding terms are
the same for array and refe