vhdl语言四输入与门

用vhdl四输入与门，两种方法2010-11-0122:44碧草cc|分类：其他编程语言|浏览1032次急，谢谢！要过程分享到：检举|2010-11-0218:35提问者采纳第一种方法，程序如下：libraryieee;useieee.std_logic_1164.all;entityand4isport(a,b,c,d:instd_logic;z:outstd_logic);endand4;architecturemediedofand4isbeginz<=(aandb)and(candd);endmedied;第二种方法，程序如下：libraryieee;useieee.std_logic_1164.all;entityand4isport(a,b,c,d:instd_logic;z:outstd_logic);endand4;architecturemediedofand4issignalabcd:std_logic_vector(3downto0);beginabcd<=a&b&c&d;process(abcd)begincaseabcdiswhen"1111"=>Z<='1';whenothers=>z<='0';endcase;endprocess;endmedied;