DM9000_Application_Notes_V100

DM9000 APPLICATION NOTES Preliminary Page 1 Version: DM9000-AP-01 Jul 21, 2003 DM9000 32/16/8-Bit Three-In-One Fast Ethernet Controller Application Notes V1.0 Technical Reference Manual Davicom Semiconductor, Inc DM9000 APPLICATION NOTES Preliminary Page 2 Version: DM9000-AP-01 Jul 21, 2003 1 INTRODUCTION................................................................................................ 6 1.1 General Description ................................................................................................................. 6 2 GENERAL PROCESSOR BUS DESCRIPTION ............................................. 7 2.1 ISA Bus ..................................................................................................................................... 7 2.1.1 Pin Function Table ............................................................................................................ 7 2.1.2 I/O Base Address Decoding............................................................................................... 8 2.1.3 ISA Bus 8/16-Bit Mode and MII Interface Setting............................................................. 9 2.1.4 Command Type .................................................................................................................. 9 2.2 Typical Signal Connection with Processor Bus ...................................................................... 10 2.2.1 Pin Function Table .......................................................................................................... 10 2.2.2 I/O Base Address Decoding..............................................................................................11 2.2.3 Processor Parallel Buse 8/16/32-Bit Mode and MII Interface Setting............................ 12 2.2.4 Command Type ................................................................................................................ 13 3 SYSTEM HARDWARE DESIGN .................................................................... 14 3.1 How to Select DM9000........................................................................................................... 14 3.2 How to Change I/O Base Address .......................................................................................... 14 3.3 Serial EEPROM Operation .................................................................................................... 14 3.3.1 EEPROM Format ............................................................................................................ 15 3.4 GPIO Pins Setting .................................................................................................................. 16 3.5 Timing Analysis ...................................................................................................................... 18 3.5.1 Read Cycle....................................................................................................................... 18 3.5.2 Write Cycle ...................................................................................................................... 18 3.6 Reference Schematic Design .................................................................................................. 19 3.6.1 DM9000 ISA Bus for 8/16-Bit ......................................................................................... 19 3.6.2 DM9000 Host Parallel Bus for 8-Bit............................................................................... 21 3.6.3 DM9000 Host Parallel Bus for 8/16-Bit.......................................................................... 22 3.6.4 DM9000 Host Parallel Bus for 16/32-Bit........................................................................ 23 3.6.5 DM9000 Host Parallel Bus to MII Adapter..................................................................... 24 4 RESET OPERATION AND PHY POWER_DOWN MODE......................... 25 4.1 Hardware Reset ...................................................................................................................... 25 4.1.1 Power On Reset ............................................................................................................... 25 4.1.2 Processor Reset ............................................................................................................... 25 4.2 Software Reset ........................................................................................................................ 27 DM9000 APPLICATION NOTES Preliminary Page 3 Version: DM9000-AP-01 Jul 21, 2003 4.3 PHY Power Down Mode ........................................................................................................ 25 4.3.1 MII Register Setting......................................................................................................... 26 4.3.2 GEPIO0 Setting............................................................................................................... 26 5 HOW TO PROGRAM DM9000 ....................................................................... 27 5.1 Driver Initializing Steps.......................................................................................................... 27 5.2 How to Read/Write DM9000 Register .................................................................................... 28 5.3 How to Read/Write EEPROM Data........................................................................................ 29 5.3.1 Read EEPROM Data..................................................................................................... 29 5.3.2 Write EEPROM Data .................................................................................................... 30 5.4 How to Read/Write PHY Register........................................................................................... 31 5.4.1 Read PHY Register ........................................................................................................ 31 5.4.2 Write PHY Register........................................................................................................ 32 5.5 How to Transmit Packets........................................................................................................ 33 5.5.1 Transmit a Packet .......................................................................................................... 34 5.5.2 Check a Completion Flag.............................................................................................. 35 5.6 How to Receive Packets.......................................................................................................... 35 5.6.1 Receive Interrupt Service Routine ................................................................................. 36 5.6.2 Receive a Packet............................................................................................................ 36 5.6.3 Check a Packet Status and Length................................................................................. 37 5.6.4 Receive a Packet Data................................................................................................... 37 6 DIAGNOSTIC.......................................................................................................... 39 6.1 MAC Address.......................................................................................................................... 39 6.2 DM9000 Register Read/Write Test ......................................................................................... 39 6.3 EEPROM 93C46 Register Test ............................................................................................... 39 6.4 Ethernet Link .......................................................................................................................... 39 6.5 External Loopback Test .......................................................................................................... 40 6.6 Transmitting a Packet............................................................................................................. 40 6.7 Receiving a Packet ................................................................................................................. 40 6.8 System Test.............................................................................................................................. 40 DM9000 APPLICATION NOTES Preliminary Page 4 Version: DM9000-AP-01 Jul 21, 2003 FIGURE 1.1 DM9000 INTERNAL BLOCK DIAGRAM.................................................................. 6 FIGURE 2.1 SIGNAL CONNECTION WITH A PROCESSOR INTERFACING............................. 7 FIGURE 2.2 DM9000 CMD PIN AND ISA BUS ............................................................................ 10 FIGURE 2.3 DM9000 CMD PIN AND PROCESSOR PARALLEL BUS ....................................... 13 FIGURE 3.1 PROCESSOR REGISTER READ TIMING .............................................................. 18 FIGURE 3.2 PROCESSOR REGISTER WRITE TIMING.............................................................. 19 FIGURE 3.3 SCHEMATIC OF ISA BUS FOR 8/16-BITS .............................................................. 20 FIGURE 3.4 SCHEMATIC OF HOST PARALLEL BUS FOR 8-BITS ......................................... 21 FIGURE 3.5 SCHEMATIC OF HOST PARALLEL BUS FOR 8/16-BITS ..................................... 22 FIGURE 3.6 SCHEMATIC OF HOST PARALLEL BUS FOR 16/32-BITS ................................... 23 FIGURE 3.7 SCHEMATIC OF HOST PARALLEL BUS TO MII ADAPTER................................ 24 FIGURE 5.1 PACKET TRANSMITTING BUFFER........................................................................ 33 FIGURE5.2 BLOCK DIAGRAM OF THE PACKETS RECEIVED ............................................... 36 DM9000 APPLICATION NOTES Preliminary Page 5 Version: DM9000-AP-01 Jul 21, 2003 TABLE 2.1 PIN FUNCTION TABLE FOR ISA BUS........................................................................ 8 TABLE 2.2 I/O BASED ADDRESS FOR ISA BUS ......................................................................... 9 TABLE 2.3 PIN FUNCTION TABLE FOR PARALLEL INTERFACE ...........................................11 TABLE 2.4 I/O BASED ADDRESS FOR PARALLEL INTERFACE..............................................11 TABLE 3.1 EEPROM FORMAT...................................................................................................... 15 TBALE 3.2 GENERAL PURPOSE CONTROL REGISTER (GPCR) ........................................... 17 TABLE 3.3 GENERAL PURPOSE REGISTER (GPR) ................................................................... 17 TABLE 3.4 PARAMETERS FOR READ CYCLE........................................................................... 18 TABLE 3.5 PARAMETERS FOR WRITE CYCLE ......................................................................... 19 DM9000 APPLICATION NOTES Preliminary Page 6 Version: DM9000-AP-01 Jul 21, 2003 1 Introduction 1.1 General Description The DM9000 is a fully integrated and cost-effective Fast Ethernet MAC controller with a general processor interface, a 10/100M PHY and 4K dword SRAM (3K-Byte for TX, 13K-Byte for RX). It is designed with low power and high performance process that support 3.3V with 5V tolerant I/O. Besides, the DM9000 supports 8-bit, 16-bit and 32-bit uP interfaces to internal memory accesses for the different processors. The goal of this document is to provide information pertaining to the DM9000 to allow a design engineer to be able to connect the device to any processors architecture. Figure 1.1 DM9000 Internal Block Diagram EEPROM Interface External MII InterfaceLED TX+/- RX+/- MII Management Control & MII Register Autonegotiation Memory Management RX Machine TX Machine MAC MII 100 Base-TX PCS 100 Base-TX transceiver 10 Base-T Tx/Rx PHYceiver Control &Status Registers Internal SRAM Pr oc es so r In te rf ac e DM9000 APPLICATION NOTES Preliminary Page 7 Version: DM9000-AP-01 Jul 21, 2003 2 General Processor Bus Description This section is intended to aid design engineers connecting the DM9000 device to a microprocessor or micro-controller. The discussion will include the pin functional table, and the individual control signals of the DM9000 involved in the connection between the device and an associated microprocessor / micro-controller in detail. Figure 2.1 Signal Connection with a Processor Interfacing 2.1 ISA Bus The DM9000 supports an asynchronous bus interface. The industry standard ISA bus is one of the typical asynchronous buses. 2.1.1 Pin Function Table Note: The pins of ISA interface except SD8, SD9 and IO16 all have a pulled down resistor about 60k ohm internally. SD0-SD31D0-D31 SA4-SA9A4-A9 CMDA2 AEN#nAEN/nCS IOR#nRD IOW#nWR INTINT nIO16 nIOCHRDY/nWAIT PW_RST#Power On Reset RSTRESET X1_25M X2_25M 25MHz Transformer TXO+ TXO- RXI+ RXI- RJ-45 EED0(65) WAKEUP(79) Strap pin for data width (see data sheet 5.3) EECS(67) strap pin for LED mode (see data sheet 5.3) MII MII Interface 93C46 nIO16# IOWAIT# DM9000DM9000DM9000DM9000 DM9000 APPLICATION NOTES Preliminary Page 8 Version: DM9000-AP-01 Jul 21, 2003 ISA Bus Signal DM9000 Signal Pin No. I/O Description IORC# IOR# 1 I ISA Read Command The default is low active. The polarity can be controlled via EEPROM setting. IOWC# IOW# 2 I ISA Write Command The default is low active. The polarity can be controlled via EEPROM setting. AEN AEN# 3 I Address Enable A low active signal is used to select the DM9000. CHRDY IOWAIT 4 O ISA Command Ready This ISA signal is driven low to insert the wait cycles to current host read/write command. RESET RST 14 I Hardware Reset Command When this pin is asserted high, The DM9000 performs an internal system reset. SD0 ~ 15 SD0 ~ 15 6,7,8,9, 10,11,12, 13,89, 88,87,86, 85,84, 83,82 I/O ISA Data Bus 0 ~ 15 SA4 ~ 9 SA4 ~ 9 93,94,95, 96,97,98 I ISA Address Bus 4 ~ 9 These pins are used to select the DM9000 I/O base address 0x300 ~ 0x370. SA2 CMD 92 I Command Type When an input signal is low, the access of the command cycle is ADDR_PORT. The DM9000 device address port = 0x300 ~ 0x370 + 0x0 When an input signal is high, the access of the command cycle is DATA_PORT. The DM9000 device data port = 0x300 ~ 0x370 + 0x4 IO16# IO16 91 O ISA Word Command Indication This pin is used to indicate the access of internal memory is word or dword. The default is low active and open-collected which can be programmed by the EEPROM setting. IRQn INT 100 O ISA Interrupt Request The default is high active. Its polarity can be modified by EEPROM setting or strap pin MDC. Table 2.1 Pin Function Table for ISA Bus 2.1.2 I/O Base Address Decoding Example The I/O base address for ISA bus can be programmed from 300h to 370h. The default value of I/O base address is 300h. A9 A8 A7 A6 A5 A4 I/O basedaddress 1 1 0 0 0 0 300h 1 1 0 0 0 1 310h 1 1 0 0 1 0 320h 1 1 0 0 1 1 330h DM9000 APPLICATION NOTES Preliminary Page 9 Version: DM9000-AP-01 Jul 21, 2003 1 1 0 1 0 0 340h 1 1 0 1 0 1 350h 1 1 0 1 1 0 360h 1 1 0 1 1 1 370h Table 2.2 I/O Based Address for ISA Bus The chart below shows the decoding of I/O based address 300h: A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 2.1.3 ISA Bus 8/16-Bit Mode and MII Interface Setting The DM9000 provides two I/O modes: byte/word of memory commands for ISA bus to read/write the data from hardware DATA_PORT. The decoder table is shown as follows. WAKEUP EEDO Data width 0 0 16-bit 0 1 32-bit (Not supported for ISA interface) 1 0 8-bit 1 1 Reserved The EEDO pin is used as a strap pin. It combines with another strap pin WAKEUP, and these two pins can be used to set the data width of the internal memory access. The logic 1 means the strap pin is pulled high. In ISA bus interface, the 32-bit I/O mode is not supported and the system designer can use the SD[16:31] pins as the MII interface function. The interrupt status register ISR (reg_FEh) can help us to check the setting of I/O mode: ISR reg_FEh IOMODE Bit 7 6 0 0 16-bit mode 0 1 32-bit mode (Not supported for ISA interface) 1 0 8-bit mode 1 1 Reserved 2.1.4 Command Type DM9000 APPLICATION NOTES Preliminary Page 10 Version: DM9000-AP-01 Jul 21, 2003 The CMD pin is an input pin and used to set the command type. When the CMD pin detected the input signal is low, the access of this command cycle is for ADDR_PORT. When input is high, the access of this command cycle is for DATA_PORT. The following diagram is an example for the DM9000 CMD pin connecting to ISA bus. Figure 2.2 DM9000 CMD Pin and ISA Bus. 2.2 Typical Signal Connection with Processor Bus The DM9000 can support many general processor parallel bus interfaces such as 8051, ARM, MIPS… It is designed to facilitate the implementation of Fast Ethernet connectivity solutions for embedded systems. 2.2.1 Pin Function Table Note: The pins of processor parallel interface except SD8, SD9 and IO16 all have a pulled down resistor about 60k ohm internally. Processor Bus Signal DM9000 Signal Pin No. I/O Description nRD IOR# 1 I Processor Read Command This pin is low