全减器(eda技术实用教程第四版)

11电本3班  黄斯文  学号：1101902310 编译程序如下： 半减器程序如下： library ieee; use ieee.std_logic_1164.all; entity h_suber is port(a,b : in std_logic; diff,s_out : out std_logic); end entity h_suber; architecture banjian of h_suber is signal bj: std_logic_vector(1 downto 0); begin bj <= a&b; process(bj)  begin case bj is when "00" => diff<='0';s_out<='0'; when "01" => diff<='1';s_out<='1'; when "10" => diff<='1';s_out<='0'; when "11" => diff<='0';s_out<='0'; when others => null; end case; end process; end architecture banjian; 或门程序如下： library ieee; use ieee.std_logic_1164.all; entity or2a is port(a,b : in std_logic; c : out std_logic); end entity or2a; architecture one of or2a is begin c<= a or b; end architecture one; 全减器程序如下： library ieee; use ieee.std_logic_1164.all; entity f_suber is port(x,y,sub_in : in std_logic; sub_out,diffr : out std_logic); end entity f_suber;    architecture fd1 of f_suber is component h_suber port(a,b : in std_logic; diff,s_out : out std_logic); end component; component or2a port(a,b : in std_logic; c : out std_logic); end component; signal d,e,f :std_logic; begin u1 : h_suber port map(a=>x, b=>y, diff=>e, s_out=>d); u2 : h_suber port map(a=>e, b=>sub_in, diff=>diffr, s_out=>f); u3 : or2a    port map(a=>d, b=>f, c=>sub_out); end architecture fd1; 编译图形如下：