DARPA-BAA-10-77_CLASIC_Final_For_Posting_31Aug10

1 Broad Agency Announcement Cognitive radio Low-energy signal Analysis Sensor ICs (CLASIC) Microsystems Technology Office DARPA-BAA-10-77 8/31/2010 2 Table of Contents Part I: Overview Information ...........................................................................................3 Part II: Full Text of Announcement ...................................................................................4 Sec. 1: FUNDING OPPORTUNITY DESCRIPTION .........................................4 Sec. 2: AWARD INFORMATION .....................................................................11 Sec. 3: ELIGIBILITY INFORMATION .............................................................12 A. Eligible Applicants...............................................................................12 B. Cost Sharing / Matching ......................................................................13 C. Other Eligibility Criteria ......................................................................14 Sec. 4: APPLICATION AND SUBMISSION INFORMATION .......................14 A. Address to Request Application Package ............................................14 B. Content and Form of Application Submission .....................................14 1. Security and Proprietary Issues .......................................................14 2. Abstract and Proposal Information .................................................16 3. Proposal Abstract Format ................................................................18 4. Full Proposal Format .......................................................................19 5. Volume I: Technical and Management Proposal ...........................19 6. Volume II: Cost Proposal ...............................................................22 7. Submission Dates and Times ..........................................................25 8. Intergovernmental Review ..............................................................25 9. Funding Restrictions .......................................................................25 Sec. 5: APPLICATION REVIEW INFORMATION .........................................25 A. Evaluation Criteria ...............................................................................25 B. Review and Selection Process .............................................................27 Sec. 6: AWARD ADMINISTRATION INFORMATION .................................28 A. Award Notices .....................................................................................28 B. Administrative and National Policy Requirements ..............................28 1. Meeting and Travel Requirements ..................................................28 2. Human Use ......................................................................................28 3. Animal Use .....................................................................................29 4. Publication Approval ......................................................................30 5. Export Control .................................................................................31 6. Subcontracting ................................................................................32 7. Electronic and Information Technology .........................................33 8. Employment Eligibility Verification ..............................................33 C. Reporting .............................................................................................33 D. Electronic Systems ...............................................................................33 Sec. 7: AGENCY CONTACTS ..........................................................................34 Sec. 8: OTHER INFORMATION .......................................................................34 A. Intellectual Property .............................................................................34 B. Other Transactions..............................................................................37 Sec. 9: Attachment 1. ..........................................................................................39 3 Part I: Overview Information • Federal Agency Name – Defense Advanced Research Projects Agency (DARPA), Microsystems Technology Office (MTO) • Funding Opportunity Title – Cognitive Radio Low-energy signal Analysis Sensor ICs (CLASIC) • Announcement Type – Initial Announcement • Funding Opportunity Number – DARPA-BAA-10-77 • Catalog of Federal Domestic Assistance Numbers (CFDA) – 12.910 Research and Technology Development • Dates o Posting Date: August 31, 2010 o Proposal Abstract Due Date: 4:00:00 p.m. Eastern Time, October 1, 2010 o Proposal Due Date: 4:00:00 p.m. Eastern Time, December 10, 2010 • Concise description of the funding opportunity - The goal of CLASIC is to enable monolithic, high performance, ultra high energy efficiency, signal recognition integrated circuits (ICs) for next-generation military microsystems in areas such as cognitive communications, radar and electronic warfare. • Anticipated individual awards – Multiple awards are anticipated. • Types of instruments that may be awarded - Procurement contract, grant, cooperative agreement or other transaction. • Any cost sharing requirements - None • Agency contact - o Dr. Sanjay Raman The BAA Coordinator for this effort can be reached at, fax: (703) 248- 8070, electronic mail: DARPA-BAA-10-77@darpa.mil. DARPA/MTO ATTN: DARPA-BAA-10-77 3701 North Fairfax Drive Arlington, VA 22203-1714 4 Part II: Full Text of Announcement Sec. 1: FUNDING OPPORTUNITY DESCRIPTION The Defense Advanced Research Projects Agency often selects its research efforts through the Broad Agency Announcement (BAA) process. The BAA will appear first on the FedBizOpps website, http://www.fedbizopps.gov/, and Grants.gov website at http://www.grants.gov/. The following information is for those wishing to respond to the BAA. DARPA is soliciting innovative research and development (R&D) proposals in the area of Cognitive radio Low-energy signal Analysis Sensor Integrated Circuits (CLASIC), a thrust within the DARPA Adaptive RF Technology (ART) program. The goal of CLASIC is to enable monolithic, high performance, ultra high energy efficiency, signal recognition integrated circuits (ICs) for next-generation military microsystems in areas such as cognitive communications, radar and electronic warfare. A cognitive system is aware of its external environment and internal states, such as the electromagnetic/signal environment in the case of cognitive RF systems, and can autonomously decide and adjust its behavior to optimize quality of service or other operational objectives. Signal parameters of interest include modulation schemes, signal constellations, multiple access or hopping schemes, channel utilization and demodulated symbols.  DARPA envisions that this goal will be achieved by investigating and developing novel RF, analog and mixed- signal integrated circuit architectures and design techniques. The scaling of integrated circuit technologies has resulted in transistor unity current gain cutoff frequencies (fT) surpassing 400 GHz. In combination with specialized processor architectures, this has resulted in digital processor speeds approaching 100,000 MIPS and processing efficiencies surpassing 2 MIPS/mW with silicon-based integrated circuits. However, the waveform processing requirements of emerging military cognitive radio systems have resulted in ADC, DSP and algorithm complexity levels pushing beyond what is realizable in low-power hand-held form factors. Therefore, a major challenge in communications integrated circuit design is achieving ultra-high levels of performance and energy efficiency for signal (waveform) recognition processing (i.e., high performance cognitive radio signal sensor on a chip). Significant technical obstacles to be overcome in CLASIC include the development of energy-efficient, analog and/or mixed-signal processing techniques for separating and analyzing mixtures of complex signals. These techniques may require: blind source separation using RF adaptive recursive and transversal filters; analog implementations of fast Fourier and wavelet transforms; and efficient implementations of signal feature extraction and classification algorithms (e.g., cyclostationary signal feature extractors and classifiers, etc.) in analog/neuromorphic processing blocks. Proposed research should investigate innovative approaches that enable revolutionary advances in integrated circuit design, architectures or algorithms. Specifically excluded is research that primarily results in evolutionary improvements to the existing state of practice. 5 Background Over the past several years, DARPA has initiated programs addressing a number of important technical challenges in RF/mixed-signal microelectronics, including design of silicon CMOS/silicon-germanium BiCMOS RF/microwave integrated circuits; linearization; self-healing integrated circuits to combat variability, environment and ageing; and reducing power and thermal dissipation. Meanwhile, in the Cognitive Radio space, a number of recent DARPA programs such as Analog Spectral Processors (ASP), Wolfpack, NeXt-Generation Communications (XG) and Chip-Scale Mechanical Spectrum Analyzers (CSSA) have implemented energy detection-based sensing functionalities for characterization of spectral occupancy. With CLASIC, DARPA seeks to develop new technologies that can realize blind waveform sensing functions of cognitive military radios with unprecedented low energy performance. Waveform parameters to be sensed include modulation schemes, signal constellations, multiple access or hopping schemes, and channel utilization. In addition, DARPA is also interested in approaches that can provide demodulated symbol streams. Traditionally, signal recognition functions have been implemented in digital electronics, including FPGAs and DSPs. Figure 1 shows the architecture of a conventional signal recognition system, where RF signals are down-converted, digitized and correlated against a library of known signals in order to determine waveform parameters. In commercial wireless communications systems, where a known set of established communications standards are involved, this process can be done quite efficiently. However, in military systems, excessive amounts of energy are typically expended in the waveform correlation process due to the potentially large numbers of waveforms of interest, as well as significant power for the A/D conversion process in the case of wide analysis bandwidths of interest. Alternative classification approaches, such as those based on cyclostationary statistic computation and analysis, likewise require large amounts of energy because of the high computational complexity of the underlying algorithms. Figure 1. A conventional “digitize, search, correlate” signal recognition approach While the technological advances in digital electronics have enabled increasing processor power efficiencies in MIPS/mW, the high computational requirements in MIPS for 6 advanced waveform recognition functions result in physically large, power hungry processing systems. Figure 2 shows this trend as related to processing requirements of several waveforms of interest and an estimated processing requirement for blind source separation. Figure 2. Processing requirements of emerging cognitive radio techniques outpace increasing power efficiencies of General Purpose Processors (GPP), Field- Programmable Gate Arrays (FPGAs), Digital Signal Processors (DSPs) and Graphics Processing Units (GPUs). Efficient signal processing techniques for separating and decoding mixtures of complex signals are needed. DARPA envisions that, in combination with architectural innovations, analog signal processing techniques may provide significant improvements in effective MIPS/mW with respect to state-of-art DSP/FPGA techniques; however, other approaches that can reach the energy consumption goals are of interest as well. Figure 3 shows the expected improvement over the state-of-art as applicable to recognition of an example narrowband BPSK signal with SNR of -8 dB in a 500 MHz bandwidth. For the SOA signal recognizer and other possible digital processors, use of an 11.7-ENOB COTS analog-to-digital converter was assumed. 100 mW 1 W 10 W 100 W 1 kW 0.00001 0.0001 0.001 0.01 0.1 1 10 0.1 1 10 100 1000 10000 100000 1000000 M IP S  /  m W MIPS Single Core GPP Multi Core GPP FPGA DSP GPU GSM SINCGARS WNW OFDM Blind Source Separation of 25 10 Mbps Signals 7 Figure 3: CLASIC goal; recognition of an example narrowband BPSK signal with SNR of -8 dB in a 500 MHz analysis bandwidth1. Technical Areas DARPA seeks innovative proposals for research and development (R&D) of technologies that will lead to revolutionary decreases in energy consumption needed to separate and analyze arbitrary mixtures of signals. Figure 4 shows a conceptual block diagram of a CLASIC demonstration radio platform, including an integrated, highly energy efficient signal analyzer. Symbol estimation, although of interest, is not a required functional component of the processor. It is expected that proposers will need to address both technical areas described below. Proposers should include in their proposal a radio front- end architecture that will couple to their CLASIC processor or a teaming strategy that will enable field demonstration of the processor in the final phase of the thrust. Specifically excluded is research and development that primarily results in evolutionary improvements to the existing state of practice, regardless of the chosen analyzer architecture or approach. 1 The curves for probability of correct classification vs. energy are derived from results presented in Spooner et al, Automatic Radio-Frequency Environment Analysis, , IEEE 2000 30 40 50 60 70 80 90 100 0.01 0.1 1 10 100 1000 10000 Pr ob ab ili ty o f C or re ct C la ss ifi ca tio n [% ] Energy [J] 400x More Energy Efficient Goal = 95 % SOA Signal Recognizer ER = 700 Joules CLASIC ER = 0.25 Joules SOA COTS Digital Processor ER > 100 Joules 8 Figure 4: Conceptual block diagram of the CLASIC Processor platform. The technical areas of interest are as follows: Technical Area One: Low-Energy Blind Signal Separation and Parameter Extraction The goal of this area is to demonstrate (in fabricated hardware) the ability to accurately separate “mixtures” of signals (waveforms) present in the analysis bandwidth with low energy performance to reduce overall power requirements for next-generation cognitive radio applications. The signal sensor should have the capability to separate multiple, emitters with arbitrary signal parameters such as carrier frequency, symbol rate, modulation type, multiple access scheme, etc., including overlapping (co-channel) signals. Signal bandwidths of interest are both narrowband (e.g., 12.5 kHz) to wideband (up to 500 MHz). Further, the signal sensor should have the capability to accurately (with high probability of correct classification and low probability of false classification) extract parameters from multiple emitters with randomly chosen emitter parameters such as carrier frequency, symbol rate, modulation type, multiple access scheme, etc., including overlapping (co-channel) signals. Table 1 describes example parameters of interest; however, this list should not be construed as exhaustive and proposals will be evaluated on their ability to extract as many different parameter combinations as possible. Table 1. Example Signal Parameters of Interest Signal Parameter Examples Modulation Scheme FM, AM, USB, LSB, CW, ASK, FSK, PSK, CPM, QAM and OFDM Digital Modulation Constellation Size 2, 4, 8, 16, 32, 64, 128, 256 Spread Spectrum Technique Frequency hopping and direct sequence Multiple Access Scheme CDMA, TDMA and FDMA Signal Mixture Measurements M1 M2 Mk S1 S2 Sm P1 P2 Pn Parameters Of Separated Signals B lin d So ur ce Se pa ra tio n Sy m bo l Es tim at io n Feature Extraction / Signal Recognition CLASIC Signal Mixture Symbols of Selected Separated Signals LNA LO 9 CLASIC technology should be able to identify signal parameters for waveforms that are not known a priori; however, example military waveforms of interest include SINCGARS, SRW, WNW, HAVE QUICK, LINK-11, EPLRS, DAMA SATCOM, and DSCS, among others. Commercial waveforms of interest include GSM, UMTS, LTE, WiMAX, 802.11 standards, FM & AM, TV, Bluetooth, etc. Limitations in the relative signal strengths of signals in the mixture should be studied and evaluated. Methods that can classify signals in the negative SNR regime are also of interest to DARPA. Technical Area Two: Integration with RF Front-End Proposers should include in their proposal a radio front-end architecture that will couple to their CLASIC processor, or a teaming strategy that will enable field demonstration of the processor in the final phase of the thrust. It should also be noted that approaches that optimize the overall energy consumption by co-design of the RF front-end with the CLASIC processor circuitry are also considered within the scope of this solicitation. However, in cases where innovative co-design of the RF front-end and the signal recognition processing is employed, the proposers should clearly and credibly explain how efficiencies gained in the RF front-end are consistent with the performance goals of CLASIC discussed below. Another area that is not explicitly identified as a separate technical area, but is integral to all the above technical areas of interest, is the test and measurement (T&M) techniques required to evaluate performance of the developed integrated circuits. These will likely include capabilities such as generation of numerous signals of different types, various higher order modulations, etc. Therefore, proposers should provide detailed information on how they plan to characterize the circuits developed under CLASIC. CLASIC Program Structure DARPA anticipates that in order to achieve the end goal of signal identification as a sensing function for low-energy waveform-agile cognitive radios, CLASIC performers will need to structure their efforts as described below. DARPA also anticipates that this program will be conducted over approximately four years; however, the length of each program phase should be proposed based on the approach and the level of effort needed. The aggressiveness of the proposed schedule will be considered in the evaluation of the proposals. Intermediate technical milestones that demonstrate progress over the proposed duration should be included in the proposal. These milestones must define a credible trajectory towards achieving the program goals described below. Signal recognition processor design and simulation: Performers are expected to focus on algorithm development and optimization, processor architecture definition and behavioral simulation, design and simulation of constituent function blocks, and transistor-level simulation of overall processor design including parasitics and variability. The performers should clearly and credibly demonstrate that their design will be able to meet the end-of-thrust goals (described in the next section). A Critical Design Review (CDR) of performers' designs will be conducted by a government review team at the end of each 10