EDA技术与VHDL 第三版 (黄继业 著) 第3章习题 答案

第3章习 第3章习题 3-1．画出与下列实体描述对应的原理图符号文件 ENTITY buf3s IS PORT ( input : IN STD_LOGIC; Enable : IN STD_LOGIC; Output : OUT STD_LOGIC); END buf3s; Buf3s Input output Enable ENTITY mux21 IS PORT (in0, in1, sel : IN STD_LOGIC; Output : OUT STD_LOGIC); END mux21; mux21 in0 in1 output sel 3-2．四选一多路选择器 （1）用CASE语句： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS PORT ( a,b,c,d: IN STD_LOGIC; s1,s0: IN STD_LOGIC; y: OUT STD_LOGIC); END mux41a; ARCHITECTURE one OF mux41a IS SIGNAL s10: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN s10<=s1&s0; PROCESS (s10) BEGIN CASE s10 IS WHEN "00" => y<=a; WHEN "01" => y<=b; WHEN "10" => y<=c; WHEN "11" => y<=d; WHEN OTHERS => NULL; END CASE; END PROCESS; END ARCHITECTURE one; 用IF THEN语句： …… PROCESS (s10) BEGIN IF s10 = “00” THEN y <= a; ELSIF s10 = “01” THEN y <= b; ELSIF s10 = “10” THEN y <= c; ELSE y <= d; END IF; END PROCESS; …… 3-3．双2选1多路选择器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY muxk IS PORT ( a1,a2,a3: IN STD_LOGIC; s0,s1: IN STD_LOGIC; outy: OUT STD_LOGIC); END muxk; ARCHITECTURE one OF muxk IS SIGNAL tmp: STD_LOGIC; BEGIN pro1: PROCESS (s0) BEGIN CASE s0 IS WHEN '0'=> tmp<=a2; WHEN '1'=> tmp<=a3; WHEN OTHERS => NULL; END CASE; END PROCESS pro1; pro2: PROCESS (s1) BEGIN CASE s1 IS WHEN '0'=> outy<=a1; WHEN '1'=> outy<=tmp; WHEN OTHERS => NULL; END CASE; END PROCESS pro2; END ARCHITECTURE one; 3-4． 1位全减器 （1） 半减器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS PORT( x, y: IN STD_LOGIC; diffr, s_out: OUT STD_LOGIC); END h_suber; ARCHITECTURE one OF h_suber IS SIGNAL xy: STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN xy <= X & y; PROCESS ( xy ) BEGIN CASE xy IS WHEN "00" => s_out <= '0'; diffr <= '0'; WHEN "01" => s_out <= '1'; diffr <= '1'; WHEN "10" => s_out <= '0'; diffr <= '1'; WHEN "11" => s_out <= '0'; diffr <= '0'; WHEN OTHERS => NULL; END CASE; END PROCESS; END one; （2）二输入或门 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END or2a; ARCHITECTURE one OF or2a IS BEGIN c <= a OR b; END one; （3）1位全减器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS PORT ( xin, yin, sub_in: IN STD_LOGIC; diff_out, sub_out: OUT STD_LOGIC); END f_suber; ARCHITECTURE one OF f_suber IS COMPONENT h_suber PORT( x, y: IN STD_LOGIC; diffr, s_out: OUT STD_LOGIC); END COMPONENT; COMPONENT or2a PORT( a, b: IN STD_LOGIC; c: OUT STD_LOGIC); END COMPONENT; SIGNAL d, e, f : STD_LOGIC; BEGIN u1: h_suber PORT MAP ( x => xin, y => yin, diffr => d, s_out => e); u2: h_suber PORT MAP ( x => d, y => sub_in, diffr => diff_out, s_out => f); u3: or2a PORT MAP ( a => f, b => e, c => sub_out); END one; （4）8位全减器 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber8 IS PORT ( x, y: IN STD_LOGIC_VECTOR(7 DOWNTO 0); diff: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); subi: IN STD_LOGIC; subo: OUT STD_LOGIC); END ENTITY suber8; ARCHITECTURE one OF suber8 IS COMPONENT f_suber PORT ( xin, yin, sub_in: IN STD_LOGIC; diff_out, sub_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a, b, c, d, e, f, g: STD_LOGIC; BEGIN u0: f_suber PORT MAP (sub_in=>subi, sub_out=>a, xin=>x(0), yin=>y(0), diff_out=>diff(0)); u1: f_suber PORT MAP (sub_in=>a, sub_out=>b, xin=>x(1), yin=>y(1), diff_out=>diff(1)); u2: f_suber PORT MAP (sub_in=>b, sub_out=>c, xin=>x(2), yin=>y(2), diff_out=>diff(2)); u3: f_suber PORT MAP (sub_in=>c, sub_out=>d, xin=>x(3), yin=>y(3), diff_out=>diff(3)); u4: f_suber PORT MAP (sub_in=>d, sub_out=>e, xin=>x(4), yin=>y(4), diff_out=>diff(4)); u5: f_suber PORT MAP (sub_in=>e, sub_out=>f, xin=>x(5), yin=>y(5), diff_out=>diff(5)); u6: f_suber PORT MAP (sub_in=>f, sub_out=>g, xin=>x(6), yin=>y(6), diff_out=>diff(6)); u7: f_suber PORT MAP (sub_in=>g, sub_out=>subo, xin=>x(7), yin=>y(7), diff_out=>diff(7)); END ARCHITECTURE one; 3-5．含D触发器的时序电路 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY dff3_4 IS PORT ( cl, clk0: IN STD_LOGIC; out1: OUT STD_LOGIC); END dff3_4; ARCHITECTURE one OF dff3_4 IS SIGNAL d, q: STD_LOGIC; BEGIN PROCESS (clk0) BEGIN IF clk0'EVENT AND clk0='1' THEN q<=d; END IF; END PROCESS; d <= NOT (cl OR q); out1 <= NOT q; END ARCHITECTURE one; 3-6． LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MX3256 IS PORT ( INA, INB, INC, INCK : IN STD_LOGIC; E, OUT1 : OUT STD_LOGIC); END ENTITY MX3256; ARCHITECTURE one OF MX3256 IS COMPONENT LK35 PORT ( A1, A2, CLK: IN STD_LOGIC; Q1, Q2: OUT STD_LOGIC); END COMPONENT; COMPONENT DFF1 PORT ( D, C, CLK: IN STD_LOGIC; Q: OUT STD_LOGIC); END COMPONENT; COMPONENT MUX21A PORT ( A, B, S: IN STD_LOGIC; C : OUT STD_LOGIC); END COMPONENT; SIGNAL aa, bb, cc, dd: STD_LOGIC; --Q1->B: aa; Q2->A1/D/S: bb; A2->Q: cc; Q1->A: dd BEGIN u1: LK35 PORT MAP (A1=>INA, A2=>INB, CLK=>INCK, Q1=>aa, Q2=>bb); u2: LK35 PORT MAP (A1=>bb, A2=>cc, CLK=>INCK, Q1=>dd, Q2=>OUT1); u3: DFF1 PORT MAP (D=>bb, CLK=>INCK, C=>INC, Q=>cc); u4: MUX21A PORT MAP (B=>aa, A=>dd, S=>bb, C=>E); END ARCHITECTURE one; 3-7. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT16_up_down IS PORT (CLK,RST,EN,up_down : IN STD_LOGIC; CQ : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); COUT : OUT STD_LOGIC ); END CNT16_up_down; ARCHITECTURE behav OF CNT16_up_down IS BEGIN PROCESS(CLK, RST, EN) VARIABLE CQI : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF RST = '1' THEN CQI := (OTHERS =>'0') ; ELSIF CLK'EVENT AND CLK='1' THEN IF EN = '1' THEN IF UP_DOWN = '1' THEN CQI := CQI + 1; ELSIF UP_DOWN = '0' THEN CQI := CQI - 1; END IF; END IF; END IF; IF CQI = "1111111111111111" THEN COUT <= '1'; ELSE COUT <= '0'; END IF; CQ <= CQI; END PROCESS; END behav; 3.13 改错 程序1 Signal A, EN: std_logic; Process( A,EN) Variable B : std_logic; Begin If EN = 1 then B <= A; end if; End process; 程序2 Architecture one of sample is Variable a, b, c : integer; Begin C <= a + b; end; 程序3 Library ieee; Use ieee.std_logic_1164.all; Entity mux21 is Port ( a, b :in std_logic; Sel : in std_logic; c: out std_logic;); End sam2; Architecture one os mux21 is Begin If sel = ‘0’ then c := a; Else c := b; End if; End two;