基于黑金EP4CE15F17C8流水灯实验

module shift_led( input wire clk,            //时钟信号50MHz input wire rst_n,            //复位信号低电平有效 output wire [3:0]led        //4个LED灯，高电平的时候点亮 ); //-------------------------------------------- parameter cnt_400ms = (25'd20000_000 - 1);  reg [24:0]cnt; reg cnt_400ms_flag; reg [3:0]led_r; wire shift_flag;                always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt <= 'd0; else if(cnt_400ms_flag == 1'b1) cnt <= 'd0; else cnt <= cnt + 1'b1; end always @(posedge clk or negedge rst_n) begin if(!rst_n) cnt_400ms_flag <= 1'b0; else if(cnt == (cnt_400ms - 1)) cnt_400ms_flag <= 1'b1;            //每400ms拉高cnt_400ms_flag一个时钟周期高电平 else cnt_400ms_flag <= 1'b0; end assign shift_flag = cnt_400ms_flag; always @(posedge clk or negedge rst_n) begin if(!rst_n) led_r <= 4'b0001; else if(shift_flag == 1'b1)          led_r <= {led_r[2:0],led_r[3]}; end assign led = led_r; endmodule