A LOW–POWER LOW–VOLTAGE BANDGAP REFERENCE IN CMOS

A LOW–POWER LOW–VOLTAGE BANDGAP REFERENCE IN CMOS Na Sun and Robert Sobot Department of Electrical and Computer Engineering The University of Western Ontario London ON, Canada N6A 5B9 ABSTRACT A low–voltage low–power bandgap voltage reference in 90nm CMOS is designed and simulated. The overall bandgap ar- chitecture is optimized to achieve high accuracy temperature and power supply independent voltage reference. It consists of the bandgap core circuit, op–amp, start–up circuit and out- put stage. The bandgap reference circuit provides reference voltage of 584.7mV ± 0.8mV with 1.2V ± 10% power sup- ply and over −40◦C to 125◦C temperature ranges simultane- ously. The total layout area including dummy structures is 100µm× 85µm. Index Terms— Bandgap Voltage Reference, analog IC, Low–Voltage, Low–Power, Op–Amp, Start–Up Circuit, Out- put Stage 1. INTRODUCTION As the CMOS technology has developed rapidly during the past several decades and has brought us into a new era of high integration and ultra–low power consumption with the power supply voltage levels scaled down, the need for lower than the conventional bandgap voltage reference of 1.205V was cre- ated. Hence, it is critical to develop low–power consumption bandgap references working under low–voltage supply that is compatible with the other modern circuit blocks. Since the first bandgap reference circuit based on Bipo- lar Junction Transistor (BJT) was introduced [1], the bandgap voltage reference circuit has been continuously improved in many aspects. A number of researchers are contributing new solutions based on the concept of using a fraction of the orig- inal bandgap voltage level [2, 3, 4] and for low–power supply voltage conditions [5, 6, 7]. In this paper, design and simulation of a high accuracy bandgap voltage reference circuit working over 0.9V to 1.4V power supply and−40◦C to 125◦C temperature range in 90nm CMOS technology are presented. The rest of the paper is or- ganized as follows. In Section 2 the basic concepts of build- ing a bandgap reference are outlined. In Section 3, details of the proposed bandgap voltage reference circuit design are This work was supported by NSERC. 0.4 0.5 0.6 0.7 0.8 0.9 1 -150 -100 -50 0 50 100 150 V B E(V ) Temperature(C) IC=0.10uA IC=0.17uA IC=0.28uA IC=0.46uA IC=0.77uA IC=1.30uA IC=2.15uA IC=3.59uA IC=6.00uA IC=10.0uA Fig. 1. Simulated base–emitter voltage VBE dependance vs. the biasing current IC and temperature. presented. In Section 4, a simulated characterization results are provided for the bandgap circuit as well as the composing sub–blocks. The concluding remarks are given in Section 5. 2. TEMPERATURE INDEPENDENT REFERENCE A typical BJT’s base–emitter voltage VBE has a negative tem- perature coefficient (TC), Fig. 1, and it is function of both temperature and the biasing current IC . This particular prop- erty, the negative TC, of the VBE voltage is not explicitly captured in the conventional approximated equation VBE = k/qT ln(Ic/Is), because temperature dependance of the satu- ration current Is is much stronger and more complicated. In addition, it should be noted that the TC itself is also function of the collector current IC . It can be shown that base–emitter voltage VBE depen- dance upon temperature T and the collector current IC is some- what more accurately captured by the following equation: VBE(IC , T ) = (a1 ln IC + a2)T + a3 (1) where coefficients a1, a2, a3 are technology dependent con- stants that can be determined by simulation. Obviously, con- Fig. 2. Circuit diagram of bandgap voltage generator. stant a3 is the traditional 1.205V bandgap voltage, while ex- pression (a1 ln IC + a2)T is the temperature coefficient of VBE that includes dependance upon the collector current IC . While a single base–emitter voltage VBE exhibits nega- tive TC, difference of two base–emitter voltages∆VBE , under condition that there are two different current densities used, exhibits positive TC. Hence, it is possible to deliver propor- tional to absolute temperature (PTAT) voltage that has posi- tive TC [8]. Linear combination of these two voltages, there- fore, may result in voltage generator with zero temperature coefficient, i.e.: VREF = α1VBE + α2∆VBE = α1VBE + α2 (VT lnn) (2) where α1 and α2 are design constants and n is the ratio be- tween the two current densities. 3. CIRCUIT DESIGN Temperature independent bandgap voltage lower then 1.205V can be realized by using a fraction of the original bandgap voltage, specifically, its current terms [3]. Schematic diagram of bandgap voltage generator, Fig. 2, shows the low–voltage bandgap core, the output stage and start-up node. In this configuration, the current through R0 has positive TC, while the voltage value across R1 and R2 equals to the base–emitter voltage of the diode connected BJT transistor Q1. The current through M2 (also M1, because I1 = I2) is temperature independent: I1 = I2 = VBE R2 + VT lnN R0 = 1 R2 (VBE + R2 R0 VT lnN) (3) Value of current I3 may vary slightly, following variations of the transistor M3 size and the load impedance. The output reference voltage across the capacitive load CL is VREF = I3RL = kI1RL (4) where k = W3/W1 is the M3,1 transistor gate width ratio, and RL is determined by the loading transistor ML1,2 of the output stage. Fig. 3. Circuit diagram of two stage op–amp. Table 1. Sensitivity of op–amp’s voltage VOUT . Parameter Case 1 Case 2 (W/L)09 1.6µm/0.8µm 2µm/1µm m 50 10 VGS − Vth −10.7mV −106.9mV ID 27.73µA 21.75µA ∆ID(VDD ± 10%) ±20nA −44nA +24nA Vout 812mV 517.5mV ∆Vout(VDD ± 10%) −17.74mV +0.3mV +7.97mV +0.9mV Sensitivity to power supply variation: Two study cases pre- sented in Table 1 demonstrate influence of gate–source volt- age VGS of MO9 transistor on power supply variation sen- sitivity. The results imply that larger MOS transistor size is beneficial. In order to reduce circuit sensitivity to the nominal ±10% power supply disturbance, drain currents ID1,2 should be kept as stable as possible. However, a three–way trade-off between power consumption, gate–source voltage VGS and MOS size (W/L) must be very carefully balanced. Op–Amp Circuit: Figure 3 shows circuit diagram of a clas- sical two stage op–amp implementation that is used in this project. The first stage is a differential stage followed by the second stage composed of transistors Mo6 to Mo9. Transis- tors Mo6 and Mo7 act as the level shifter while Mo8 and Mo9 act as a class AB push–pull output [9]. The VBE voltage of Q1,2 is set to approximately 695mV at room temperature. Hence, the input common–mode volt- age of the op–map is set be in the 650mV ∼ 750mV range. The op–amp is optimized to control the bandgap’s feedback loop and it needs to have gain of more then 40dB, Fig. 4. The Biasing Circuit: Sub–circuit consisting of M15,16 and RB serves as a voltage divider, Fig. 3, which provides volt- age reference that is dependent upon the power supply volt- age. The biasing voltage VB is 683mV for 1.2V power sup- ply (nominal), and 600mV for 1.08V and 770mV for 1.32V power supply respectively. 574 576 578 580 582 584 586 -40 -20 0 20 40 60 80 100 120 140 V R EF (m V) Temperature(oC) Gain=100 Gain=325 Gain=550 Gain=775 Gain=1K Fig. 4. Reference voltage VREF vs. gain and temperature. Fig. 5. Modified start–up circuit diagram. Start–Up Circuit: Bandgap circuit has two stable operating points, in this case at IC0 = 0 and IC0 = 8.8µA, therefore a start–up circuit is needed to guarantee the desired mode of operation [3]. In a conventional start–up circuit, transistor M13 is BJT and its base is connected to the base of Q1 (i.e. to node A instead of node B, Fig. 5) and capacitor CS is not used. Under normal conditions and once the power supply is on, transistor MS1 injects a significant current into R1 and Q1. At the end of the start–up phase, the current through MS3 makes the voltage across RS high enough (close to VDD) to turn off MS1, thus the start–up circuit is turned off. However, there are two issues with the conventional start– up circuit. First, a small percentage of the injected current flows into the base of M13 (when it is BJT with base con- nected to node A), which disturbs the balance in the bandgap core circuit due to the local feedback loop. Thus, the out- put reference voltage is also affected because there is a slight amount of current drawn from bandgap core circuit and then 0 0.2 0.4 0.6 0.8 1 1.2 50 100 150 200 250 300 350 0 6 12 18 24 30 V( V) I D S1 (uA ) Time(ns) Vdd VREF VOpamp-Out IDS1 Fig. 6. The start–up transition period behaviour of VREF , op–amp’s output voltage, and MS1 drain–source current. injected into the start–up circuit continuously, even when the circuit locks at the desired operating point. To solve this problem, M13 BJT is replaced by a diode connected NMOS transistor M13, Fig. 5. This replacement guarantees that the start–up circuit is completely disconnected from the bandgap circuit once the start–up task is finished. Second, drain current of MS1 may stop too early, even be- fore the power voltage level is settled. To solve this problem, a gate capacitor CS is added to delay the rise of the voltage at gate of MS1. This delay also gives MS1 more time to turn on thoroughly and generate larger instantaneous current, Fig. 6. The Output Stage: As shown in Fig. 2, M3 mirrors the bandgap current through M1,2 proportionally, while the cur- rent’s absolute value is controlled by the main feedback loop. In order to reduce layout area and the temperature dependence of diffusion resistors, in the output stage appropriately biased transistors are used instead. Transistor ML2 is biased in linear region, while ML1 is diode connected and increases VREF voltage by Vthn. The biasing voltage of ML2 is the output voltage itself, as this node generates the most stable voltage in the circuit (in respect to temperature and power supply volt- age variations). This, the biasing arrangement drastically re- duces dependance of the transistor’s output impedance in re- spect to temperature and power supply voltage because the resistance of ML2 is controlled only by VGS , which is equiv- alent to VREF voltage. In addition, a 0.75pF CL capacitor is connected as a capacitive load to the bandgap voltage refer- ence output node. 3.1. Temperature dependance of passive components The n–type and p–type diffusion resistors have the opposite sign temperature coefficients, which implies that by combin- ing the two type of resistors in series with an appropriate ra- tio, the overall TC can be made very low. Considering that the 0.58 0.582 0.584 0.586 0.588 0.59 0.592 0.594 -40 -20 0 20 40 60 80 100 120 140 V R EF (V ) temperature(oC) VDD=0.96V VDD=1.08V VDD=1.20V VDD=1.32V Fig. 7. Simulation graph for VREF vs. VDD and temperature. 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.6 0.8 1 1.2 1.4 1.6 1.8 V R EF (V ) VDD (V) temp = -40oC -7oC 20oC 26oC 59oC 92oC 125oC Fig. 8. Simulation graph for VREF vs. temperature and VDD. bandgap reference voltage has a convex characteristic, use of real resistors have a slight complementary effect on the output voltage. 4. SIMULATION RESULTS AND DISCUSSION Graph with family of temperature sweep curves for various power supply voltages, Fig. 7, shows that the reference volt- age varies by 244µV over temperature sweep from 0◦C to 125◦C at the nominal VDD voltage. Slight increases of VREF at the low temperature and low power supply, and for high temperature and high power supply are caused by the gate– capacitors’ temperature dependence. To better investigate the power supply dependence, graph with family of curves of the output voltage dependance against the supply voltage sweep is shown in Fig. 8. The ripples in 600mV to 1V range are caused by the current difference be- 576 578 580 582 584 586 -40 -20 0 20 40 60 80 100 120 V R EF (m V) Temperature(oC) RL=850K Ohm 5M Ohm 30M Ohm 170M Ohm 1G Ohm Fig. 9. Dependence of VREF vs. load impedance and tem- perature. tween the two bipolar transistors in the bandgap core circuit. When VDD is low, it is easier for the bipolar transistors with lower current density to carry more current under the same condition of low VBE . For high temperature, i.e. 125◦C, the ripple disappears as the high temperature makes the bipolar transistor capable to work under higher current with the same low VBE , which eliminates the current difference between the two bipolar transistors, as shown by this equation [10] IBE(T2) = IBE(T1)( T2 T1 )XT1/nF exp[−qEg(300) nF kT2 (1− T2 T1 )] In order to specify the lower limit of the resistive load, the bandgap output node is connected to a load resistor whose resistance is swept over wide range. The simulation results show that the resistive load has lower limit at around 850kΩ, under constrain that a variation of reference voltage VREF is no more then 1.849mV across the temperature range of −40◦C to 125◦C, which means the error due to temperature variation is 0.3%, Fig. 9. More then 1000 Monte Carlo Analysis runs were executed that covered all corner extremes. If all of these runs that gen- erated |error| ≥ 1% are counted as failure, then the success rate for process variation and mismatch is around 85% and the yield is expected to be over 90%. Table 2 shows summary of the simulation specifications. This bandgap achieved very high accuracy without additional compensation circuit and it is able to operate within a very wide temperature range. The main drawback is relatively high dependence on the supply voltage, which may be caused by the high demand of the the CMOS op–amp, i.e. the op–amp itself needs to work under very harsh low–voltage conditions. Layout design occupies 100.92µm×84.74µm area, which includes dummy ring of BJT devices and array of decoupling capacitors, Fig. 10. Fig. 10. The bandgap voltage reference layout. 5. CONCLUSIONS A CMOS bandgap circuit has been presented for operation with 1.2V nominal power supply, while the extended power supply range is 0.96V ∼ 1.4V . The start–up block is further improved and an innovative output stage is applied, both con- tributing to improvement in performance and the accuracy. As a result, the presented circuit achieves very high accuracy of the voltage reference over wide temperature variation range and performs very well under wide power supply variation, without additional curvature compensation circuits. In the fu- ture work, contribution of curvature compensation circuit will be studied in more details. 6. ACKNOWLEDGEMENTS The authors would like to express gratitude to CMC Microsys- tems Inc. for providing infrastructure and support for our re- search. 7. REFERENCES [1] R.J. Widlar, “New developments in IC voltage regula- tors,” Solid-State Circuits, IEEE Journal of, vol. 6, no. 1, pp. 2–7, Feb 1971. [2] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. 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