1998-A Low-Voltage, Low Quiescent Current,Low Drop-out Regulator

36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998 A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator Gabriel A. Rincon-Mora, Member, IEEE, and Phillip E. Allen, Fellow, IEEE Abstract—The demand for low-voltage, low drop-out (LDO) regulators is increasing because of the growing demand for portable electronics, i.e., cellular phones, pagers, laptops, etc. LDO’s are used coherently with dc-dc converters as well as standalone parts. In power supply systems, they are typically cascaded onto switching regulators to suppress noise and provide a low noise output. The need for low voltage is innate to portable low power devices and corroborated by lower breakdown voltages resulting from reductions in feature size. Low quiescent current in a battery-operated system is an intrinsic performance parameter because it partially determines battery life. This paper discusses some techniques that enable the practical realizations of low qui- escent current LDO’s at low voltages and in existing technologies. The proposed circuit exploits the frequency response dependence on load-current to minimize quiescent current flow. Moreover, the output current capabilities of MOS power transistors are enhanced and drop-out voltages are decreased for a given device size. Other applications, like dc-dc converters, can also reap the benefits of these enhanced MOS devices. An LDO prototype incorporating the aforementioned techniques was fabricated. The circuit was operable down to input voltages of 1 V with a zero- load quiescent current flow of 23 �A. Moreover, the regulator provided 18 and 50 mA of output current at input voltages of 1 and 1.2 V, respectively. Index Terms— Low drop-out, low-voltage regulators, power supply circuits, regulators. I. INTRODUCTION THE low drop-out nature of the regulator makes it appro-priate for use in many applications, namely, automotive, portable, industrial, and medical applications [1]. The automo- tive industry requires low drop-out (LDO) regulators to power up digital circuits, especially during cold-crank conditions where the battery voltage can be below 6 V. The increasing demand, however, is especially apparent in mobile battery- operated products, such as cellular phones, pagers, camera recorders, and laptops [2]. In a cellular phone, for instance, switching regulators are used to boost up the voltage but LDO’s are cascaded in series to suppress the inherent noise associated with switchers. LDO’s benefit from working with low input voltages because power consumption is minimized accordingly, . Low voltage and low quiescent current are intrinsic circuit characteristics for increased battery efficiency and longevity [3]. Low voltage operation is also a consequence of process technology. This is because isolation Manuscript received October 4, 1996; revised March 30, 1997. G. A. Rincon-Mora is with the Standard Linear Design Branch, Texas Instruments Incorporated, Dallas, TX 75243 USA. P. E. Allen is with the School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0250 USA. Publisher Item Identifier S 0018-9200(98)00368-0. Fig. 1. Typical low drop-out regulator topology. barriers decrease as the component densities per unit area increase, thereby exhibiting lower breakdown voltages [4], [5]. Therefore, low power and finer lithography require regulators to operate at low voltages, produce precise output voltages, and have characteristically lower quiescent current flow [5]. By the year 2004, the power supply voltage is expected to be as low as 0.9 V in 0.14- m technologies [5], [6]. Drop-out voltages also need to be minimized to maximize dynamic range within a given power supply voltage. This is because the signal-to- noise ratio typically decreases as the power supply voltages decrease while noise remains constant [7]. Lastly, financial considerations also require that these circuits be realized in relatively simple processes, such as standard CMOS, bipolar, and inexpensive BiCMOS technologies [8]. An example of the relatively inexpensive BiCMOS process is the 2- m MOSIS technology (information is available through the Internet at http://www.isi.edu/mosis). This is a vanilla CMOS process with an added p-base layer to realize vertical NPN transistors. Fig. 1 illustrates the general components of a typical low drop-out regulator, namely, an error amplifier, a pass device, a reference circuit, a feedback network, and some loading elements. The associated gate capacitance of the pass device is depicted as . II. CURRENT EFFICIENT BUFFER A. Current Efficiency Current efficiency is an important characteristic of battery- powered products. It is defined as the ratio of the load-current to the total battery drain current, which is comprised of load- 0018–9200/98$10.00  1998 IEEE RINCON-MORA AND ALLEN: LOW-VOLTAGE, LOW QUIESCENT CURRENT, LOW DROP-OUT REGULATOR 37 current and the quiescent current of the regulator Efficiency (1) Current efficiency determines how much the lifetime of the battery is degraded by the mere existence of the regulator. Battery life is restricted by the total battery current drain. During conditions where the load-current is much greater than the quiescent current, operation lifetime is essentially determined by the load-current, which is an inevitable char- acteristic of linear regulators. On the other hand, the effects of quiescent current on battery life are most prevalent during low load-current conditions when current efficiency is low. For many applications, high load-current is usually a temporary condition, whereas the opposite is true for low load-currents. As a result, current efficiency plays a pivotal role in designing battery-powered supplies. The two performance specifications that predominantly limit the current efficiency of low drop-out regulators are maximum load-current and transient output volt- age variation requirements. Typically, more quiescent current flow is necessary for improved performance in these areas. B. Challenges Output current and input voltage range directly affect the characteristics of the pass element in the regulator, which defines the current requirements of the error amplifier. As the maximum load-current specification increases, the size of the pass device necessarily increases. Consequently, the amplifier’s load capacitance, in Fig. 1, increases. This affects the circuit’s frequency performance by reducing the value of the parasitic pole present at the output of the amplifier [9]. Therefore, phase-margin degrades and stability may be compromised unless the output impedance of the amplifier is reduced accordingly. As a result, more current in the buffer stage of the amplifier is required, be it a voltage follower or a more complicated circuit architecture. In a similar manner, low input voltages require that MOS pass device structures increase in size and thus yield the same negative effects on frequency response and quiescent current as just described. This is because the gate drive decreases as the input voltages decrease, thereby demanding larger MOS pass elements to drive high output currents. Further limits to low quiescent current arise from the transient requirements of the regulator, namely, the permissible output voltage variation in response to a maximum load- current step swing. The output voltage variation is determined by the response time of the circuit, the specified load-current, and the output capacitor [9]. The worst case response time corresponds to the maximum output voltage variation. This time limitation is determined by the closed-loop bandwidth of the system and the output slew-rate current of the error amplifier [9]. These characteristic requirements become more difficult to realize as the size of the parasitic capacitor at the output of the amplifier increases, which results from low-voltage operation and/or increased output current specifications. Consequently, the quiescent current of the am- plifier’s gain stage is limited by a bandwidth minimum while Fig. 2. Current efficient LDO buffer stage. the quiescent current of the amplifier’s buffer stage is limited by the slew-rate current required to drive . C. Proposed Circuit Topology A topology that achieves good current efficiency perfor- mance is illustrated in Fig. 2. The operation revolves around sensing the output current of the regulator and feeding back a ratio of the current to the slew-rate limited node of the circuit. Transistor Mps sources a fraction of the current flowing through the output transistor Mpo. During low load-current conditions, the current fed back is negligible, thereby yielding high overall current efficiency and not aggravating battery life. Consequently, the current through the emitter follower is simply when load-current is low. During high load-current conditions, the current through the emitter follower is increased by , which is no longer negligible. The resulting increase in quiescent current has an insignificant impact on current efficiency because the load-current is, at this point, much greater in magnitude. However, the increase in current in the buffer stage aids the circuit by pushing the para- sitic pole associated with to higher frequencies and by increasing the current available for slew-rate conditions. Thus, the biasing conditions for the case of zero load-current can be designed to utilize a minimum amount of current, which yields maximum current efficiency and prolonged battery life. 1) Frequency Response: When the load-current is low, the magnitude of the system’s dominant pole , determined by the output capacitor and the output impedance of the pass device, is also low [10]. This is because the output impedance of the pass device is inversely proportional to the current flowing through it - (2) where is the output capacitance, - is the output resis- tance of Mpo, is the channel length modulation parameter, and is the load-current. Consequently, the unity gain frequency (UGF) is at low frequencies when the load-current is low, which relaxes the requirement of the parasitic pole at the 38 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998 output of the error amplifier to be approximately greater than or equal to the minimum unity gain frequency . This corresponds to a phase margin of approximately 45 to 90 with an associated design equation of - - (3) where is the transconductance of the emitter follower and is the thermal voltage. As load-current increases, how- ever, the dominant pole increases linearly and consequently so does the UGF. The open-loop gain is inversely proportional to the square root of the load current - (4) where is the gain of the error amplifier, while and - are the transconductance and the output resistance of the pass device, respectively. Since the dominant pole increases faster than the gain decreases with load-current, the unity gain frequency increases as the load-current increases [(2) and (4)]. These consequential effects of load-current on frequency response are graphically illustrated in Fig. 3. Zero and pole are defined by the output capacitor , associated equivalent series resistance (ESR) of , and the bypass capacitors shown in Fig. 1 [9]. Therefore, the parasitic pole is also required to increase with load- current, which is achieved by the load dependent boost current. This is apparent from the following equation: (5) where corresponds to a constant mirror ratio, i.e., 1/1500 for Fig. 2. The circuit can be designed such that increases at a faster rate than the UGF with respect to load-current. This results in the following relation: - - (6) or (7) where - , - , and are the rates with re- spect to load-current of pole , pole , and the unity gain frequency, respectively. Thus, current efficiency can be maximized to accommodate the load dependent requirements of . If the load dependence of is not incorporated into the circuit, then more current than necessary is used during low load-current conditions. The frequency response behavior was confirmed through simulations. 2) Transient Response: The circuit of Fig. 2 exhibits the transient response illustrated in Fig. 4 depicted as trace “a” where a maximum load-current step swing is applied to the load. One of the parameters that determines the maximum Fig. 3. System frequency response as a function of load-current. output voltage variation is the response time required for the system to react and may be expressed as (8) where BW is the closed-loop bandwidth of the system, is the voltage change associated with , and is the output slew-rate current of the error amplifier [9]. However, the slew-rate current is not constant for the circuit proposed, . As a result, a slew-rate condition does not aptly describe the operation of the circuit at hand. During a load-current transition from zero to maximum value, the response time of the circuit is dominated by the bandwidth of the system and the transient response of the buffer stage. In particular, the response time is composed of the time required for the amplifier to respond , for the sense PMOS transistor (Mps) to start conducting current - , for the positive feedback circuit to latch up - , and for the output PMOS device (Mpo) to conduct the load-current . This is represented by the following equation: - - - - (9) where BW is the closed-loop bandwidth of the system (approximately ). The composite buffer stage is essentially a localized positive feedback circuit. The system is stable because the positive feedback gain is less than one. Consequently, the circuit attempts to latch up until the output transistor is fully turned on; at which point, the error amplifier forces the circuit back into the linear region. As a result, the performance tradeoffs between the slew-rate and the quiescent current requirements of typical LDO’s are circumvented. For instance, if the parasitic capacitance is 200 pF, the source-to-gate voltage change required for the output PMOS transistor is 0.5 V, the bandwidth of the system is 1 MHz, and the response time is limited to be less than 5 s, then the slew-rate current required is approximately 25 A [(8)]. For the case of the circuit in Fig. 2, a dc current bias of only 1 A can provide the same performance. The dominant factor of the new is the time required for the sense transistor (Mps) to go from being off to subthreshold and finally to strong inversion. Fig. 4 illustrates the simulation results showing the effect of the presence of boost element Mps in the circuit shown in Fig. 2 on the output voltage, for the same biasing conditions. In this case, the load- current is stepped from zero to a maximum of 50 mA in 1 ns. RINCON-MORA AND ALLEN: LOW-VOLTAGE, LOW QUIESCENT CURRENT, LOW DROP-OUT REGULATOR 39 Fig. 4. LDO output voltage variation with and without the boost element Mps in the current efficient buffer stage. It is observed that the output voltage variation is lower for the circuit implementing the current efficient buffer resulting from a reduction in response time. This does not come at the expense of additional quiescent current flow during zero load-current conditions. Consequently, current efficiency and battery life are maximized. III. CURRENT BOOSTING A. Challenge As the power supply voltages decrease, the gate drive available for the PMOS pass device decreases. As a result, the aspect ratio of the power transistor needs to be increased to provide acceptable levels of output current. However, the parasitic gate capacitance also increases as the size of the PMOS transistor increases. This constitutes an increase in in Fig. 1, which pulls the parasitic pole down to lower frequencies. Consequently, the phase margin of the system is degraded and stability may be compromised. This presents a problem when working in a low quiescent current environment. B. Boosting Technique One way to improve gate drive without increasing input voltage or device size is by forward biasing the source-to-bulk junction of the PMOS pass device. This results in a reduction of threshold voltage, commonly referred as the bulk effect phenomenon. The threshold voltage is described by (10) where is at a source-to-bulk voltage of zero, is the body bias coefficient, and is the bulk Fermi potential [11]. Consequently, the threshold voltage decreases as increases, thereby effectively increasing the gate drive of the power PMOS transistor (pass device). 1) Maximum Output Current: For comparative analysis, the maximum current can be observed at the region where the power PMOS device is in saturation, which corresponds to the nondrop-out condition. The corresponding drain current Fig. 5. Maximum load-current performance of the current boost enhance- ment. of the device is (11) where is the transconductance parameter of a PMOS transistor. Maximum output current results when the gate drive is at its peak, which occurs when the source-to-gate voltage is equal to the input voltage . Thus, if is 15 A/V , is 0.9 V, is 30 k m/ m, and is 1.2 V, then the maximum output current - is 20.2 mA when the source-to-bulk junction is not forward biased. On the other hand, if the source-to-bulk junction is forward biased by 0.3 V, then - is 38.5 mA (assuming that is 0.5 V and is 0.6 V). As a result, the output current capability of a PMOS device can be significantly increased by simply forward biasing the source-to-bulk junction. Fig. 5 illustrates how this technique performs on the prototype circuit of Fig. 2 where the aspect ratio of the power PMOS transistor is 2 k m/ m. A battery is placed between the source and bulk of the output PMOS device, and the load-current is swept from 0 to 500 A. For the same input voltage, the maximum output current capability is increased as is increased, in other words, the circuit stays in regulation for an increased load-current range. At a forward-biased junction voltage of 0.3 V, the output current is more than doubled compared to its nonforward-biased state. Fig. 6 illustrates a successful implementation of the tech- nique in a low drop-out regulator. This concept could easily be extended to dc-dc converters. The forward-biased junction is defined by the voltage drop across the Schottky diode (Ds). This voltage drop has to be less than a base-emitter voltage to prevent the parasitic vertical PNP transistors of the power PMOS device (Mpo) from turning on and conducting significant ground current through the substrate via the well. The effects of the parasitic bipolar transistors are mitigated by placing a heavily doped buried layer underneath the well of the power PMOS transistor, if this layer is available. Furthermore, the ability to shut off Mpo is not degraded since the forward 40 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998 Fig. 6. LDO with current boosting capabilities. bias voltage is a function of load-current. This is similar to the operation of the current efficient circuit of Fig. 2. Thus, is low and is close to zero at low load-currents. At high load-currents, however, and increase, thereby decreasing the threshold voltage and increasing the gate drive of the output PMOS device. 2) Drop-Out Voltage: The method of forward biasing the source-to-bulk junction also yields lower drop-out voltages. In other words, the “on” resistance of the pass device (Mpo) is reduced. When the regulator is in drop-out, Mpo is charac- teristically in the triode region and exhibits the well-known current relationship of (12) The “on” resistance of the PMOS device is approxi- mately (13) and the drop-out voltage is (14) Thus, if is 15 A/V , is 0.9 V, is 30 k m/ m, is 1.2 V, and is 20 mA, then the drop-out voltage is 296 mV (corresponding to 14.8 ) when the source-to-bulk junction is not forward biased. However, if the source-to-bulk junction is forward biased by 0.3 V, then bec