电压模式脉宽调制控制电路SG3525_DataSheet

������� ������� SEMICONDUCTOR TECHNICAL DATA PULSE WIDTH MODULATOR CONTROL CIRCUITS PIN CONNECTIONS Order this document by SG3525A/D N SUFFIX PLASTIC PACKAGE CASE 64816 1 DW SUFFIX PLASTIC PACKAGE CASE 751B (SO–16L) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top View) Inv. Input Sync OSC. Output RT Discharge Soft–Start Noninv. Input CT Compensation Shutdown Output A VC Output B VCC Vref Ground Device Operating Temperature Range Package ORDERING INFORMATION SG3525AN SG3525ADW TA = 0° to +70°C Plastic DIP SO–16L SG3527AN Plastic DIP 16 1 1MOTOROLA ANALOG IC DEVICE DATA ���� ����� ���� ��� ������� �������� The SG3525A, SG3527A pulse width modulator control circuits offer improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on–chip +5.1 V reference is trimmed to ±1% and the error amplifier has an input common–mode voltage range that includes the reference voltage, thus eliminating the need for external divider resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. A wide range of deadtime can be programmed by a single resistor connected between the CT and Discharge pins. These devices also feature built–in soft–start circuitry, requiring only an external timing capacitor. A shutdown pin controls both the soft–start circuitry and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft–start recycle with longer shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft–start capacitor when VCC is below nominal. The output stages are totem–pole design capable of sinking and sourcing in excess of 200 mA. The output stage of the SG3525A features NOR logic resulting in a low output for an off–state while the SG3527A utilized OR logic which gives a high output when off. • 8.0 V to 35 V Operation • 5.1 V ± 1.0% Trimmed Reference • 100 Hz to 400 kHz Oscillator Range • Separate Oscillator Sync Pin • Adjustable Deadtime Control • Input Undervoltage Lockout • Latching PWM to Prevent Multiple Pulses • Pulse–by–Pulse Shutdown • Dual Source/Sink Outputs: ±400 mA Peak Representative Block Diagram NOR NOR 16 15 12 4 3 6 5 7 9 1 2 8 10 Reference Regulator Under– Voltage Lockout Oscillator Latch F/F Q Q – PWM Error Amp + – + – To Internal Circuitry VREF Vref VCC Ground OSC Output Sync RT CT Discharge Compensation INV. Input Noninv. Input CSoft–Start Shutdown 5.0k S R S50µA VC 13 Output A 11 14 Output B SG3525A Output Stage 13 VC Output A 11 Output B 14 SG3527A Output Stage OR OR 5.0k  Motorola, Inc. 1996 Rev 2 SG3525A SG3527A 2 MOTOROLA ANALOG IC DEVICE DATA MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit Supply Voltage VCC +40 Vdc Collector Supply Voltage VC +40 Vdc Logic Inputs –0.3 to +5.5 V Analog Inputs –0.3 to VCC V Output Current, Source or Sink IO ±500 mA Reference Output Current Iref 50 mA Oscillator Charging Current 5.0 mA Power Dissipation (Plastic & Ceramic Package) TA = +25°C (Note 2) TC = +25°C (Note 3) PD 1000 2000 mW Thermal Resistance Junction–to–Air RθJA 100 °C/W Thermal Resistance Junction–to–Case RθJC 60 °C/W Operating Junction Temperature TJ +150 °C Storage Temperature Range Tstg –55 to +125 °C Lead Temperature (Soldering, 10 seconds) TSolder +300 °C NOTES: 1. Values beyond which damage may occur. 2. Derate at 10 mW/°C for ambient temperatures above +50°C. 3. Derate at 16 mW/°C for case temperatures above +25°C. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit Supply Voltage VCC 8.0 35 Vdc Collector Supply Voltage VC 4.5 35 Vdc Output Sink/Source Current (Steady State) (Peak) IO 0 0 ±100 ±400 mA Reference Load Current Iref 0 20 mA Oscillator Frequency Range fosc 0.1 400 kHz Oscillator Timing Resistor RT 2.0 150 kΩ Oscillator Timing Capacitor CT 0.001 0.2 µF Deadtime Resistor Range RD 0 500 Ω Operating Ambient Temperature Range TA 0 +70 °C APPLICATION INFORMATION Shutdown Options (See Block diagram, front page) Since both the compensation and soft–start terminals (Pins 9 and 8) have current source pull–ups, either can readily accept a pull–down signal which only has to sink a maximum of 100 µA to turn off the outputs. This is subject to the added requirement of discharging whatever external capacitance may be attached to these pins. An alternate approach is the use of the shutdown circuitry of Pin 10 which has been improved to enhance the available shutdown options. Activating this circuit by applying a positive signal on Pin 10 performs two functions: the PWM latch is immediately set providing the fastest turn–off signal to the outputs; and a 150 µA current sink begins to discharge the external soft–start capacitor. If the shutdown command is short, the PWM signal is terminated without significant discharge of the soft–start capacitor, thus, allowing, for example, a convenient implementation of pulse–by–pulse current limiting. Holding Pin 10 high for a longer duration, however, will ultimately discharge this external capacitor, recycling slow turn–on upon release. Pin 10 should not be left floating as noise pickup could conceivably interrupt normal operation. SG3525A SG3527A 3MOTOROLA ANALOG IC DEVICE DATA ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 4], unless otherwise noted.) Characteristics Symbol Min Typ Max Unit REFERENCE SECTION Reference Output Voltage (TJ = +25°C) Vref 5.00 5.10 5.20 Vdc Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline – 10 20 mV Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload – 20 50 mV Temperature Stability ∆Vref/∆T – 20 – mV Total Output Variation Includes Line and Load Regulation over Temperature ∆Vref 4.95 – 5.25 Vdc Short Circuit Current (Vref = 0 V, TJ = +25°C) ISC – 80 100 mA Output Noise Voltage (10 Hz ≤ f ≤ 10 kHz, TJ = +25°C) Vn – 40 200 µVrms Long Term Stability (TJ = +125°C) (Note 5) S – 20 50 mV/khr OSCILLATOR SECTION (Note 6, unless otherwise noted.) Initial Accuracy (TJ = +25°C) – ±2.0 ±6.0 % Frequency Stability with Voltage (+8.0 V ≤ VCC ≤ +35 V) ∆fosc D VCC – ±1.0 ±2.0 % Frequency Stability with Temperature ∆fosc D T – ±0.3 – % Minimum Frequency (RT = 150 kΩ, CT = 0.2 µF) fmin – 50 – Hz Maximum Frequency (RT = 2.0 kΩ, CT = 1.0 nF) fmax 400 – – kHz Current Mirror (IRT = 2.0 mA) 1.7 2.0 2.2 mA Clock Amplitude 3.0 3.5 – V Clock Width (TJ = +25°C) 0.3 0.5 1.0 µs Sync Threshold 1.2 2.0 2.8 V Sync Input Current (Sync Voltage = +3.5 V) – 1.0 2.5 mA ERROR AMPLIFIER SECTION (VCM = +5.1 V) Input Offset Voltage VIO – 2.0 10 mV Input Bias Current IIB – 1.0 10 µA Input Offset Current IIO – – 1.0 µA DC Open Loop Gain (RL ≥ 10 MΩ) AVOL 60 75 – dB Low Level Output Voltage VOL – 0.2 0.5 V High Level Output Voltage VOH 3.8 5.6 – V Common Mode Rejection Ratio (+1.5 V ≤ VCM ≤ +5.2 V) CMRR 60 75 – dB Power Supply Rejection Ratio (+8.0 V ≤ VCC ≤ +35 V) PSRR 50 60 – dB PWM COMPARATOR SECTION Minimum Duty Cycle DCmin – – 0 % Maximum Duty Cycle DCmax 45 49 – % Input Threshold, Zero Duty Cycle (Note 6) Vth 0.6 0.9 – V Input Threshold, Maximum Duty Cycle (Note 6) Vth – 3.3 3.6 V Input Bias Current IIB – 0.05 1.0 µA NOTES: 4. Tlow = 0° for SG3525A, 3527A Thigh = +70°C for SG3525A, 3527A 5. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 6. Tested at fosc = 40 kHz (RT = 3.6 kΩ, CT = 0.01 µF, RD = 0Ω). SG3525A SG3527A 4 MOTOROLA ANALOG IC DEVICE DATA ELECTRICAL CHARACTERISTICS (Continued) Characteristics Symbol Min Typ Max Unit SOFT–START SECTION Soft–Start Current (Vshutdown = 0 V) 25 50 80 µA Soft–Start Voltage (Vshutdown = 2.0 V) – 0.4 0.6 V Shutdown Input Current (Vshutdown = 2.5 V) – 0.4 1.0 mA OUTPUT DRIVERS (Each Output, VCC = +20 V) Output Low Level (Isink = 20 mA) (Isink = 100 mA) VOL – – 0.2 1.0 0.4 2.0 V Output High Level (Isource = 20 mA) (Isource = 100 mA) VOH 18 17 19 18 – – V Under Voltage Lockout (V8 and V9 = High) VUL 6.0 7.0 8.0 V Collector Leakage, VC = +35 V (Note 7) IC(leak) – – 200 µA Rise Time (CL = 1.0 nF, TJ = 25°C) tr – 100 600 ns Fall Time (CL = 1.0 nF, TJ = 25°C) tf – 50 300 ns Shutdown Delay (VDS = +3.0 V, CS = 0, TJ = +25°C) tds – 0.2 0.5 µs Supply Current (VCC = +35 V) ICC – 14 20 mA NOTE: 7. Applies to SG3525A only, due to polarity of output pulses. Reference Regulator Flip/ Flop PWM – + E/A DUT Vref Clock 16 4 0.1 3 6 7 5 Deadtime 100Ω 0.001 Comp 10k 9 0.01 1 2 1 2 3 1 2 33 2 1 3 + – 1 = VIO 2 = 1(+) 3 = 1(–) 0.1 0.009 1.5k 1.0k 3.0k PWM ADJ. Sync RT Ramp 50µA 5.0k 5.0k 15 13 11 VC Out A 0.1 0.1 1.0k, 1.0W (2) 14 Out B Gnd12 8 Softstart 5.0µF 10 2.0k Shutdown Vref + O s c i l l a t o r V/I Meter VCC A 1 2 B Lab Test Fixture SG3525A SG3527A 5MOTOROLA ANALOG IC DEVICE DATA R T Ω , TI MI NG R ES IS TO R (k ) Figure 1. Oscillator Charge Time versus RT Figure 2. Oscillator Discharge Time versus RD Figure 3. Error Amplifier Open Loop Frequency Response Figure 4. Output Saturation Characteristics (SG3525A) 2.0 5.0 10 20 50 100 200 500 1000 2000 5000 10,000 CHARGE TIME (µs) 6 5 7RD * CT RT * RD = 0 Ω 0.2 0.5 1.0 2.0 5.0 10 20 50 100 200 DISCHARGE TIME (µs) , DE AD TI ME R ES IS TO R ( ) D Ω R 1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 1 2 9 CP RZ f, FREQUENCY (Hz) , VO LT AG E GA IN (d B) VO L – + A RZ = 20 k Vref RT CT Sync Discharge Gnd 16 6 5 3 7 12 Q2 Q1 Q6 Q9 2.0k 2.0k 14k Q10 Q11 5.0pF 400µA 23k Q4 Q7 1.0k Q12 Q133.0k 250 4 Blanking To Output Ramp To PWM Q14 25k 7.4k Q5 Q8 Q3 OSC Output 1.0k 15 Q3 VCC 9 30 Compensation 1 2 Q4 Q1 Q2InvertingInput 5.8V100µA To PWM Comparator 200µA Noninverting Input Figure 5. Oscillator Schematic (SG3525A) 0.01 0.02 0.03 0.05 0.07 0.1 0.2 0.3 0.5 0.7 1.0 IO, OUTPUT SOURCE OR SINK CURRENT (A) , SA TU RA TI ON V OL TA GE (V ) sa t V Sink Sat, (VOL) Source Sat, (VC–VOH) VCC = +20 V TJ = +25°C Figure 6. Error Amplifier Schematic (SG3525A) 200 100 50 20 10 5.0 2.0 500 400 300 200 100 0 100 80 60 40 20 0 –20 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 SG3525A SG3527A 6 MOTOROLA ANALOG IC DEVICE DATA Figure 7. SG3525A Output Circuit (1/2 Circuit Shown) Figure 8. Single–Ended Supply Figure 9. Push–Pull Configuration Figure 10. Driving Power FETS Low power transformers can be driven directly by the SG3525A. Automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. Q1 R1 R2 13 To Output Filter 11 14 12 VC SG3525A A B Gnd +Vsupply For single–ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem–pole source transistors on alternate oscillator cycles. In conventional push–pull bipolar designs, forward base drive is controlled by R1–R3. Rapid turn–off times for the power devices are achieved with speed–up capacitors C1 and C2. VC SG3525A A B Gnd +Vsupply R1 13 12 11 14 R3 C2 C1 Q1 Q2 T1 R2 The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. +Vsupply VC SG3525A A BGnd 11 14 Q1 Q2 T1 R1 13 12 VC SG3525A A BGnd 13 11 14 12 +Vsupply T1 Q1 Q2 R2 R1 T2 C1 C2 Figure 11. Driving Transformers in a Half–Bridge Configuration Q3 VCC Q5 Q4 Q7 Q9 Q10 13 VC Vref Q1 Q2 Q6 Omitted in SG3527A 5.0k 10k 10k 2.0k Q11 Q6 Q8 5.0k 11, 14 Output Clock F/F PWM SG3525A SG3527A 7MOTOROLA ANALOG IC DEVICE DATA OUTLINE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R DW SUFFIX PLASTIC PACKAGE CASE 751B–05 (SO–16L) ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– B F C S H G D J L M 16 PL SEATING 1 8 916 K PLANE–T– MAM0.25 (0.010) T DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.740 0.770 18.80 19.55 B 0.250 0.270 6.35 6.85 C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7.74 M 0 10 0 10 S 0.020 0.040 0.51 1.01 ���� NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 1 8 16 9 SEATING PLANE F JM R X 45 � G 8 PLP–B– –A– M0.25 (0.010) B S –T– D K C 16 PL SBM0.25 (0.010) A ST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.80 10.00 0.386 0.393 B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 G 1.27 BSC 0.050 BSC J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 M 0 7 0 7 P 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 � � � � SG3525A SG3527A 8 MOTOROLA ANALOG IC DEVICE DATA Motorola reserves the right to make changes without further notice to any products herein. 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