©On-Bright Electronics Confidential
- 1 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
GENERAL DESCRIPTION
OB2279 is a highly integrated current mode PWM
control IC optimized for high performance, low
standby power and cost effective offline flyback
converter applications.
PWM switching frequency at normal operation is
externally programmable and trimmed to tight range.
At no load or light load condition, the IC operates in
extended ‘burst mode’ to minimize switching loss.
Lower standby power and higher conversion
efficiency is thus achieved.
VDD low startup current and low operating current
contribute to a reliable power on startup design with
OB2279. A large value resistor could thus be used in
the startup circuit for reduced power loss.
The internal slope compensation improves system
large signal stability and reduces the possible sub-
harmonic oscillation at high PWM duty cycle output.
Leading-edge blanking on current sense input
removes the signal glitch due to snubber circuit diode
reverse recovery and greatly reduces the external
component count and system cost in the design.
OB2279 offers comprehensive protection coverage
including Cycle-by-Cycle current limiting(OCP),
VDD Under Voltage Lockout(UVLO), VDD Over
Voltage Protection(OVP), VDD Clamp, Gate Clamp,
Over Load protection(OLP) and Over Temperature
protection (OTP), etc.
Different latch shutdown options are offered on
OB2279 in different device version. V version has
OVP Latch shutdown. T version supports both OVP
and OTP latch shutdown. L version provides all OVP,
OTP and OLP latch shutdown control.
Excellent EMI performance is achieved with On-
Bright proprietary frequency shuffling technique
together with soft switching control at the totem pole
gate drive output.
OB2279 is offered in SOP-8 and DIP-8 packages.
FEATURES
■ On-Bright Proprietary Frequency Shuffling
Technology for Improved EMI Performance
■ Power On Soft Start
■ Extended Burst Mode Control For Improved
Efficiency and Minimum Standby Power Design
■ Audio Noise Free Operation
■ External Programmable PWM Switching
Frequency
■ Internal Synchronized Slope Compensation
■ Low VIN/VDD Startup Current(3uA) and Low
Operating Current (2.3mA)
■ Leading Edge Blanking on Current Sense Input
■ Complete Protection Coverage with selective
protections for Latch Shutdown
o VDD Over Voltage Protection(OVP) – Latch
Shutdown
o Over Temperature Protection(OTP) – Auto
recovery or Latch Shutdown
o Over Load Protection. (OLP) – Auto recovery
or Latch Shutdown
o VDD Under Voltage Lockout with Hysteresis
(UVLO)
o Gate Output Voltage Clamp (16.5V)
o Built-in OCP Compensation to Achieve
Minimum OPP Variation over Universal AC
Input Range.
APPLICATIONS
Offline AC/DC flyback converter for
■ Adaptor
■ Notebook Adaptor
■ LCD Monitor/TV/PC/Set-Top Box Power
Supplies
■ Open-frame SMPS
■ Printer Power
TYPICAL APPLICATION
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- 2 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
GENERAL INFORMATION
Pin Configuration
The pin map of OB2279 in DIP8 and SOP8 package
is shown as below.
Ordering Information
Part Number Description
OB2279AP-V DIP8, tube package, V
version with OVP Latch
OB2279AP-T DIP8, tube package, T
version with OVP/OTP latch
OB2279AP-L DIP8, tube package, L
version with OVP/OTP/OLP
latch
OB2279CP-V SOP8, tube package, V
version with OVP latch
OB2279CPA-V SOP8, taping package, V
version with OVP latch
OB2279CP-T SOP8, tube package, T
version with OVP/OTP latch
OB2279CPA-T SOP8, taping package, T
version with OVP/OTP latch
OB2279CP-L SOP8, tube package, L
version with OVP/OTP/OLP
latch
OB2279CPA-L SOP8, taping package, L
version with OVP/OTP/OLP
latch
Note: All Devices are offered in Pb-free Package if not otherwise
noted.
Package Dissipation Rating
Package RθJA (°C/W)
DIP8 90
SOP8 150
Absolute Maximum Ratings
Parameter Value
VDD Clamp Voltage (Vclamp) 35 V
VDD Clamp Continuous
Current
10 mA
VIN / VDD Input Voltage -0.3V to Vclamp
FB Input Voltage -0.3 to 7V
Sense Input Voltage -0.3 to 7V
RT Input Voltage -0.3 to 7V
RI Input Voltage -0.3 to 7V
Min/Max Operating Junction
Temperature TJ
-20 to 150 oC
Min/Max Storage Temperature
Tstg
-55 to 150 oC
Lead Temperature (Soldering,
10 seconds)
260 oC
Note: Stresses beyond those listed under “absolute maximum
ratings” may cause permanent damage to the device. These are
stress ratings only, functional operation of the device at these or
any other conditions beyond those indicated under
“recommended operating conditions” is not implied. Exposure to
absolute maximum-rated conditions for extended periods may
affect device reliability.
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- 3 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
Marking Information
TERMINAL ASSIGNMENTS
Pin Num Pin Name I/O Description
1 GND P Ground
2 FB I Feedback input pin. PWM duty cycle is determined by voltage level into this
pin and current-sense signal level at Pin 6.
3 VIN I Connected through a large value resistor to rectified line input for startup
and line voltage sensing.
4 RI I Internal oscillator frequency setting pin. A resistor connected between RI
and GND sets the PWM frequency.
5 RT I Dual function pin. Either connected through a NTC resistor to GND for over
temperature shutdown control or used as latch shutdown control input.
6 SENSE I Current sense input pin. Connected to MOSFET current sensing resistor
node.
7 VDD P DC power supply pin.
8 GATE O Totem-pole gate drive output for power MOSFET.
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- 4 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
BLOCK DIAGRAM
RECOMMENDED OPERATING CONDITION
Symbol Parameter Min Max Unit
VDD VDD Supply Voltage 11.5 25 V
TA Operating Ambient Temperature -20 85 oC
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- 5 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
ELECTRICAL CHARACTERISTICS
(TA = 25℃, RI=100K ohm, VDD=16V, if not otherwise noted)
Symbol Parameter Test Conditions Min Typ Max Unit
Supply Voltage (VDD)
I_VDD_Startup VDD Start up Current VDD =15VMeasure
current into VDD
3 20 uA
I_VDD_Ops Operation Current VFB=3V 2.3 mA
UVLO(Enter) VDD Under Voltage
Lockout Enter
8.8 9.8 10.8 V
UVLO(Exit) VDD Under Voltage
Lockout Exit
(Startup)
15.5 16.5 17.5 V
OVP(Latch) VDD Over Voltage
Latch Trigger
26.5 28 29.5 V
OVP(De-Latch) VDD Latch Release
Voltage Threshold
7.5 V
I(Vdd)_latch VDD bleeding current
at latch shutdown
when VDD = 9V
45 uA
TD_OVP VDD OVP Debounce
time
80 uSec
VDD_Clamp VDD Zener Clamp
Voltage
I(VDD ) = 5 mA 35 V
T_Softstart Soft Start Time 3 mSec
Feedback Input Section(FB Pin)
AVCS PWM Input Gain ΔVFB /ΔVcs 2.8 V/V
VFB_Open VFB Open Voltage 6.2
V
IFB_Short FB pin short circuit
current
Short FB pin to GND,
measure current
0.75 mA
VTH_0D Zero Duty Cycle FB
Threshold Voltage
0.95 V
VTH_BM Burst Mode FB
Threshold Voltage
1.6 V
VTH_PL Power Limiting FB
Threshold Voltage
4.4 V
TD_PL Power limiting
Debounce Time
80 mSec
ZFB_IN Input Impedance 9.0 Kohm
Current Sense Input(Sense Pin)
T_blanking Sense Input Leading
Edge Blanking Time
300 nSec
ZSENSE_IN Sense Input
Impedance
30 Kohm
TD_OC Over Current
Detection and Control
Delay
CL=1nf at GATE, 70 nSec
VTH_OC_0 Current Limiting
Threshold at No
Compensation
I(VIN) = 0uA 0.85 0.90 0.95 V
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- 6 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
VTH_OC_1 Current Limiting
Threshold at
Compensation
I(VIN) = 150uA, 0.80 V
Oscillator
FOSC Normal Oscillation
Frequency
60 65 70 KHZ
∆f_Temp Central Frequency
Temperature Stability
-20oC to 100 oC 3 %
∆f_VDD Central Frequency
Voltage Stability
VDD = 12-28V, 3 %
RI_range Operating RI Range 50 100 250 Kohm
V_RI_open RI open voltage 2.0 V
F_BM Burst Mode Base
Frequency
20 KHZ
Gate Drive Output
VOL Output Low Level Io = 20 mA 0.3 V
VOH Output High Level Io = 20 mA 11 V
VG_Clamp Output Clamp
Voltage Level
16.5 V
T_r Output Rising Time CL = 1nf 120 nSec
T_f Output Falling Time CL = 1nf 50 nSec
Over Temperature Protection
I_RT Output Current of RT
pin
70 uA
VTH_OTP OTP Threshold
Voltage
1.015 1.065 1.115 V
VTH_OTP_off
(Version V Only)
OTP Recovery
Threshold Voltage
1.165 V
VTH_RT_latch
(Version V Only)
RT Input Latch
Threshold Voltage
0.6 V
TD_OTP OTP De-bounce Time 100 uSec
V_RT_Open RT Pin Open Voltage 3.7 V
Frequency Shuffling
∆f_OSC Frequency
Modulation range
/Base frequency
-3 3 %
Freq_Shuffling Shuffling Frequency 32 HZ
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- 7 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
CHARACTERIZATION PLOTS
VDD Startup Current vs. VDD
0
2
4
6
8
10
12
14
16
18
20
0 2 4 6 8 10 12 14 16
VDD(V)
I_
vd
d(
uA
)
I_vdd Startup vs. Temperature
0
2
4
6
8
-20 0 20 40 60 80 100 120
Temp (C)
I_
vd
d
(u
A)
VDD UVLO and Ops Current
0
0.5
1
1.5
2
2.5
3
0 4 8 12 16 20 24 28
VDD (V)
I_
VD
D
(m
A)
VDD Operation Current vs. Load
1
2
3
4
5
6
0 500 1000 1500 2000
Gatedrive Loading (pf)
I(
VD
D)
(
mA
)
Fosc 50Khz Fosc 65Khz Fosc 100Khz
UVLO(enter) vs. Temp
9.3
9.4
9.5
9.6
9.7
9.8
9.9
-20 0 20 40 60 80 100 120
Temp (C)
UV
LO
(e
nt
er
)
(V
)
UVLO(exit) vs. Temp
15.8
15.9
16
16.1
16.2
16.3
16.4
16.5
16.6
-20 0 20 40 60 80 100 120
Temp (C)
UV
LO
(e
xi
t)
(
V)
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- 8 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
Fosc vs. RI
0
20
40
60
80
100
120
140
50 70 90 110 130 150 170 190 210 230 250
RI (Kohm)
Fo
sc
(
Kh
z)
Fosc vs. Temperature
64
64.5
65
65.5
66
66.5
67
67.5
-20 0 20 40 60 80 100 120
Temp (C)
Fo
sc
(
Kh
z)
Vth_OC(V) vs Ivin(uA)
0.6
0.7
0.8
0.9
1.0
0 50 100 150 200 250 300
Ivin(uA)
V
th
_O
C
(V
)
I_RT vs. Temp
69
69.2
69.4
69.6
69.8
70
70.2
70.4
70.6
-20 0 20 40 60 80 100 120
Temp (C)
I_
RT
(
uA
)
w/
RI
=1
00
Ko
hm
Ivdd_lacth(uA) vs Vdd(V)
30.0
35.0
40.0
45.0
50.0
7.5 7.8 8.1 8.4 8.7 9.0
Vdd(V)
Iv
dd
_l
ac
th
(u
m
A
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- 9 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
OPERATION DESCRIPTION
OB2279 is a highly integrated PWM controller IC
optimized for offline flyback converter applications
with requirement in latch shutdown or auto recovery.
The extended burst mode control greatly reduces the
standby power consumption and helps the design
easily meet the international power conservation
requirements.
z Startup Current and Start up Control
Startup current of OB2279 is designed to be very low
so that VDD could be charged up above UVLO(exit)
threshold level and device starts up quickly. A large
value startup resistor can therefore be used to
minimize the power loss yet reliable startup in
application. For a typical AC/DC adaptor with
universal input range design, a 2 MΩ, 1/8 W startup
resistor could be used together with a VDD capacitor
to provide a fast startup and yet low power
dissipation design solution.
z Operating Current
The Operating current of OB2279 is low at 2.3mA.
Good efficiency is achieved with OB2279 low
operating current together with extended burst mode
control schemes.
z Frequency shuffling for EMI improvement
The frequency Shuffling/jittering (switching
frequency modulation) is implemented in OB2279.
The oscillation frequency is modulated with a
internally generated random source so that the tone
energy is evenly spread out. The spread spectrum
minimizes the conduction band EMI and therefore
eases the system design in meeting stringent EMI
requirement.
z Burst Mode Operation
At zero load or light load condition, most of the
power dissipation in a switching mode power supply
is from switching loss of the MOSFET transistor, the
core loss of the transformer and the loss in the
snubber circuit. The magnitude of power loss is in
proportion to the number of switching events within
a fixed period of time. Reducing switching events
leads to the reduction on the power loss and thus
conserves the energy.
OB2279 self adjusts the switching mode according to
the loading condition. At no load or light load
condition, the FB input drops below burst mode
threshold level. Device enters Burst Mode control.
The Gate drive output switches only when VDD
voltage drops below a preset level and FB input is
actived to output an on state. Otherwise the gate
drive remains at off state to minimize the switching
loss thus reduce the standby power consumption to
the greatest extend.
The nature of high frequency switching also reduces
the audio noise at any loading conditions.
z Oscillator Operation
A resistor connected between RI and GND sets the
constant current source to charge/discharge the
internal cap and thus the PWM oscillator frequency
is determined. The relationship between RI and
switching frequency follows the below equation
within the specified RI in Kohm range at nominal
loading operational condition.
)(
)(
6500 Khz
KohmRI
FOSC =
z Current Sensing and Leading Edge Blanking
(LEB)
Cycle-by-Cycle current limiting is offered in
OB2279 current mode PWM control. The switch
current is detected by a sense resistor into the sense
pin. An internal leading edge blanking circuit chops
off the sense voltage spike at initial MOSFET on
state due to snubber diode reverse recovery so that
the external RC filtering on sense input is no longer
needed. The current limit comparator is disabled and
cannot turn off the external MOSFET during the
blanking period. The PWM duty cycle is determined
by the current sense input voltage and the FB input
voltage.
z Internal Synchronized Slope Compensation
Built-in slope compensation circuit adds voltage
ramp onto the current sense input voltage for PWM
generation. This greatly improves the close loop
stability at CCM and prevents the sub-harmonic
oscillation and thus reduces the output ripple voltage.
z Over Temperature Protection with Latch
Shutdown(Only to T and L version)
A NTC resistor in series with a regular resistor
should be connected between RT and GND for
temperature sensing and protection. NTC resistor
value becomes lower when the ambient temperature
rises. With the fixed internal current IRT flowing
through the resistors, the voltage at RT pin becomes
lower at high temperature. The internal OTP circuit
is triggered and shutdown the MOSFET when the
sensed input voltage is lower than VTH_OTP.
OTP is a latched shutdown.
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- 10 - OB_DOC_DS_79A1
OB2279
Current Mode PWM ControllerFreq Shuffling with Latch Shutdown
z RT Pin Used as Latch Shutdown Input
Control
RT pin could also be used as a control input to
implement system latch shutdown function.
An example is to implement system OVP protection
with a latch shutdown function through a photo
coupler and affiliated circuits. When OVP detection
signal connected to RT is lower than VTH_OTP for
Version T/L device, (or VTH_OT_Latch for Version
V), OB2279 controls system into latch shutdown.
The recovery of the AC/DC system could only start
by resetting internal latch when VDD voltage drops
below VDD_De-latch value. This could be achieved
by unplugging/re-plugging of AC source in AC start-
up configuration.
z Gate Drive
OB2279 Gate is connected to the Gate of an external
MOSFET for power switch control. Too weak the
gate drive strength results in higher conduction and
switch loss of MOSFET while too strong gate drive
output compromises the EMI.
Good tradeoff is achieved through the built-in totem
pole gate drive design with right output strength and
dead time control. The low idle loss and good EMI
system design is easier to achieve with this dedicated
control scheme. An internal 16.5V clamp is added for
MOSFET gate protection at higher than expected
VDD input.
z Protection Controls
Good system reliability is achieved with OB2279’s
rich protection features including Cycle-by-Cycle
current limiting (OCP), Over Load Protection (OLP)
with auto-recovery(V and T version) or latch
shutdown(L version), over temperature protection
(OTP) with auto-recovery(V version) or latch
shutdown(T and L version), on-chip VDD over
voltage protection (OVP) with latch shutdown and
under voltage lockout (UVLO).
VDD OVP protection is a latched shutdown in
OB2279.
The OCP threshold value is self adjusted lower at
higher current into VIN pin. This OCP threshold