Final Project Enhanced Music Synthesizer and Display：项目最终增强音乐合成器和显示

Final Project Enhanced Music Synthesizer and Display：项目最终增强音乐合成器和显示 EE108A – Digital Systems I Final Project Winter 06 – 07 Final Project: Enhanced Music Synthesizer and Display Introduction The final project will provide you with a complete digital systems design experience. It encompasses all of the elements you have encountered in EE108A: , combinational and sequential logic , high level module design , timing considerations , user, memory and device I/O , employing the right tools and strategies for testing , debugging, debugging and debugging Most importantly, this project gives you the chance to build a system of your own design. Due Dates: thCheckpoint 1: Monday, March 5, 2007 thCheckpoint 2: Monday, March 12, 2007 th,Submission: Saturday, March 17 2007 files due at noon, report due at midnight thDemonstrations: Sunday, March 18, 2007, Packard 127 (time to be decided) Project Overview By the end of lab 5, you should have a working system on the Xilinx Virtex II Pro FPGA board that plays a song stored in memory using pure tones (sine waves), and displays the waveform being played on a VGA monitor. For the project you are to extend this basic music player, implementing additional sound effects, display functionality, and/or interface modes. A list of features and the points associated with each is included in this handout. Your grade will be determined by the number of extensions (number of points) you implement, the quality of your implementation, a demonstration of your system, an oral presentation and a written report. Your final project should be implemented with good design and coding style, it should work as defined and summarized in a well organized report. Extra credit will be awarded for more than 15 points worth of features. To maximize your probability of success, adopt a rigorous design methodology (no shortcuts like not simulating modules) and a strict timeline. These will ensure a timely completion, with minimal chance of needing a complete redesign near the due date. To make sure you are on track, there will be two graded checkpoints in which the course staff will check on your progress and give you feedback. Since all the components of the project, i.e. check points, code submission, project report, demonstration, and presentation contribute to the final project grade, it is imperative that you manage your time wisely and plan to give each component adequate attention. In the remainder 1 EE108A – Digital Systems I Final Project Winter 06 – 07 of this handout further information is provided on the project’s grade breakdown, schedule, deliverables and implementation details. Grading The grade breakdown for the project is as follows: , Checkpoint 1 – 10% , Checkpoint 2 – 10% , Project submission (Verilog files, simulations, and functionality) – 60% , Report – 10% , Presentation and polish – 10% Project Schedule Checkpoint 1 The first checkpoint for the project is one week after the project is assigned. For this checkpoint you should have completed the following: , Complete block diagrams of your system, including detailed interface specifications listing all signals and describing their timing , State diagrams for all FSMs , Timing table(s) showing all non-trivial system timing The block diagrams should indicate how you plan to partition the overall system into more manageable sub-systems by function, as well as how they relate to and interact with one another. Timing tables detail how actions are sequenced in time. They will be especially helpful when dealing with audio, video, and memory events, which occur at well defined time intervals. Groups will sign up for 20 minute meetings with the course staff to review their progress. Sign up for the earliest time you can make so you’ll get feedback sooner! Checkpoint 2 The second checkpoint is one week after checkpoint 1. At this point you must demo the following: , Successful simulation of all parts that can be simulated , At least 2/3 of your features must be working in the lab on the FPGA board In order to fulfill the checkpoint requirements, it is advisable to work incrementally and save a copy of your design files in a repository each time you add a feature or a significant part thereof. This way, if you break your system just before the check point, you would still be able to demonstrate the features you previously had working. Groups will need to demonstrate their working features and show their simulations in lab to the TAs for credit. 2 EE108A – Digital Systems I Final Project Winter 06 – 07 Project Submission You must submit all your project files, your final .bit file, and your project report electronically. Note that you will use this exact .bit file when you demo. This means the due date is absolute. You will not be able to make last minute changes. Project Deliverables Project Files Your project submission should include: , All synthesizable Verilog files defining your system. , All files pertaining to any memory modules used, i.e. ROMs, RAMs, and any spreadsheets you used to generate them. , The Xilinx project file along with a *.bit file that encapsulates the final version of your system. , All testbenches you wrote and used to verify your design along with any ModelSim *.do files. It is recommended that you organize your files in the same manner as the lab files, i.e. files of synthesizable Verilog code in the top-level folder, Xilinx ISE project files in the ise subfolder (remember to clean up project files in Xilinx before submitting), ModelSim *.do files and subfolder. Verilog testbenches in the sim Project Demonstration The demonstrations will take place in the lab. During this session you will have exactly 8 minutes to demonstrate each of your features to the staff. The performance and behavior of your system will be checked against the specifications and requirements in this document. You will use the same .bit file you submitted on the project due date. (I.e., you can’t stay up all night finishing it the day before the demo.) During your demo you should make sure you clearly list the features you implemented, if they meet the requirements, any special features you’ve added, and describe (briefly) how you implemented them. Don’t worry about the fact that everyone else probably did chords the same way: you’re being graded on your presentation so it should be complete and compelling. Prepare ahead of time the best demo you can to show off your project and your understanding of it in the best possible light. This is worth 10% of your grade. Project Report Along with the Verilog files submitted, you are also required to electronically submit a report with a maximum length of 5 pages including figures. Please adhere to this length restriction. Points will be deducted for reports that are too long. The purpose of the report is to convey what you did, how you did it, and what you learned. Topics in the report should include the following: , Specification: a description of each extension you implemented, and the number of points it is worth. (List these at the beginning of your report.) 3 EE108A – Digital Systems I Final Project Winter 06 – 07 , High-level design: describe your block diagram and overall functionality. , Key implementation details: describe aspects of your design that you think are noteworthy. Include design techniques and timing that is particularly clever or subtle. , Brief descriptions of any problems encountered during design and how you resolved them. Remember, your report may not exceed 5 pages! You need to condense the design, implementation, and functionality of your project into at most 5 pages. Have I mentioned the 5 1page limit? Audio Implementation and Additional Feature List Audio Data Specification Unlike labs 4 and 5, the format of the data inside the note memory for the project employs a more elaborate specification, analogous to a MIDI file. This is done in order to make the realization of a wider range of acoustic effects possible. More specifically, the note memory will be 18 bits wide by 512 entries long, providing 4 songs of 128 notes each (you can make it longer if needed by instantiating larger ROMs). Each entry will have one of two formats: , 0 xxxxxx yyyyyy zzz ww– schedule note xxxxxx (6 bits) to be played for duration thyyyyyy (6 bits) 48 notes with an amplitude of zzz (3 bits) and voice ww (2 bits) starting ththat the current time. We use 48 notes as our time basis to allow both 16 notes and triplets to be encoded. The amplitude is used if you choose to include dynamics. th, 1 yyyyyy 000000 000 00 – advance time by yyyyyy (6 bits) 48 notes. This format allows us to play multiple notes at the same time and to have some notes held for longer than others. For example, to play a C-major cord for one quarter note and then play an E (single note) for a half note we would encode: th, 0 C 12 – Play C for 12 48 notes, ? note th, 0 E 12 – Play E for 12 48 notes, ? note th, 0 G 12 – Play G for 12 48 notes, ? note th, 1 12 – Advance time for 12 48 notes , 0 E 24 – Play E for ? note , 1 24 – Advance time ? bar The first three entries schedule three notes to be played starting at the current time. The fourth entry advances time. While time advances, the scheduled notes are played. All notes don’t have to start and end at the same time. For example, suppose we want to hold a C through a bar and play E-G-E for ? note each on the 2-3-4 count. We would encode this as: 1 You may think I’m belaboring this point, but for the past two quarters at least one group per quarter has decided that 5 pages really means something other than 5 pages. They lost points for this. 4 EE108A – Digital Systems I Final Project Winter 06 – 07 , 0 C 48 – Play C for a whole bar , 1 12 – Advance ? bar , 0 E 12 – Play E for ? bar , 1 12 – Advance ? bar , 0 G 12 – Play G for ? bar , 1 12 – Advance , 0 E 12 – Play E for ? bar Note that in addition to your enhancements you will need to modify the music player to handle this new note file format. You are advised to modify the provided spreadsheet to make it easier for you to generate songs in this new format. (This is easy and will save you a huge amount of time.) Note that the time-advance format has a lot of unused bits. You could do something cool with them...like encode text to go along with the notes, or control the reverb length, or maybe something even more creative. Design a la Carte You only have three requirements for additional features for the final project: implement the chords feature below and at least one feature from each of the Display and Interface sections below. The rest of this section presents the additional features you may choose from to implement for your final project. Each feature has an associated maximum number of points it can garner. To get full credit you need to successfully implement 15 points worth of features. (Note: if your group has three people you will need to do an additional 5 points of features.) You are welcome to propose your own enhancements to the music generator or the VGA display not listed in this handout. For these please consult the staff to get approval and point value. Audio: Reverberation (2-4 points) – This addition should create an “echo” to the sound being played by combining an attenuated and delayed version of the output (not the note) being fed to the output. The delay should be in the range of 100ms to 500ms. Basic reverb is worth 2 points. If you add user controls for adjusting the length and attenuation you can get 2 additional points. Note that your reverb should continue until the last sound dies away. That is, it should not just echo once. You should make sure that your reverb behaves correctly when the player is paused, when the song is done, and during rests. In all cases it should continue to generate sound until the reverb dies out. REQUIRED: Chords (5 points) – Allow your music player to play multiple (at least 3) notes simultaneously. Your design will need to generate multiple waveforms (one for each note in the chord) and combine them into a single audio sample to feed to the codec. Please note that choosing which note player to use for the next note is combinational logic and you should not need an FSM for this. Harmonics (5 points) – Add weighted harmonics (multiples of the fundamental frequency) to the note being played. Different weights will give different instrument sounds to the music. You 5 EE108A – Digital Systems I Final Project Winter 06 – 07 can make a flute sound, a violin sound, a trumpet sound, or an electric guitar with distortion with the proper use of harmonics (and dynamics – see the next item). This is similar to playing chords, except the frequencies of the additional notes are multiples of the base note and the amplitudes of the higher harmonics are necessarily lower. (This is by far the coolest addition.) Simple Dynamics (3 points) – Modulate the signal amplitude during the time the note is played. The signal amplitude should increase linearly from zero to the specified value (zzz) during the attack interval and then decay exponentially during the decay period. I.e., a very short note may not have much decay whereas a long one will decay to almost nothing. You will need to decide how to generate this amplitude “envelope” (a ROM is a good approach) and how to use it to modulate the waveform. At the maximum value point the volume should be the zzz value specified in the song format. You should provide a song which clearly demonstrates the effect of the dynamics. Advanced Dynamics (5 points) – In addition to the features of the simple dynamics, you must include the ability to specify the length of the attack and decay periods in 48ths. This can either be done on a per-note basis in the song ROM or via switches on the board. Build in multiple dynamics profiles that provide different effects. Funky Dynamics (2 points) – These effects must be either user selectable via switches or programmed in the song. You should clearly demonstrate the differences. Multiple Voices (4-5 points) – This involves having he ability to play multiple instruments (notes or chords) simultaneously, with different harmonics and possibly different attack and decay envelopes. You should use the note format to specify the voice for each note, and you should provide a song that makes the multiple voices clear. For the full 5 points the dynamics should be able to change with the voice either via the voice from the song rom or via switches on the board. If you are not implementing the full dynamics then you must implement the zzz per-note volume to get the full points for multiple voices. Special Effect Voices (5 points) – Modify your design so you can select from the regular voice or one of two special-effect voices. When a special effect voice is selected your sine player will not be used and you will instead step through a ROM which contains a sampled sound. For higher-frequency notes you will step through the ROM faster and therefore play the sound higher (and shorter). This won’t work perfectly as a long high-pitched note will either repeat the sampled sound or cut off early. Good examples of samples to use are drums, famous cartoon character voices, and the like. It’s your responsibility to get the sample into the correct format and load it into a ROM file. (Matlab is a good way to read in WAV files.) Display: Adjustable waveform display (2 points) – By using the available push buttons on the Xilinx FPGA board, allow the horizontal and vertical scale of the waveform display from lab 5 to be adjusted in real time. This does not mean changing the size of the display from lab 5. For example, when you zoom out in the horizontal direction you should display more than 256 samples. When you zoom in vertically you should show only part of the wave (probably centered at 0). You will need to figure out the details to make this a cool feature. Note display (2 points) – This additional feature should display the note or chord currently being played as text on the screen. 6 EE108A – Digital Systems I Final Project Winter 06 – 07 Enhanced note display (2-4 points) – For this item your system should display the few notes or chords most recently played and the few notes or chords soon to be played along with the current note. The sequence of notes can be displayed using characters or a graph with time along the horizontal direction and pitch along the vertical direction. You can get up to 2 points if you just display the previous notes or the next notes, and up to 4 points if you do both. Enhanced waveform display (1 points) – Draw each note in a different color on the display and show the combined waveform in white. This is really easy and really cool. You should figure out how to prevent your combined display from freezing when it is only playing a single note after a chord. Interface: Playback control (2 points) – Add play, pause, fast-forward, and rewind functionality to your player. When rewinding you do not have to obey delays perfectly, but if you do we will give extra points. Composition editor (5 points) – This feature entails a user interface that allows the composition currently stored in the note memory to be edited by the user. Interactive Instrument Editing (5points) – This item should provide a means to interactively allow the user to edit: , The weighting of harmonics and/or , The attack and decay values used in dynamic amplitude modulation. MIDI reader (8 points) – Create a module that can read a standard MIDI file stored in a RAM. You’ll have to look up the MIDI file spec, but this will allow you to play any MIDI file you can find online. Friendly Suggestions There are a lot of these, but there’s also a lot of good hints in here. Plan on re-reading them a few times while working on the project as they won’t all make sense at the beginning. (And don’t be surprised if the TAs tell you to look here for answers to a lot of your questions.) Make sure you fully understand the requirements of each feature you plan to implement before committing to it. List its I/O requirements, points of change in the current music player and high level event and data flow. Don’t bite off more than you can chew. It is better to have a fully functional set of features worth 15 points, than to have a partial implementation with a potential of 18. When you demo your design, a partially working feature will look really bad. Visit office hours and ask questions early in the development stage. Don’t start coding before you have a complete module breakdown, including control and data interfaces. The most important thing is to understand the data flow and timings. Keep your code simple. If your case statement doesn’t fit on a single screen page (width and length) it is probably too complicated. Break it down with intermediate values and give them meaningful names. This will also assist in testing and debugging. 7 EE108A – Digital Systems I Final Project Winter 06 – 07 Add features incrementally. Before working on the next feature, make sure the current design runs smoothly on the FPGA, and save a copy of it. If you can, add features first using the switches on the FPGA board to control them so you can test them. Once that is working, then hook them up to the song ROM. (E.g., voice, dynamics, volume, etc.) Keep as much precision for as long as you can. I.e., if you are adding 3 16-bit signals, make the result be 18 bits so you can keep all the data. Only when you need to (i.e., at the end, or if your design is too slow) should you throw out bits. If you do this you will be able to adjust your final volume so you get a strong signal without clipping by picking the correct bits near the end. xxFractional multiplication can be thought of as multiplying by (2-1)/(2). That is, if you have a 4- bit number and you want to interpret that as a fraction you will multiply by 0000 to 1111 (0 to 15) and then shift right by 4 (divide by 16) so you effectively have a range of 0/16 to 15/16. Not that if you have only a 3 bit number this means the closest you can get to 1 is 7/8, which is 13% below 1. By default Verilog interprets everything in your project as unsigned. This means if you shift you will need to manually extend the sign bit and if you multiply you will need to manually deal with the case where one number is negative. Our tools supposedly support the “signed” attribute to handle this case. I.e., if you define a register as “reg signed [15:0]” a then if you multiply it by another signed register and assign the result to a signed register you should get a correct singed multiplication. Similarly, if you have a signed value and use the >>> operator it should do a sign-extended right shift. I haven’t actually tried this so you should double-check it. You will need to pipeline your design. Make sure you always check your timing when you synthesize in Xilinx. If you do not meet the timing requirements for our 100MHz clock you will have to figure out what your critical path is and insert flip flops to break it up. If you do not meet timing Xilinx will happily synthesize a .bit file for you and you can download it to the board, but it may not work correctly and you will not be able to figure out why. (Note: changing the .ucf file does not change the clock. All it does is till the Xilinx tools what clock it has to meet.) Further, since the synthesis process is very complicated, you may get very different results from one synthesis to another. One reasonable approach to fixing timing problems is to put flip-flops on all the inputs of all modules. This will insure that when you hook modules together you don’t end up with really long chains of combinational logic. If your design does not meet timing then you must find and fix your critical path. There are two approaches to pipelining: 1) The guess and check approach. Make a relatively (un)educated guess as to which part of your design is slow and add flip-flops to see if it helps. When it doesn’t, you’ve just messed up your code, and you probably messed up your control flow by forgetting to put in a flip-flop on a control signal anyway. Undo all the work you just did and try approach 2 below. 2) The measure and analyze approach. Run the Xilinx Post-place and route timing analyzer. Then choose “analyze against auto-generated constraints.” This will show you your top ten worst paths. Take out your block diagram from checkpoint 1 and trace the worst path on your block diagram. Figure out from the timing analysis and your block diagram where it is easy and reasonable to break up your path. (Remember you would like to break it up evenly, but sometimes that isn’t easy. In 8 EE108A – Digital Systems I Final Project Winter 06 – 07 any case you need to make sure that no part of your new path is longer than 10ns. The timing report will show you the time of the logic and the wires along your path.) Decide where to put in your flip fops. On your block diagram, look at any other control or data signals that are supposed to be in sync with the path you are pipelining and make sure you have exactly the same number of flip flops on those paths so all the data arrives together at the end. Add your flip flops, re-check your timing, and you’re done. Good luck. 9