怎样查看.map文件

文文: D:\s0l(注注）.map 2008-11-21, 11:31:28盛盛盛 78K/0 Series Linker V3.80 Date:22 Feb 2008 Page: 1 Command: -flcd.plk Para-file: -yC:\NECTools32\DEV\ -olcd.lmf "C:\Program Files\NEC Electronics Tools\LIB78K0\s0l.rel" -bcl0x.lib -bcl0.lib -bcl0f.lib -s lcd.rel lcd_wait.rel main.rel option.rel Out-file: lcd.lmf Map-file: s0l.map Direc-file: Directive: *** Link information *** 22 output segment(s) 在lmf文文文文文文文文文文 1635H byte(s) real data lmf文文文文文文（字字） 1206 symbol(s) defined *** Memory map *** SPACE=REGULAR 存存存存存文存存 MEMORY=ROM 以以以以以ROM存存 BASE ADDRESS=00000H SIZE=08000H 开开开开以00000H，存存空空以08000H。 OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS @@VECT00 00000H 00002H CSEG AT 文文输lmf文文文文存 开开开开以0000H，空空以0002H字字 CSEG AT以为文文为为，可可 见文见U17198EJ1V0UM0 0表3-3 @@VECT00 @cstart 00000H 00002H * gap * 00002H 00004H gap表表表表文存存以存 @@VECT06 00006H 00002H CSEG AT @@VECT06 main 00006H 00002H * gap * 00008H 00006H @@VECT0E 0000EH 00002H CSEG AT @@VECT0E main 0000EH 00002H * gap * 00010H 00010H @@VECT20 00020H 00002H CSEG AT @@VECT20 main 00020H 00002H * gap * 00022H 00002H @@VECT24 00024H 00002H CSEG AT @@VECT24 main 00024H 00002H * gap * 00026H 00006H 页: 1 文文: D:\s0l(注注）.map 2008-11-21, 11:31:28盛盛盛 @@VECT2C 0002CH 00002H CSEG AT @@VECT2C main 0002CH 00002H * gap * 0002EH 0000AH @@VECT38 00038H 00002H CSEG AT @@VECT38 main 00038H 00002H 以以表以以以以文以文以以文，在main.c 文以以文文以以文。 * gap * 0003AH 00006H @@CALT 00040H 00000H CSEG CALLT0 @@CALT @cstart 00040H 00000H @@CALT lcd 00040H 00000H 78K/0 Series Linker V3.80 Date:22 Feb 2008 Page: 2 @@CALT main 00040H 00000H 为以以以CALT区文区以区区 * gap * 00040H 00040H 从40H开开文40H个开开个个以以存，没没区以CALT函文 O 00080H 00005H CSEG AT OPPT option 00080H 00005H 表以以表表从80H开开文5个字字个个个，以OPPT文，也也以为也也文option-byte以以 ， 与在与与文以以以与与文，为此与文，option-byte以以与与部以： OPPT CSEG AT 0080H OPTION: DB 00H DB 00H ; 1.59 V POC mode DB 00H ; Reserved area DB 00H ; Reserved area DB 02H ; On-chip debug operation disabled END option-byte以以与与部部 @@R_INIS 00085H 00000H CSEG UNITP @@R_INIS @cstart 00085H 00000H @@R_INIS lcd 00085H 00000H @@R_INIS main 00085H 00000H @@R_INIS @rom 00085H 00000H 以上以@@R_INIS文文段段，为文以此此此没此此文sreg变文，关此关个文文关以，可可 见 文见U17200EJ1V0UM00，P528，表B-1。 * gap * 00085H 00001H 表字字文存此存存 @@R_INIT 00086H 0008AH CSEG UNITP @@R_INIT @cstart 00086H 00000H @@R_INIT lcd 00086H 00002H @@R_INIT main 00088H 00088H @@R_INIT @rom 00110H 00000H 以上以@@R_INIT文文段段，为文以此此此没此此文文文 @@CNST 00110H 0001AH CSEG UNITP @@CNST @cstart 00110H 00000H @@CNST lcd 00110H 00000H @@CNST main 00110H 0001AH 以上以@@CNST文文段段，为文以此此此const型变文 @@LCODE 0012AH 005F2H CSEG 页: 2 文文: D:\s0l(注注）.map 2008-11-21, 11:31:28盛盛盛 @@LCODE @cstart 0012AH 00076H @@LCODE @hdwinit 001A0H 00001H @@LCODE sprintf 001A1H 00557H @@LCODE exit 006F8H 00024H 以上以@@LCODE文文段段，为文以此此此此函文此此 @@CODE 0071CH 00F41H CSEG @@CODE lcd 0071CH 002BEH @@CODE main 009DAH 00C83H 以上以@@CODE文文段段，为文以此此此此此 ?CSEG 0165DH 0004BH CSEG ?CSEG lcd_wait 0165DH 0004BH 在在文文lcd_wait.asm文以以文CSEG文 @@CALF 016A8H 00000H CSEG @@CALF @cstart 016A8H 00000H @@CALF lcd 016A8H 00000H @@CALF main 016A8H 00000H CALF函文区 * gap * 016A8H 06958H MEMORY=BANK0 BASE ADDRESS=08000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS BANK0区 * gap * 08000H 04000H MEMORY=IXRAM BASE ADDRESS=0E000H SIZE=01800H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 0E000H 01800H 个以内内RAM区 MEMORY=LRAM BASE ADDRESS=0FA00H SIZE=00020H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 0FA00H 00020H buffer RAM区 MEMORY=RAM 个以RAM区＋SFR区 BASE ADDRESS=0FB00H SIZE=00500H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS @@DATA 0FB00H 0009AH DSEG UNITP @@DATA @cstart 0FB00H 00078H @@DATA lcd 0FB78H 00000H @@DATA main 0FB78H 00022H @@DATA @rom 0FB9AH 00000H 以上以@@DATA文文段段，为文以此此此此此此文文文 @@INIT 0FB9AH 0008AH DSEG UNITP @@INIT @cstart 0FB9AH 00000H @@INIT lcd 0FB9AH 00002H @@INIT main 0FB9CH 00088H 页: 3 文文: D:\s0l(注注）.map 2008-11-21, 11:31:28盛盛盛 @@INIT @rom 0FC24H 00000H 以上以@@INIT文文段段，为文以此此此没此此文文文 * gap * 0FC24H 001FCH @@INIS 0FE20H 00000H DSEG SADDRP @@INIS @cstart 0FE20H 00000H @@INIS lcd 0FE20H 00000H @@INIS main 0FE20H 00000H @@INIS @rom 0FE20H 00000H 以上以@@INIS文文段段，为文以此此此没此此文sreg型变文 @@DATS 0FE20H 00000H DSEG SADDRP @@DATS @cstart 0FE20H 00000H @@DATS lcd 0FE20H 00000H @@DATS main 0FE20H 00000H @@DATS @rom 0FE20H 00000H 以上以@@DATS文文段段，为文以此此此没此此此文sreg型变文 @@BITS 0FE20H 00000H BSEG @@BITS @cstart 0FE20H.0 00000H.0 @@BITS lcd 0FE20H.0 00000H.0 @@BITS main 0FE20H.0 00000H.0 以上以@@BITS文文段段，为文以此此此此此型（位）变文 * gap * 0FE20H 00098H * @@RTARG0 0FEB8H 00008H DSEG AT @@RTARG0 @RTARG0 0FEB8H 00008H 以上以@@RTARG0文文段段，为文以此此 * gap * 0FEC0H 00040H * gap (Not Free Area) * 0FF00H 00100H SFR区 MEMORY=BANK1 BASE ADDRESS=18000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 18000H 04000H MEMORY=BANK2 BASE ADDRESS=28000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 28000H 04000H MEMORY=BANK3 BASE ADDRESS=38000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 38000H 04000H MEMORY=BANK4 BASE ADDRESS=48000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS * gap * 48000H 04000H MEMORY=BANK5 BASE ADDRESS=58000H SIZE=04000H OUTPUT INPUT INPUT BASE SIZE SEGMENT SEGMENT MODULE ADDRESS 页: 4 文文: D:\s0l(注注）.map 2008-11-21, 11:31:28盛盛盛 78K/0 Series Linker V3.80 Date:22 Feb 2008 Page: 4 * gap * 58000H 04000H Target chip : uPD78F0547_80 Device file : V2.10 � 页: 5