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fax id: 3612 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 4, 1996 - Revised July 24, 1997 Layout and Termination Techniques For Cypress Clock Generators Cypress Semiconductor makes a variety of PLL-based clock generators. This application note provides a set of recom- mendations to optimize usage of Cypress clock devices in a system. The application note begins with recommended ter- mination techniques for clock generators. Subsequently, pow- er supply filtering and bypassing is discussed. Finally, the ap- plication note provides some recommendations on board layout. Summary of Transmission Line Theory Typically, Cypress clock generators have low output imped- ances. When these devices drive loads with large input im- pedances, there is an impedance mismatch between the low-impedance source and high-impedance load. Under cer- tain conditions, this causes voltage reflections to occur from the load, thus resulting in overshoot and undershoot of the signal. Ultimately, this results in less-than-optimum system operation. When do Voltage Reflections Occur? Simply put, voltage reflections can occur when the PCB trace starts behaving as a transmission line and there is an imped- ance mismatch between the trace and the load. Expressing the first condition mathematically, reflections will occur when: Eq. 1 where L is the length of the trace, tr is the rise time of the signal and tpd is the propagation delay of the signal through the trace. Under these conditions, a trace starts behaving as a trans- mission line. Once this occurs, signals will be reflected from the load if the energy of the signal is not completely dissipated along the trace. Such reflections result in signal overshoot and undershoot. Our objective is to reduce this overshoot and undershoot to within acceptable limits, such that system noise margins are not affected, and spurious clocking does not oc- cur. Table 1 shows the various trace lengths at which reflections begin to occur. Values in Table 1 assume a 50Ω intrinsic line characteristic impedance, a multilayer PCB using stripline construction on G-10 glass epoxy material with a dielectric constant of 5. These conditions result in an unloaded line propagation delay of 2.27 ns/ft. The rise time is specified be- tween 10% and 90% of the signal swing. Note that if the capacitive loading on the trace is higher (for example, a trace drives multiple loads), or if the signal rise time is faster, reflections will start occurring on shorter traces. How to Reduce Voltage Reflections? Properly terminating the trace will reduce voltage reflections. There are two general strategies for transmission line termi- nation: • Match the load impedance to the line impedance • Match the source impedance to the line impedance From a systems design perspective, the first strategy is pre- ferred, since it eliminates any reflections travelling back to the source, thus resulting in less noise, electromagnetic interfer- ence (EMI), and radio frequency interference (RFI). However, from a practical standpoint, either of the two techniques can be used, depending on the system under design. Common Types of Transmission Lines Microstrip lines and strip lines are two types of transmission lines used in multilayer boards. They are described below. For a complete analysis on other kinds of transmission lines, please refer to the application note, “System Design Consid- erations” available from your Cypress representative. Microstrip Lines A microstrip line (Figure 1) is a strip conductor (signal line) on a PCB separated from a ground plane by a dielectric. If the line’s thickness, width, and distance from the ground plane are controlled, the line’s characteristic impedance can be pre- dicted with a tolerance of ±5 percent. L tr 2tpd -----------< Table 1. Length for Voltage Reflections tr (ns) CD (pF) L (inches) 2 10 4.73 2 20 4.32 2 40 3.74 2 80 3.05 1 10 2.16 1 20 1.87 1 40 1.53 1 80 1.18 0.5 10 0.93 0.5 20 0.76 0.5 40 0.59 0.5 80 0.44 Layout and Termination Techniques for Cypress Clock Generators 2 The formula given in Figure 1 has proven to be very accurate for width-to-height ratios between 0.1:1 and 3.0:1 and for di- electric constants between 1 and 15. The inductance per foot for microstrip lines is Eq. 2 where ZO is the characteristic impedance and CO is capaci- tance per foot. The propagation delay of a microstrip line is Eq. 3 Note that the propagation delay depends only upon the di- electric constant and is not a function of the line width or spac- ing. For G-10 fiberglass epoxy PCBs (dielectric constant of 5), the propagation delay is 1.74 ns per foot. Strip Lines A strip line consists of a copper strip centered in a dielectric between two conducting planes (Figure 2). If the line’s thick- ness, width, dielectric constant, and distance between ground planes are all controlled, the tolerance of the characteristic impedance is within ±5 percent. The equation given in Figure 2 is accurate for W/(b – t) < 0.35 and t/b < 0.25. The inductance per foot is given by the formula Eq. 4 The propagation delay of the line is given by the formula Eq. 5 For G-10 fiberglass epoxy boards, the propagation delay is 2.27 ns per foot. The propagation delay is not a function of line width or spacing. Unloaded and Loaded Line Impedances Adding loads to the transmission line increases the propaga- tion delay of the signal travelling on it. The following formula shows the relationship between the unloaded and load char- acteristic impedances of a transmission line. Eq. 6 where ZL is the impedance of a capacitively loaded transmis- sion line, ZO is the characteristic impedance of an unloaded transmission line, CL is the load capacitance placed at the end of the transmission line, l is the length of the transmission line, and CO is the capacitance per unit length of the trans- mission line. Additionally, the characteristic (intrinsic) capacitance of a transmission line per unit length is expressed as: Eq. 7 where tpd is the propagation delay through a lossless trans- mission line. Table 2 shows the values of intrinsic capacitanc- es for strip lines and microstrip lines on PCBs using G-10 Fiberglass epoxy, with a dielectric constant of 5. Using the values of capacitances calculated in Table 2 and Equation 7, we can calculate the characteristic impedance of a transmission line loaded with 10 pF. This is shown in Tables 3 and 4. Values for different loads and characteristic imped- ances can be calculated in the same manner. Figure 1. Microstrip Line Figure 2. Strip Line Construction L Z0( ) 2C0= tpd 1.017 0.45er 0.67+ ns ft⁄( )= L Z0( ) 2C0= tpd 1.017 er ns ft⁄( )= Table 2. Intrinsic Capacitances of Lines Stripline Microstrip ZO (Ω) 50 75 50 75 tpd(ns/ft) 1.74 1.74 2.27 2.27 CO(pF/ft) 35 23 45 30 Table 3. Loaded Impedances for 50Ω Lines Stripline Microstrip l (inch) ZO(Ω) ZL(Ω) ZO(Ω) ZL(Ω) 4 50 38.73 50 36.69 8 50 43.29 50 41.83 12 50 45.21 50 44.1 Table 4. Loaded Impedances for 75Ω Lines Stripline Microstrip l (inch) ZO(Ω) ZL(Ω) ZO(Ω) ZL(Ω) 4 75 53.04 75 49.41 8 75 61.22 75 58.35 12 75 64.94 75 62.62 ZL Z0 1 CL IC0 ---------+ -----------------------= C0 tpd Z0 -------= Layout and Termination Techniques for Cypress Clock Generators 3 Termination Techniques As mentioned before, we need to properly terminate the trace to reduce voltage reflections. There are three basic types of terminations: series, pull-up/pull-down, and parallel AC. Each has its advantages and disadvantages. Parallel AC termination is usually not rec- ommended for clock generators, since it degrades the rise time of the output clock. However, it can be used with series termination to reduce EMI. Except for series termination, the termination network should be attached to the input (load) that is electrically the greatest distance from the source. Component leads should be as short as possible to prevent reflections due to lead induc- tance. Series Termination Series termination is accomplished by inserting a small resis- tor (typically 10Ω to 75Ω) in series with the transmission line, as close to the source as possible (Figure 3). Series termina- tion is a special case of damping in which the series resistor value plus the clock generator output impedance equals the transmission line impedance. In this case, since there is no energy absorbed at the load (typically, loads have high input impedance) the wave will be reflected back. Using series ter- mination resistors will prevent reflection of this reflected wave from the source. Equation 8 shows the relationship between the output impedance of the clock generator (RO), the series terminating resistance (RS), and the characteristic imped- ance of the loaded transmission line (ZL). Eq. 8 The series terminating resistance can be greater than the dif- ference of the characteristic impedance of the line and the output impedance of the clock generator, resulting in a slightly overdamped condition, which will still prevent reflections from the source. Note that you will need to observe the actual clock waveform and experimentally determine the optimal value of series terminating resistance to be used. A disadvantage of the series-damping technique, as illustrat- ed in Figure 4, is that during the two-way propagation delay time of the signal edges, the voltage at the input to the line is halfway between the logic levels, due to the voltage divider action of RS. The “half voltage” propagates down the line to the load and then back from the load to the source. This means that no inputs can be attached along the line, because they would respond incorrectly during this time. However, you can attach any number of devices to the load end of the line because all the reflections are absorbed at the source. The advantages of series termination are: • Requires only one resistor per line • Consumes little power • Permits incident wave switching at the load after a TO prop- agation delay • Provides current limiting when driving highly capacitive loads; the current limiting also helps reduce groundbounce, and therefore, improve jitter. • The advantages of series termination are: • Requires only one resistor per line • Consumes little power • Permits incident wave switching at the load after a TO prop- agation delay • Provides current limiting when driving highly capacitive loads; the current limiting also helps reduce groundbounce, and therefore, improve jitter. The disadvantages of series termination are: • Degrades rise time at the load due to increased RC time constant, arising from the increased resistance in series with the transmission line. Hence, choosing too high a val- ue of series terminating resistance can cause the rise time of the signal to be very high, resulting in incomplete rail to rail swing. • Should not be used with highly distributed loads. Figure 3. Series Termination RS ZL R0–≥ BA C ZL TORs Figure 4. Series Termination Timing Layout and Termination Techniques for Cypress Clock Generators 4 The low input current required by Cypress CMOS ICs results in essentially no DC power dissipation in the series terminat- ing resistor. The only AC power required is to charge and discharge parasitic capacitances. Series Termination For Multiple Loads If the clock generator is driving multiple loads, series termina- tion can be performed in two ways, as shown in Figures 5 and 6. If the trace length between the two loads is less than 2" at 50 MHz, the loads can be daisy chained as shown in Figure 5. If the distance between the loads is more than 2" at 50 MHz, two separate traces must be driven from the source, each having its own series termination. In this case, the series termination value for each of the traces satisfies Equation 8. This set-up is shown in Figure 6. Pull-Up/Pull-Down Termination Pull-up/pull-down resistor termination is shown in Figure 7. The equivalent Thévenin resistance is Eq. 9 The value of RT is equal to the transmission line’s character- istic impedance. To achieve an overdamped condition, RT can be slightly less than the characteristic impedance of the trans- mission line. The value of R1 and R2 are chosen depending on the current sourcing and sinking characteristics of the clock generator. Additionally, point B in Figure 7 must be biased at the thresh- old voltage of the load, either TTL or CMOS levels. If both resistors are used, DC power is dissipated all the time. If only a pull-down resistor (R2) is used, DC power is dissipat- ed when the input is in the logic HIGH state. Conversely, if only a pull-up resistor (R1) is used, power is dissipated when the input is in the LOW state. Due to these power dissipations, this termination is not recommended. If an unterminated control signal on a PCB is suspected of causing a problem, a resistor whose value is slightly less than the characteristic impedance of the line (e.g., 47Ω) can be connected between the input pin of the load and ground. Be sure that the driver can source sufficient current to develop a TTL high voltage level (2.0V) across the resistor. External Components Figure 8 shows the connections of external components to a Cypress clock generator. External components such as de- coupling capacitors, bulk capacitors, and ferrite beads are re- quired to optimize system operation. Decoupling All decoupling capacitors must be placed on the same side as the component on the PCB. High quality, low-ESR, mono- lithic, ceramic, surface mount capacitors must be used, as they provide best performance. These capacitors must be connected as close to the power supply pins as is physically possible, preferably within 0.25" of the pins. Typically, a 0.1-µF capacitor for every power supply pin of the clock generator will provide adequate decoupling. However, in certain cases, capacitors in the range of 470 pF to 2.2 nF may be required to filter high frequency noise typically caused by odd harmonics of the clock frequency. In this case, select a capacitor which will present an impedance of 1Ω at the problem frequency. Bulk (Bypass) Capacitors A bulk (bypass) tantalum capacitor of value between 10 µF and 100 µF can be used to prevent power supply droop when the clock generator is switching all outputs at the same time with maximum capacitive load. This capacitor can be con- nected to the power supply island supplying the part. Addi- tionally, if a ferrite bead is used in the system, this bulk capac- itor must be placed on the clock generator side of the ferrite bead, as close to the bead as is physically possible. Ferrite Beads Ferrite beads are tricky to use. You may not need to use ferrite beads on the power supply if layout, termination, and filtering are done properly. However, provide pads for ferrite beads on the board, and use a 0Ω resistor if it is not required. Ferrite beads can be used to isolate the power supply island of the clock generator from the board power supply. Use only those ferrite beads which can provide the rated DC current to the VCC island. In addition, the DC impedance of the ferrite bead must be as low as possible, preferably between 0Ω and 5Ω. At the clock frequency, the impedance of the ferrite bead must be relatively high, typically greater than 50Ω under load- ed conditions with DC current flowing through it. (Ferrite beads from Fair-Rite Corp. (P/N 2743021447 and 2743019447) meet the above requirement. Other vendors may have similar products.) The ferrite bead will then present a large impedance at the clock frequency, and will prevent noise due to clock harmonics from spreading in the PCB. Figure 5. Series Termination, Multiple Loads Figure 6. Series Termination, Multiple Loads Figure 7. Pull-Up/Pull-Down Termination Rs Trace Length less than 2” at 50 MHz Rs Rs RT R1R2 R1 R2+ --------------------= R1 A B ZO R2 VCC Layout and Termination Techniques for Cypress Clock Generators 5 The ferrite bead provides noise isolation only. It does not en- hance or degrade the performance of the clock generator. EMI Reducing Capacitors On some integrated clock generators/buffers, EMI reducing capacitors may be required on the output clocks. These ca- pacitors round the rising and falling edges of clock, and there- fore, reduce the EMI radiated from the clock generator. Typi- cally, these capacitors range in value from 4.7 pF to 22 pF. The capacitors to ground can be placed close to the terminat- ing resistor, between the resistor and the load, or directly be- tween the load and ground, close to the load. Crystal Circuitry Cypress clock generators have on-chip crystal oscillator cir- cuitry, and therefore, can accept an external crystal as a ref- erence source. Cypress data sheets will indicate what kind of crystal or external clock can be uses with the clock generator. Please refer to the application note, “Crystal Oscillator Topics” for more details on reference clocks. Power and Ground Planes There are essentially three techniques for laying out power and ground planes on a board. They are described below. Isolated Power Plane for Clock Generator Figure 9 shows the layout diagram for the CY225X and CY226X family of clock generators. In this case, the power plane for the clock generator is isolated from the board pow- erplane by means of a ferrite bead. Additionally, the entire board contains a common ground plane for all parts. This technique provides the maximum isolation for the clock gen- erator’s power supply, and also prevents the clock generator noise from being distributed through the board power plane. Power Plane for High-Speed Components In this case, group all the high-frequency components (pro- cessor, clock generator, chipset etc.) and place them on an isolated power plane. The layout recommendations are exact- ly similar to the previous case. Localized Ground Plane for Clock Generator Alternatively, a common ground plane can be used for the entire board. However, a continuous localized ground plane for the clock generator is created on the component (top) layer of the board. This localized plane then connects directly to the board ground plane by means of the pin connections of the clock generator and at least two additional vias to the board ground plane. Figure 10 shows a clock layout with the local- ized ground plane on the top layer, and vias to the system Figure 8. External Circuit for CY225X, CY226X Family Board VCC FB Decoupling Capacitors Series Terminating Resistors Optional EMI-Reducing Capacitors Bypass Capacitor XTAL with optional Trimming Capacitors OE GND XOUT VDD XIN PCLK PCLK VDD PCLK PCLK VDD S0 GND S1 REF REF VDD IO USB GND GND BCLK BCLK VDD BCLK BCLK BCLK BCLK Layout and Termination Techniques for Cypress Clock Generators 6 ground plane. An isolated power plane for the clock generator is optional in this case, although it is shown in Figure 10. Do not run traces through the localized ground plane, as it will cause small ground loops, and may result in EMI problems at higher frequencies. The main reason for placing a localized ground plane under the clock generator is that it provides an efficient path for RF currents to ground. The ground layer inside the PCB is two or three layers away, and hence may be an inefficient path for these RF currents. Placement and Routing All clock traces must be hand-routed before any other signal. Under no circumstances must the clock traces be auto-rout- ed. Additionally, placement of the clock generator on the board is very important. The following are some tips on place- ment of the clock generator, and routing of the clock signals. Placement • Place the clock generator near the center of the board, and near a chassis ground. • Place the clock generator in a manner to ensure that clock traces do not intersect each other. • Do not use sockets. Place clock components directly