UCC28070 300W Interleaved PFC Pre-regulator Design Review

Application Report SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator Design Review MIchael O'Loughlin ........................................................................ PMP - Power Supply Control Products ABSTRACT In higher power applications to utilize the full line power and reduce line current harmonics PFC Pre-regulators are generally required. In these high power applications interleaving PFC stages can reduce inductor volume and reduce input and output capacitor ripple current. This results in smaller overall magnetic volume and filter capacitor volume increasing the converters overall power density. This is made possible through distributing the power over two interleaved boost converters and the inductor ripple current cancellation that occurs with interleaving, reference [5]. This application note will review the design of a 300W two-phase interleaved power factor corrected (PFC) pre-regulator. This power converter achieves PFC with the use of the UCC28070 interleaved PFC controller, reference [7]. 1 Design Goals The specifications for this design were chosen based on the power requirements of a medium power LCD TV. Table 1. Design Specifications PARAMETER MIN TYP MAX UNITS 85 265VIN RMS input voltage (VIN_MIN) (VIN_MAX) V VOUT Output voltage 390 47 HzLine frequency 63 Hz(fLINE) PF Power factor at maximum load 0.90 POUT Output power 300 W h Full load efficiency 90% fs Individual phase switching frequency 200 kHz 1SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated +– Vin V OUT 12Vto21V Q2 R B2 RA1 R B1 Q1 L2 L1 D2 D1 C OUT R A2 C PCA R RDM T2 C CDR C B2 R PK1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 CAOA CAOBPKLMT GND VAO VINAC VSENSE CSA CSB RT CDR SS GDB GDA IMO VCC RSYNTH VREF DMAX RDM R IMO R PK2 C ZCA R ZCA CPCB C ZCB R ZCB CPV C ZV R ZV C B3 0.1uF 0.1uF C SS T1 T1 T2 RSYN D RA R SA R SB R R R R C FA C FB R FA R FB 220pF 220pF 1k 1k D RB R DMX R RT DB UCC28070 I IN IL1 I L2 CB1 1.2nF C B4 1.2nF R OB R OA 4.7pF C RR 4.7pF C RR D PA2 D PB2 D PA1 D PB1 C TA C TB RTA R TB VCC=13V GDA GDB Schematic www.ti.com 2 Schematic UCC28070 PFC controller in a two-phase average current mode control interleaved PFC pre-regulator. Figure 1. Typical Average Current Mode Interleaved PFC Pre-Regulator 2 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated IN L1 I K(D) = I D D 1 2D K(D) = if D is < 05 = 0.5 1 D - - 2D 1 K(D) = if D is > 0.5 D - D - Duty Cycle K (D )= D I I N /D I L 1 www.ti.com Inductor Selection 3 Inductor Selection One of the benefits of interleaved PFC boost pre-regulators is inductor ripple current reduction that is seen at the input of the converter. The following equations and Figure 2 show the ratio of input ripple current (ΔIIN) to individual inductor ripple current (ΔIL1) in a two-phase interleaved PFC as a function of duty cycle(D). Because of this inductor ripple current cancellation, the designer can allow each inductor to have more inductor ripple current than in a single stage design. (1) (2) (3) Figure 2. Input Inductor Ripple Current Cancellation The boost inductors (L1 and L2) are selected based on the maximum allowable input ripple current. In universal applications (e.g., 85 V to 265 V RMS input) the maximum input ripple current occurs at the peak of low line and for this design the maximum input ripple current was set to 30% of the peak nominal input current at low line. 3SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated OUT IN_MIN PLL OUT V V 2 390V 85V 2 D = = 0.69 V 390 V - - » PLL 2 0.69 1 K(D ) = = 0.55 0.69 ´ - OUT IN_MIN PLL P 2 × 0.3 300W 2 0.3 IL = = 3.0 A V K(D ) 85V 0.90 0.55h ´ ´ ´ D » ´ ´ ´ ´ IN_MIN PLL s V 2 D 85V 2 0.69 L1 = L2 = = 140 H IL × 2.96A 200 kHz ´ ´ ´ ´ » D ´ u f 2 2 IN_MIN OUT IN_MIN OUT s OUT L1_RMS L2_RMS 0IN_MIN V 2sin( ) V V 2sin( )P L1 V12I = I = + V 12 p q q h p æ ö - æ ö ç ÷ ´ ç ÷ ç ÷ ´ ç ÷ ò ç ÷ ´ ç ÷ ç ÷ ç ÷ ç ÷ è ø è ø f 2 2 L1_RMS L2_RMS 0 85V 2sin( ) 390V 85V 2sin( )300W 1 140 H 200kHz 390V2I = I = + 2A 85V 0.90 12 p q q p æ ö - æ ö ç ÷ ´ ç ÷ ´ ç ÷ » ç ÷ ò ç ÷ ´ ç ÷ ç ÷ ç ÷ ç ÷ è ø è ø u MIN MINL1 = L2 = 140 Hu MAX MAXL1 = L2 = 350 Hu MIN MAX AVG AVG L1 + L1 140 H + 350 H L1 = L2 = = = 245 H 2 2 u u u Inductor Selection www.ti.com The following calculations are used to select the appropriate inductance for L1 and L2. Where, variable DPLL is the converter’s duty cycle at the peak of low line operation. Variable K(DPLL) is the ratio of input current to inductor ripple current at the peak of low line operation. ∆IL is the boost inductor ripple current at the peak of low line based on the converters input ripple current requirements. (4) (5) The following equation can be used to calculate total inductor RMS current (IL1_RMS and IL2_RMS). (6) (7) A 140-mH boost inductor from Cooper Electronic Technologies part number CTX16-18060 was chosen for the design. The inductance during normal operation will swing from 140mH to 350mH. (8) (9) The average inductance is calculated for current loop compensation purposes. This will be used in the current loop compensation section of the application note: (10) 4 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated ( ) OUT LINE OUT 2 2 22 OUT OUT 2 P 2 300W 47 HzC = 192 F V (V 0.75) (390V) 292.5V ´ ´ ³ » - ´ - f u OUTC = 200 μF OUT RIPPLE OUT LINE OUT 2 300W 2 P 1 0.90V = = 14.5V V 2 2 C 390V 2π 2 47Hz 200 μFh p ´ ´ » ´ ´ ´ ´ ´ ´ ´f OUT COUT_LF OUT P 300W I = = 0.604A V 2 0.90 390V 2h » ´ ´ ( ) 2 22OUT OUT COUT_HF COUT_LF OUT IN_MIN P 16 V I = I V 6 V 2 h h p æ ö ´ ç ÷ - - ç ÷ ´ è ø ( ) 2 22 COUT_HF 300W 16 390V I = (0.90) 0.604 1.0A 0.90 390V 6 85V 2p æ ö ´ - - » ç ÷ ç ÷ ´ ´ è ø www.ti.com Output Capacitor Selection 4 Output Capacitor Selection The output capacitor (COUT) is selected based on holdup requirements. (11) Two 100-mF capacitors were used in parallel for the output capacitor. (12) For this size capacitor the output peak to peak voltage ripple (VRIPPLE) is: (13) In addition to holdup requirements, a capacitor must be selected so that it can withstand both the low-frequency RMS current (ICOUT_LF) and the high-frequency RMS current (ICOUT_HF). High-voltage electrolytic capacitors generally have both low frequency (100 Hz to 120 Hz) and high frequency RMS current ratings on their data sheets. (14) (15) (16) 5SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated OUT L1 PEAK IN_MIN P 2 I 300W 2 2.97A I = + 1.2 = + 1.2 5.1A 2 V 2 2 × 85V 0.90 2h æ ö æ ö ´ D ´ » ç ÷ ç ÷ ç ÷ ç ÷ ´ ´ ´ è ø è ø OUT IN_MIN DS OUTIN_MIN P 300W 16 V 2 16 85V 2η 0.90I = 2 = 2 1.685A 3 V 3 390V2 V 2 2 85V 2p p ´ ´ - - » ´ ´ ´ ´ ´ ´ OUT D OUT P 300W I = = 0.39A V 2 390V » ´ Power Semiconductor Selection (Q1, Q2, D1, D2) www.ti.com 5 Power Semiconductor Selection (Q1, Q2, D1, D2) The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note (SLUA369), UCC28528 350-W Two Phase Interleaved PFC Pre-regulator, explains how to select power semiconductor components for interleaved PFC pre-regulators using average current mode control techniques, reference [4]. To meet the power requirements of this design IRFB11N50A N channel FETs from IR were chosen for Q1 and Q2. To reduce reverse recovery losses SiC diodes CSD10060G from CREE were chosen for the design. Boost Diode (D1, D2) and FET (Q1, Q2) peak current (IPEAK) calculation: A factor of 1.2 was added to the equation for added design margin. (17) Q1 and Q2 RMS current (IDS) calculation: (18) D1 and D2’s average current calculation (ID): (19) 6 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated S PEAK CT P RS N I 5.1A N = = = 51 N I 0.1A ³ CTN = 50 OUT IN_MINS M PEAK OUT s CT V V 2V 3.7V 390V 85V 2 L = 6.24mH I 5.1AV 390V 0.02 200kHz0.02 50N - - ³ ´ ´ » ´ ´ ´ ´ f ML = 8.25 mH S SA SB PEAK CT 0.9 V 0.9 3.7V 50 R = R = = 32.5 I 0.102A N ´ ´ ´ » W SR = 33.2 W S MAX R MAX R D 33.2 × 0.97 R = 1 k 1 D 1 0.97 ´ W ³ W - - ; P R PEAK R S N 5.1A 1 k V = I R = 103V N 50 ´ W ´ ´ ³ www.ti.com Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB) 6 Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB) The current sense transformer is selected to handle IPEAK and have a peak current sense signal (IRS) of roughly 100 mA. (20) For this design a current sense transformer with a turns ratio (NCT) of 50 was chosen for the design. (21) The magnetizing inductance (LM) of the current sense transformer should be selected or designed so the magnetizing current is less than 2% of the maximum current sense signal. The following equation calculates the minimum LM where VS is the maximum current sense signal voltage. For this design a current sense transformer was designed by Cooper Electronic Technologies (CTX16-18294) with a magnetizing inductance of 8.25 mH. (22) (23) Selection of the current sense resistors (RSA and RSB ) is based on the peak current limit signal (VS) and the peak current on the secondary side of the current sense transformer. A factor of 0.9 was multiplied by the current sense signal to leave room for the 10% PWM ramp that is used to make this design more noise immune at lighter loads. (24) Select a standard resistor for the design: (25) Resistor RR is used to reset the current sense transformer: (26) Current sense transformer’s rectifying diodes (DR) need to be designed to withstand the current sense transformers reset voltage (VR): (27) 7SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated GDA I L1 0A V RSA V OFF 0V Discontinues Current Causes False Current Sense Signal Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB) www.ti.com To improve noise immunity at extremely light loads, a PWM ramp with a dc offset is recommended to be added to the current sense signals. Electrical components RTA, RTB, CTA, CTB, DPA1, DPA2, DPB1, and DPB2 form a PWM ramp that is activated and deactivated by the gate drive outputs of the UCC28070. Resistor ROA and ROB add a DC offset to the CS resistors (RSA and RSB). When the inductor current becomes discontinuous the boost inductors ring with the parasitic capacitances in the boost stages. This inductor current rings through the CTs causing a false current sense signal. Refer to the following graphical representation of what the current sense signal looks like when the inductor current goes discontinuous. Note that the inductor current and VRSA may vary from this graphical representation depending on how much inductor ringing is in the design when the unit goes discontinuous. Figure 3. False Current Sense Signal 8 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated OFFV = 0.2 V ( ) ( )VCC OFF SA OA OB OFF V V R 13V 0.2V 33.2 R = R = = 2.1 k V 0.2V - - ´ » W OAR = 2.05 kW ( ) ( )VCC s OFF DPA2 SA TA TB s OFF V (V 0.1 V +V R 13V (3.7V 0.1 0.2V)+0.6V 33.2 R =R = = 2.62 k V 0.1 V 3.7V 0.1 0.2V - ´ - - ´ - ´ » W ´ - ´ - TA TBR = R = 2.49 kW TA TB SA S 1 C = C = 50 nF R 3 » ´ ´f TAC = 47 nF www.ti.com Current Sense Transformers Setup and Selection (T1, T2, DRA, DRB) To properly select the offset (VOFF) just requires adjusting resistors ROA and ROB to add a dc offset to the current sense resistors, that is high enough to block DRA and DRB from conducting when a false current sense signals is present. This occurs when the inductors are operating with discontinuous inductor current and was described above in detail. Setting the offset to 200 mV is a good starting point and may need to be adjusted based on individual design criteria and the amount of noise and parasitic elements present in the system. (28) (29) Select a standard resistor for the design: (30) (31) Chose a standard resistor for the design: (32) (33) A standard capacitor needs to be chosen for the design: (34) 9SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated S PK1 PK2 REF S V R 3.7V 3.65 kΩ R = = 5.9 k V V 6V 3.7V ´ ´ » W - - 9 9 RT s 7.5 10 Hz 7.5 10 Hz R = = = 37.5 k 200 kHz ´ W ´ ´ W ´ W f RTR = 37.4 kW ( ) ( )DMX RT MAXR = R 2 D 1 = 37.4 kΩ 2 0.97 1 = 35 k´ - ´ - W DMXR = 34.8 kW 3 A R M= W A B OUT VREF R 3V 3MΩ2R = = 23.3 k VREF 390V 3V V 2 ´ ´ » W - - BR = 23.2 kW A B OVP B R + R 3M + 23.2 k V = 3.18V = 3.18V 414V R 23.2 k W W » W Setting Up Peak Current Limiting (RPK1, RPK2) www.ti.com 7 Setting Up Peak Current Limiting (RPK1, RPK2) The UCC28070 has an adjustable peak current limit comparator that can be set up by selecting RPK1 and calculating the required RPK2. For this design to keep the reset voltage of the current sense transformer manageable the peak current sense signal (VS) was set to 3.7 V. (35) Converter Timing and Maximum Duty Cycle Clamp Resistor RRT and RDMX set up converter timing and the maximum PWM duty cycle clamp: (36) A standard resistor was selected for the design: (37) Resistor RDMX was selected to set the maximum duty cycle clamp (DMAX) to 0.97: (38) Chose a standard resistor for the design: (39) 8 Programming VOUT Resistor RA is selected to minimize the error due to VSENSE input bias current and to minimize loading on the power line when the PFC is disabled. Construct resistor RA from two or more resistors in series to meet high voltage requirements. Resistor RB is sized to program the converters output voltage (VOUT). (40) (41) A standard resistor was chosen for the design. (42) The resistor divider formed by RA and RB from the output voltage to the VSENSE pin also sets the over voltage protection threshold (VOVP). (43) 10 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated Vgm = 70 Sm VREF OUT V 3V H = = 0.0077 V 390V » O RIPPLE V VAO 0.03 3.2V 0.03 Z = = 12.3 k V H gm 14.5V 0.0077 70 Sm D ´ ´ » W ´ ´ ´ ´ PV LINE o 1 1 C = = 138nF 2 2 Z 2 2 47Hz 12.3kp p » ´ ´ ´ ´ ´ ´ Wf PVC = 150 nF www.ti.com VINAC Divider Setup 9 VINAC Divider Setup The UCC28070 also requires sensing the line input for proper operation. This requires a divider from the rectified line voltage to the VINAC pin of the UCC28070. For simplicity the UCC28070 was designed to use the same resistor divider values as the VSENSE pin. Resistors RA and RB need to be the same ratio for the VINAC voltage divider as thouse in the VSENSE voltage divider to ensure the UCC28070 controller operates correctly. Please refer to the applications schematic for proper component placement. 10 Voltage Loop Configuration The methodology used to compensate the voltage loop is based on the compensation methodology developed by Lloyd Dixon. A detailed explanation of this compensation scheme written by Mr. Dixon can be found in the 1990 Unitrode Power Supply Design SEM700, High Power Factor Switching Pre-regulator Design Optimization, Topic 7, reference [2]. Capacitor CPV is sized to attenuate low frequency ripple to less than 3% of the voltage amplifier output range. This will ensure good power factor and low input current harmonic distortion. Voltage Amplifier Transconductance Amplifier gain: (44) Voltage Divider Feedback Gain: (45) Output impedance (ZO) is required to attenuate the low frequency boost capacitor output ripple (VRIPPLE) to less than 3% of the effective voltage amplifier output range (ΔVAO). This impedance is set by properly selecting feedback capacitor CPV: (46) (47) Choose as standard capacitor for the design: (48) 11SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated VAO = 3.2 VD OUT OUT CV V OUT PV 1P j 2 C 1η = H gm VAO V 2 C p p ´ ´ ´ ´ ´ ´ D ´ ´ f CV 300W 1 10.90= 0.0077 70 S 11Hz 3.2V 2 200 F 390V 2 150nF m p m p ´ ´ ´ ´ » ´ ´ ´ ´ ´ f ZV CV PV 1 1 R = = 96.4 k 2 C 2 10.6Hz 150nFp p » W ´ ´ ´ ´f ZVR = 100 kW ZV CV ZV 1 1 C = = 1.5 F 11Hz 2 100 k2 R 1010 m p p » ´ ´ W ´ ´ f Voltage Loop Configuration www.ti.com For the highest possible power factor the voltage loop crossover frequency (fCV) needs to be set based on the following equation: (49) (50) (51) Voltage compensation resistor RZV is then sized to put a pole at the converter’s voltage loop crossover frequency: (52) Select a standard resistor for the design: (53) Voltage compensation capacitor CZV is used to increase the dc gain of the voltage loop and gives some added phase margin before crossover. The zero added to the voltage loop needs to be set at 1/10th the crossover frequency. (54) 12 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review SLUA479B–August 2008–Revised July 2010 Copyright © 2008–2010, Texas Instruments Incorporated ( ) ( ) VAO ZV ZV CV V OUT ZV ZV PV ZV PV ZV PV V j 2 R C +1 G ( ) = = H gm V j 2 f R C C j 2 C + C +1 C +C p p p D ´ ´ ´ ´ ´ ´ D æ ö ´ ´ ´ ´ ´ ´ ´ ´ ç ÷ è ø f f f OUT OUTOUT PSV VAO OUT 1P j 2 CV η G ( ) = = V VAO V p æ ö ç ÷ ´ ´ ´ D è ø ´ D D f f ( )PSV CVTvdB( ) = 20log G ( ) G ( )´f f f 1 10 100 1 .10 390 60 30 0 30 60 90 90 90- TvdB f( ) 1 10 3 ´ 1 f 1 10 100 1 .10 30 15 30 45 60 75 90 90 0 qv f( ) 1 10 3 ´ 1 f www.ti.com Voltage Loop Configuration The following equations can be used to estimate voltage compensation network gain, voltage loop power stage gain and voltage loop gain. These equations can also be used to graphically check loop stability. Voltage Compensation Network Gain (GCV(f)) as function of frequency: (55) Voltage Loop Power Stage Gain (GPSV(f)) as function of frequency: (56) Voltage Loop Gain in dB (TvdB(f)) as function of frequency: (57) Figure 4 shows the theoretical loop gain (TvdB(f)) as a function of frequency and Figure 5 shows the theoretical loop phase (qv(f)) as a function of frequency. From these figures it can be observed that the voltage loop crossed over at roughly 9 Hz with a phase margin of 60 degrees. Compensating the voltage loop is not an exact science and should be checked with a network analyzer and adjusted if necessary. Figure 4. Theoretical Voltage Loop Gain (TvdB(f)) Figure 5. Theoretical Voltage Loop Phase (qv(f)) 13SLUA479B–August 2008–Revised July 2010 UCC28070 300-W Interleaved PFC Pre-Regulator —Design Review Copyright © 2008–2010, Texas Instruments Incorporated B CT MAX A B SYN S R 23.2 kN L1 50 350 H R + R 3 M + 23.2 kR = = 40.5 k R 0.1 nF 33.2 0.1nF m W ´ ´ ´ W W » W ´ W ´ SYNR = 38.3 kW ( ) ( ) -6 -6 INAC VAOMAX 2 VFF 17 10 A V V 1V 17 10 A 0.76V 5V 1V IMO = = 130 A K 0.398V m ´ ´ - ´ ´ - » ( )A B I B 0.76V R + R 0.76V (3M + 23.2k ) V = = 70V R 2 23.2k 2 ´ ´ W W » ´ W ´ 2 1 1 2 1 1 1 300 2 1 33 2 2 458 2 1 2 0 92 72 50 OUT S CT . P . W V R . . V V N . Vh ´