奇美屏V315B1-L01-31004212

Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 1 TFT LCD Approval Specification MODEL NO.: V315B1 - L01 LCD TV Head Division AVP ??? TVHD / PDD QRA Dept. DDIII DDII DDI Approval Approval Approval Approval ??? ??? ??? ??? LCD TV Marketing and Product Management Division Product Manager ??? ??? Customer: Approved by: Note: Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 2 - CONTENTS - REVISION HISTORY ------------------------------------------------------- 3 1. GENERAL DESCRIPTION ------------------------------------------------------- 4 1.1 OVERVIEW 1.2 FEATURES 1.3 APPLICATION 1.4 GENERAL SPECIFICATIONS 1.5 MECHANICAL SPECIFICATIONS 2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5 2.1 ABSOLUTE RATINGS OF ENVIRONMENT 2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE 2.2.2 BACKLIGHT UNIT 3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7 3.1 TFT LCD MODULE 3.2 BACKLIGHT INVERTER UNIT 3.2.1 CCFL(Cold Cathode Fluorescent Lamp) CHARACTERISTICS 3.2.2 INVERTER CHARACTERISTICS 3.2.3 INVERTER INTERFACE CHARACTERISTICS 4. BLOCK DIAGRAM ------------------------------------------------------- 12 4.1 TFT LCD MODULE 5. INTERFACE PIN CONNECTION ------------------------------------------------------- 13 5.1 TFT LCD MODULE 5.2 BACKLIGHT UNIT 5.3 INVERTER UNIT 5.4 BLOCK DIAGRAM OF INTERFACE 5.5 LVDS INTERFACE 5.6 COLOR DATA INPUT ASSIGNMENT 6. INTERFACE TIMING ------------------------------------------------------- 19 6.1 INPUT SIGNAL TIMING SPECIFICATIONS 6.2 POWER ON/OFF SEQUENCE 7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 22 7.1 TEST CONDITIONS 7.2 OPTICAL SPECIFICATIONS 8. DEFINITION OF LABELS ------------------------------------------------------- 26 8.1 CMO MODULE LABEL 9. PACKAGING ------------------------------------------------------- 27 9.1 PACKING SPECIFICATIONS 9.2 PACKING METHOD 10. PRECAUTIONS ------------------------------------------------------- 29 10.1 ASSEMBLY AND HANDLING PRECAUTIONS 10.2 SAFETY PRECAUTIONS 11. REGULATORY STANDARDS ------------------------------------------------------- 29 11.1 SAFETY 12. MECHANICAL CHARACTERISTICS ------------------------------------------------------- 30 Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 3 REVISION HISTORY Version Date Page (New) Section Description Ver 2.0 Aug. 7,’06 All All Approval Specification was first issued. Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 4 1. GENERAL DESCRIPTION 1.1 OVERVIEW V315B1- L01 is a 31.5” TFT Liquid Crystal Display module with 16-CCFL Backlight unit and 1ch-LVDS interface. This module supports 1366 x 768 WXGA format and can display true 16.7M colors ( 8-bit colors). The inverter module for backlight is built-in. 1.2 FEATURES - High brightness (500 nits) - Ultra-high contrast ratio (1500:1) - Faster response time (gray to gray average 6.5ms) - High color saturation NTSC 72% - Ultra wide viewing angle : 176(H)/176(V) (CR>20) with Super MVA technology - DE (Data Enable) only mode - LVDS (Low Voltage Differential Signaling) interface - 180 degree rotation display (option) - Color reproduction (nature color) - Low color shift function 1.3 APPLICATION - TFT LCD TVs - Multi-Media Display 1.4 GENERAL SPECIFICATI0NS Item Specification Unit Note Active Area 697.6845 (H) x 392.256 (V) (31.51" diagonal) mm Bezel Opening Area 703.8 (H) x 398.4 (V) mm (1) Driver Element a-si TFT active matrix - Pixel Number 1366 x R.G.B. x 768 pixel Pixel Pitch (Sub Pixel) 0.17025(H) x 0.51075 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 16.7M color Display Operation Mode Transmissive mode / Normally black - Surface Treatment Anti-Glare coating (Haze 25%),Hard coating (3H) - 1.5 MECHANICAL SPECIFICATIONS Item Min. Typ. Max. Unit Note Horizontal(H) 759 760 761 mm (1) Vertical(V) 449 450 451 mm (1) Depth(D) 36.95 37.95 38.95 mm To PCB cover Module Size Depth(D) 46.4 47.4 48.4 mm To inverter cover Weight 6300 6500 6700 g Note (1) Please refer to the attached drawings for more information of front and back outline dimensions. Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 5 2. ABSOLUTE MAXIMUM RATINGS 2.1 ABSOLUTE RATINGS OF ENVIRONMENT Value Item Symbol Min. Max. Unit Note Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 +50 ºC (1), (2) Shock (Non-Operating) SNOP - 50 G (3), (5) Vibration (Non-Operating) VNOP - 1.0 G (4), (5) Note (1) Temperature and relative humidity range is shown in the figure below. (a) 90 %RH Max. (Ta ? 40 ºC). (b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC). (c) No condensation. Note (2) The maximum operating temperature is based on the test condition that the surface temperature of display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber. Thermal management should be considered in final product design to prevent the surface temperature of display area from being over 65 ºC. The range of operating temperature may degrade in case of improper thermal management in final product design. Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z. Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z. Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that the module would not be twisted or bent by the fixture. Relative Humidity (%RH) Operating Range Temperature (ºC) 100 8060 -20 400 20-40 90 80 40 60 20 10 Storage Range Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 6 2.2 ELECTRICAL ABSOLUTE RATINGS 2.2.1 TFT LCD MODULE Value Item Symbol Min. Max. Unit Note Power Supply Voltage Vcc -0.3 6.0 V Input Signal Voltage VIN -0.3 3.6 V (1) 2.2.2 BACKLIGHT UNIT ValueItem Symbol Min. Max. Unit Note Lamp Voltage VW － 3000 VRMS Power Supply Voltage VBL 0 30 V (1) Control Signal Level － -0.3 7 V (1), (3) Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional operation should be restricted to the conditions described under normal operating conditions. Note (2) No moisture condensation or freezing. Note (3) The control signals includes Backlight On/Off Control, I_PWM Control, E_PWM Control and ERR signal for inverter status output. Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 7 3. ELECTRICAL CHARACTERISTICS 3.1 TFT LCD MODULE Ta = 25 ± 2 ºC Value Parameter Symbol Min. Typ. Max. Unit Note Power Supply Voltage VCC 4.5 5.0 5.5 V (1) Power Supply Ripple Voltage VRP - - 100 mV Rush Current IRUSH - - 4 A (2) White - 1.60 2.2 A Black - 0.90 - A Power Supply Current Vertical Stripe ICC - 1.40 - A (3) Differential Input High Threshold Voltage VLVTH - - +100 mV Differential Input Low Threshold Voltage VLVTL -100 - - mV Common Input Voltage VLVC 1.125 1.25 1.375 V LVDS Interface Terminating Resistor RT - 100 - ohm Input High Threshold Voltage VIH 2.7 - 3.3 V CMOS interface Input Low Threshold Voltage VIL 0 - 0.7 V Note (1) The module should be always operated within above ranges. Note (2) Measurement Conditions: Vcc rising time is 470us 470us +5V GND 0.9Vcc 0.1Vcc VR1 47K Q2 2N7002 (Low to High) (Control Signal) SW R2 1K C1 0.01uF Vcc C3 1uF (LCD Module Input)FUSE R1 +5.0V Q1 Si4435DY 1K Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 8 Note (3) The specified power supply current is under the conditions at Vcc = 5 V, Ta = 25 ± 2 ºC, fv = 60 Hz, whereas a power dissipation check pattern below is displayed. 3.2 BACKLIGHT INVERTER UNIT 3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC) Value Parameter Symbol Min. Typ. Max. Unit Note Lamp Voltage VW - 1250 - VRMS IL = 5.2mA Lamp Current IL 4.7 5.2 5.7 mARMS (1) - - 2450 VRMS (2), Ta = 0 ºCLamp Starting Voltage VS - - 2360 VRMS (2), Ta = 25 ºC Operating Frequency FO 40 - 70 KHz (3) Lamp Life Time LBL 50,000 - Hrs (4) Active Area c. Vertical Stripe Pattern R R R R R R R R G G G G B B B B B B G G G G B B B B R R Active Area Active Area a. White Pattern b. Black Pattern Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 9 3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC) Value Parameter Symbol Min. Typ. Max. Unit Note Power Consumption PBL - 120 134 W (5),(6), IL = 5.2mA Input Voltage VBL 22.8 24 25.2 VDC Input Current IBL - 5.0 - A Non Dimming Input Ripple Noise - - - 500 mVP-P VBL=22.8V 2450 - - VRMS Ta = 0 ºC Backlight Turn on Voltage VBS 2360 - - VRMS Ta = 25 ºC Oscillating Frequency FW 55 58 61 kHz Dimming frequency FB 150 160 170 Hz Minimum Duty Ratio DMIN - 20 - % Note (1) Lamp current is measured by utilizing high frequency current meters as shown below: Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second under starting up duration. Otherwise the lamp could not be lighted on completed. Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the display input signals, and it may result in line flow on the display. In order to avoid interference, the lamp frequency should be detached from the horizontal synchronous frequency and its harmonics as far as possible. Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and the effective discharge length is longer than 80% of its original length (Effective discharge length is defined as an area that has equal to or more than 70% brightness compared to the brightness at the center point of lamp.) as the time in which it continues to operate under the Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 10 condition at Ta = 25 ?2? and IL = 4.7 ~ 5.7 mARMS. Note (5) The power supply capacity should be higher than the total inverter power consumption PBL. Since the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current changed as PWM duty on and off. The transient response of power supply should be considered for the changing loading when inverter dimming. Note (6) The measurement condition of Max. value is based on 31.5" backlight unit under input voltage 24V, average lamp current 5.5 mA and lighting 30 minutes later. 3.2.3 INVERTER INTERFACE CHARACTERISTICS No ITEM SYMBOL TEST CONDITION MIN TYPE MAX UNIT NOTE(1-2) 1 Error Signal ERR － － － － － (Note 2) ON － 2.0 － 5.0 V 2 On/Off Control Voltage OFF VBLON － 0 － 0.8 V MAX － － － 3.3 V Maximum Duty Ratio 3 Internal PWM Control Voltage MIN VIPWM － － 0 － V Minimum Duty Ratio HI － 2.0 － 5.0 V ON Duration 4 External PWM Control Voltage LO VEPWM － 0 － 0.8 V OFF Duration 5 Control Signal Rising Time Tr － － － 100 ms 6 Control Signal Falling Time Tf － － － 100 ms 7 ON/OFF Delay Time Ton － 500 － － ms 8 ON/OFF Off Time Toff － 500 － － ms 9 PWM Signal Rising Time TPWMR － － － 50 us 10 PWM Signal Falling Time TPWMF － － － 50 us Note (1) The power sequence and control signal timing are shown as the following figure 1. Note (2) When inverter protective function is triggered, ERR will output open collector status; In normal operation, the signal of ERR will output a low level voltage. Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 11 2.0V 0.8V Tr Tf Backlight on duration 0 VEPWM 3.3V VIPWM TPWMR VW Ton Minimun Duty 100% PWM Duty VBL VBLON 0 0 0 2.0V 0.8V TPWMF Toff External PWM Period External Figure 1 Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 12 4. BLOCK DIAGRAM 4.1 TFT LCD MODULE TFT LCD PANEL (1366x3x768) DATA DRIVER IC SC A N D R IVER IC DC/DC CONVERTER & REFERENCE VOLTAGE IN PU T C O N N EC TO R (JA E,FI-E30S) or equal GND Vcc FRAME BUFFER RX0(+/-) RX1(+/-) RX2(+/-) RX3(+/-) RXCLK(+/-) TIMING CONTROLLER BACKLIGHT UNIT INVERTER CONNECTOR CN1:S14B-PH-SM3-TB(D)(LF)(JST) or equivalent CN3-CN10: SM02(8.0)B-BDBS-1(LF)(SN) or equivalent CN1 CN2: S2B-ZR-SM3A-TF (D)(LF)(JST) or equivalent GND E_PWM I_PWM BLON VBL ERR Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 13 5. INTERFACE PIN CONNECTION 5.1 TFT LCD MODULE CNF1 Connector Pin Assignment Pin No. Symbol Description Note 1 ODSEL Overdrive Lookup Table Selection (2) 2 RPF Display Rotation (3) 3 NC No connection (4) 4 GND Ground 5 RX0- Negative transmission data of pixel 0 6 RX0+ Positive transmission data of pixel 0 7 GND Ground 8 RX1- Negative transmission data of pixel 1 9 RX1+ Positive transmission data of pixel 1 10 GND Ground 11 RX2- Negative transmission data of pixel 2 12 RX2+ Positive transmission data of pixel 2 13 GND Ground 14 RXCLK- Negative of clock 15 RXCLK+ Positive of clock 16 GND Ground 17 RX3- Negative transmission data of pixel 3 18 RX3+ Positive transmission data of pixel 3 19 GND Ground 20 NC No connection (4) 21 SELLVDS Select LVDS data format (5) 22 NC No connection (4) 23 GND Ground 24 GND Ground 25 GND Ground 26 VCC Power supply: +5V 27 VCC Power supply: +5V 28 VCC Power supply: +5V 29 VCC Power supply: +5V 30 VCC Power supply: +5V Note (1) Connector Part No.: FI-E30S(JAE) or compatible Note (2) Overdrive lookup table selection. The Overdrive lookup table should be selected in accordance to the frame rate to optimize image quality. ODSEL Note L or Open Lookup table was optimized for 60 Hz frame rate. H Lookup table was optimized for 50 Hz frame rate. Note (3) Low or open: normal display (default), High : display with 180 degree rotation Note (4) Reserved for internal use. Left it open. Note (5) Ground: JEIDA, High or OPEN: Normal LVDS format Please refer to 5.5 LVDS INTERFACE (Page 17) Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 14 5.2 BACKLIGHT UNIT The pin configuration for the housing and leader wire is shown in the table below. CN3-CN10 (Housing): BDBR-03(4.0)V-1S or equivalent Pin No. Symbol Description Wire Color 1 HV High Voltage White 2 HV High Voltage Pink 3 HV High Voltage Blue 4 HV High Voltage White Note (1) The backlight interface housing for high voltage side is a model BDBR-03(4.0)V-1S, manufactured by JST or equivalent. The mating header on inverter part number is SM02(8.0)B-BDBS-1-TB(LF) CN2 (Housing): ZHR-2 (JST) or equivalent Pin No. Symbol Description Wire Color 1 LV Low Voltage (+) Black 2 LV Low Voltage (-) White Note (2) The backlight interface housing and return cable for low voltage side is a model ZHR-2 , manufactured by JST or equivalent. The mating header on inverter part number is S2B-ZR-SM3A-TF(D)(LF) or equivalent. 8 Female Connectors BDBR-03(4.0)V-1S or Equal ZHR-2 or Equal Return cable 1.LV(Black) 2.LV(W hite) 1.HV(W hite,+) 4.HV(White,-) 2.HV(Pink,+) 3.HV(Blue,-) 4.HV(White,-) 1.HV(W hite,+) 3.HV(Blue,-) 2.HV(Pink,+) 4.HV(White,-) 1.HV(W hite,+) 3.HV(Blue,-) 2.HV(Pink,+) 4.HV(White,-) 1.HV(White,+) 3.HV(Blue,-) 2.HV(Pink,+) Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 15 5.3 INVERTER UNIT CN1(Header): S14B-PH-SM3-TB(D)(LF)(JST) or equivalent.. Pin No. Symbol Description 1 2 3 4 5 VBL +24V Power input 6 7 8 9 10 GND Ground 11 ERR Normal (GND) Abnormal ( open collector) 12 BLON Backlight on/off control 13 I_PWM Internal PWM control signal 14 E_PWM External PWM control signal Notice: #PIN 13:Analog Dimming Control (Use Pin 13) : 0V~3.3V and Pin 14 must open. #PIN 14:PWM Dimming Control (Use Pin 14) : Pin 13 must open. #Pin 13(I_PWM) and Pin 14(E_PWM) can not open in same period. CN2(Header): S2B-ZR-SM3A-TF(D)(LF)(JST) or equivalent Pin No. Symbol Description 1 CCFL COLD CCFL low voltage (+) 2 CCFL COLD CCFL low voltage (-) CN3-CN10 (Header): SM02(8.0)B-BDBS-1(LF)(SN) or equivalent. Pin No. Symbol Description 1 CCFL HOT CCFL high voltage 2 CCFL HOT CCFL high voltage Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 16 5.4 BLOCK DIAGRAM OF INTERFACE CNF1 R0~R7 : Pixel R Data , G0~G7 : Pixel G Data , B0~B7 : Pixel B Data , DE : Data enable signal Note (1) The system must have the transmitter to drive the module. Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is used differentially. R0-R7 G0-G7 B0-B7 DE Host Graphics Controller TxIN PLL PLL R0-R7 G0-G7 B0-B7 DE DCLK Timing Controller LVDS Transmitter THC63LVDM83A (LVDF83A) LVDS Receiver THC63LVDF84A Rx0+ Rx0- Rx1+ Rx1- Rx2+ Rx2- CLK+ CLK- RxOUT 51? 51? 51? 51? 51? 51? 51? 51? 51? 51? 100pF 100pF 100pF 100pF 100pF Rx3- Rx3+ Issued Date: Aug. 7, 2006 Model No.: V315B1 - L01 Approval Version 2.0 17 5.5 LVDS INTERFACE SIGNAL TRANSMITTER THC63LVDM83A INTERFACE CONNECTOR RECEIVER THC63LVDF84A TFT CONTROL INPUT SELLVDS= H or OPEN SELLVDS= L PIN INPUT Host TFT-LCD PIN OUTPUT SELLVDS= H or OPEN SELLVDS =L R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 DE R6 R7 G6 G7 B6 B7 RSVD 1 RSVD 2 RSVD 3 R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 DE R0 R1 G0 G1 B0 B1 RSVD 1 RSVD 2 RSVD 3 51 52 54 55 56 3 4 6 7 11 12 14 15 19 20 22 23 24 30 50 2 8 10 16 18 25 27 28 TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN7 TxIN8 TxIN9 TxIN12 TxIN13 TxIN14 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN26 TxIN27 TxIN5 TxIN10 TxIN11 TxIN16 TxIN17 TxIN23 TxIN24 TxIN25 TA OUT0+ TA OUT0- TA OUT1+ TA OUT1- TA OUT2+ TA OUT2- TA OUT3+ TA OUT3- Rx 0+ Rx 0- Rx 1+ Rx 1- Rx 2+ Rx 2- Rx 3+ Rx 3- 27 29 30 32 33 35 37 38 39 43 45 46 47 51 53 54 55 1 6 7 34 41 42 49 50 2 3 5 Rx OUT0 Rx OUT1 Rx OUT2 Rx OUT3 Rx OUT4 Rx OUT6 Rx OUT7 Rx OUT8 Rx OUT9 Rx OUT12 Rx OUT13 Rx OUT14 Rx OUT15 Rx OUT18 Rx OUT19 Rx OUT20 Rx OUT21 Rx OUT22 Rx OUT26 Rx OUT27 Rx OUT5 Rx OUT10 Rx OUT11 Rx OUT16 Rx OUT17 Rx OUT23 Rx OUT24 Rx OUT25 R0 R1 R2 R3 R4 R5 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 DE R6 R7 G6 G7 B6 B7 NC NC NC R2 R3 R4 R5 R6 R7 G2 G3 G4 G5 G6 G7 B2 B3 B4 B5 B6 B7 DE R0 R1 G0 G1 B0 B1 NC NC NC 24 bit DCLK 31 TxCLK IN TxCLK OUT+ TxCLK OUT- RxCLK IN+ RxCLK IN- 26 RxCLK OUT DCLK R0~R7: Pixel R Data (7; MSB, 0; LSB) G0~G7: Pixel G Data (7; MSB, 0; LS