1Gb_DDR2_SDRAM

- 1 - K4T1G044QE K4T1G084QE Rev. 1.11, Feb. 2010 SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. For updates or additional information about Samsung products, contact your nearest Samsung office. All brand names, trademarks and registered trademarks belong to their respective owners. ⓒ 2010 Samsung Electronics Co., Ltd. All rights reserved. datasheet K4T1G164QE 1Gb E-die DDR2 SDRAM 60FBGA/84FBGA with Lead-Free & Halogen-Free (RoHS compliant) - 2 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE Revision History Revision No. History Draft Date Remark Editor 1.0 - Initial Release Aug. 2008 - S.H.Kim 1.01 - Corrected Typo. Sep. 2008 - S.H.Kim 1.1 - Updated AC/DC operating condition with the JEDEC updated (JESD79-2E) Dec. 2008 - S.H.Kim 1.11 - Changed layout Feb. 2010 - S.H.Kim - 3 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE Table Of Contents 1Gb E-die DDR2 SDRAM 1. Ordering Information ..................................................................................................................................................... 4 2. Key Features................................................................................................................................................................. 4 3. Package pinout/Mechanical Dimension & Addressing..................................................................................................5 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package .......................................................................................... 5 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package .......................................................................................... 6 3.3 x16 Package Pinout (Top view) : 84ball FBGA Package ........................................................................................ 7 3.4 FBGA Package Dimension (x4/x8).......................................................................................................................... 8 3.5 FBGA Package Dimension (x16)............................................................................................................................. 9 4. Input/Output Functional Description.............................................................................................................................. 10 5. DDR2 SDRAM Addressing ........................................................................................................................................... 11 6. Absolute Maximum Ratings .......................................................................................................................................... 12 7. AC & DC Operating Conditions..................................................................................................................................... 12 7.1 Recommended DC operating Conditions (SSTL_1.8)............................................................................................. 12 7.2 Operating Temperature Condition ........................................................................................................................... 13 7.3 Input DC Logic Level ............................................................................................................................................... 13 7.4 Input AC Logic Level ............................................................................................................................................... 13 7.5 AC Input Test Conditions......................................................................................................................................... 13 7.6 Differential input AC logic Level............................................................................................................................... 14 7.7 Differential AC output parameters ........................................................................................................................... 14 8. ODT DC electrical characteristics ................................................................................................................................. 14 9. OCD default characteristics .......................................................................................................................................... 15 10. IDD Specification Parameters and Test Conditions.................................................................................................... 16 11. DDR2 SDRAM IDD Spec Table.................................................................................................................................. 18 12. Input/Output capacitance ............................................................................................................................................20 13. Electrical Characteristics & AC Timing for DDR2-800/667 ......................................................................................... 20 13.1 Refresh Parameters by Device Density................................................................................................................. 20 13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin ................................................................ 20 13.3 Timing Parameters by Speed Grade ..................................................................................................................... 21 14. General notes, which may apply for all AC parameters.............................................................................................. 23 15. Specific Notes for dedicated AC parameters ..............................................................................................................25 - 4 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 1. Ordering Information NOTE : 1. Speed bin is in order of CL-tRCD-tRP. 2. RoHS Compliant. 3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products. 4. “C” of Part number(13th digit) stands normal, and “L” stands for Low power products. 2. Key Features Organization DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 Package 256Mx4 K4T1G044QE-HC(L)E7 K4T1G044QE-HC(L)F7 K4T1G044QE-HC(L)E6 60 FBGA 128Mx8 K4T1G084QE-HC(L)E7 K4T1G084QE-HC(L)F7 K4T1G084QE-HC(L)E6 60 FBGA 64Mx16 K4T1G164QE-HC(L)E7 K4T1G164QE-HC(L)F7 K4T1G164QE-HC(L)E6 84 FBGA Speed DDR2-800 5-5-5 DDR2-800 6-6-6 DDR2-667 5-5-5 Units CAS Latency 5 6 5 tCK tRCD(min) 12.5 15 15 ns tRP(min) 12.5 15 15 ns tRC(min) 57.5 60 60 ns • JEDEC standard VDD = 1.8V ± 0.1V Power Supply • VDDQ = 1.8V ± 0.1V • 333MHz fCK for 667Mb/sec/pin, 400MHz fCK for 800Mb/sec/pin • 8 Banks • Posted CAS • Programmable CAS Latency: 3, 4, 5, 6 • Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5 • Write Latency(WL) = Read Latency(RL) -1 • Burst Length: 4 , 8(Interleave/nibble sequential) • Programmable Sequential / Interleave Burst Mode • Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature) • Off-Chip Driver(OCD) Impedance Adjustment • On Die Termination • Special Function Support - 50ohm ODT - High Temperature Self-Refresh rate enable • Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95 °C • All of products are Lead-Free, Halogen-Free, and RoHS compliant The 1Gb DDR2 SDRAM is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 800Mb/ sec/pin (DDR2-800) for general applications. The chip is designed to comply with the following key DDR2 SDRAM fea- tures such as posted CAS with additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance adjustment and On Die Termination. All of the control and address inputs are synchronized with a pair of exter- nally supplied differential clocks. Inputs are latched at the crosspoint of dif- ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- ion. The address bus is used to convey row, column, and bank address information in a RAS/CAS multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing. The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ. The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball FBGA(x16). NOTE : 1. This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device Operation & Timing Dia- gram”. 2. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. - 5 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 3. Package pinout/Mechanical Dimension & Addressing 3.1 x4 Package Pinout (Top view) : 60ball FBGA Package NOTE : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD,VDDQ, VSS, and VSSQ. 1 2 3 4 5 6 7 8 9 A VDD NC VSS VSSQ DQS VDDQ B NC VSSQ DM DQS VSSQ NC C VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ D NC VSSQ DQ3 DQ2 VSSQ NC E VDDL VREF VSS VSSDL CK VDD F CKE WE RAS CK ODT0 G BA2 BA0 BA1 CAS CS H A10/AP A1 A2 A0 VDD J VSS A3 A5 A6 A4 K A7 A9 A11 A8 VSS L VDD A12 NC NC A13 Populated ball Ball not populated Ball Locations (x4) Top view (See the balls through package) 1 2 3 4 8 95 6 7 A B C D E F G H J K L - 6 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 3.2 x8 Package Pinout (Top view) : 60ball FBGA Package NOTE : 1. Pins B3 and A2 have identical capacitances as pins B7 and A8. 2. For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input data masking function is disabled. 3. The function of DM or RDQS/RDQS is enabled by EMRS command. 4. VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD,VDDQ, VSS, and VSSQ. 1 2 3 4 5 6 7 8 9 A VDD NU/RDQS VSS VSSQ DQS VDDQ B DQ6 VSSQ DM/RDQS DQS VSSQ DQ7 C VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ D DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 E VDDL VREF VSS VSSDL CK VDD F CKE WE RAS CK ODT0 G BA2 BA0 BA1 CAS CS H A10/AP A1 A2 A0 VDD J VSS A3 A5 A6 A4 K A7 A9 A11 A8 VSS L VDD A12 NC NC A13 Populated ball Ball not populated Ball Locations (x8) Top view (See the balls through package) 1 2 3 4 8 95 6 7 A B C D E F G H J K L - 7 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 3.3 x16 Package Pinout (Top view) : 84ball FBGA Package NOTE : VDDL and VSSDL are power and ground for the DLL. It is recommended that they be isolated on the device from VDD, VDDQ, VSS, and VSSQ. 1 2 3 4 5 6 7 8 9 A VDD NC VSS VSSQ UDQS VDDQ B DQ14 VSSQ UDM UDQS VSSQ DQ15 C VDDQ DQ9 VDDQ VDDQ DQ8 VDDQ D DQ12 VSSQ DQ11 DQ10 VSSQ DQ13 E VDD NC VSS VSSQ LDQS VDDQ F DQ6 VSSQ LDM LDQS VSSQ DQ7 G VDDQ DQ1 VDDQ VDDQ DQ0 VDDQ H DQ4 VSSQ DQ3 DQ2 VSSQ DQ5 J VDDL VREF VSS VSSDL CK VDD K CKE WE RAS CK ODT L BA2 BA0 BA1 CAS CS M A10/AP A1 A2 A0 VDD N VSS A3 A5 A6 A4 P A7 A9 A11 A8 VSS R VDD A12 NC NC NC Populated ball Ball not populated Ball Locations (x16) Top view (See the balls through package) 1 2 3 4 8 95 6 7 A B C D E F G H J K L M N P R - 8 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 3.4 FBGA Package Dimension (x4/x8) 9. 50 ± 0 .1 0 7.50 ± 0.10 #A1 0.35±0.05 1.10±0.10 (0.95) # A1 INDEX MARK (1.90) 9. 50 ± 0 .1 0 0. 80 x 1 0 = 8. 00 0. 80 7.50 ± 0.10 1.60 0.80 x 8 = 6. 40 4. 00 0.80 A B A B C D E F H J K L G 0. 10 M A X 3.20 0. 80 9 8 7 6 5 4 3 2 1 60-∅0.45 Solder ball 0.2 M A B (Post reflow 0.50 ± 0.05) MOLDING AREA (Datum A) (Datum B) Units : Millimeters BOTTOM VIEW TOP VIEW - 9 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 3.5 FBGA Package Dimension (x16) 12 .5 0 ± 0. 10 7.50 ± 0.10 #A1 0.35±0.05 1.10±0.10 (0.95) # A1 INDEX MARK (1.90) 12 .5 0 ± 0. 10 0. 80 x 1 4 = 11 .2 0 0. 80 7.50 ± 0.10 1.60 0.80 x 8 = 6. 40 5. 60 0.80 A B A B C D E F H J K L G 0. 10 M A X 3.20 0. 80 9 8 7 6 5 4 3 2 1 84-∅0.45 Solder ball 0.2 M A B (Post reflow 0.50 ± 0.05) MOLDING AREA (Datum A) (Datum B) M N P R Units : Millimeters BOTTOM VIEW TOP VIEW - 10 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 4. Input/Output Functional Description BA0 - BA2 Input Bank Address Inputs: BA0, BA1 and BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS cycle. Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing). CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and out- put drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self refresh exit. After VREF has become stable during the power on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on sys-tems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS, RDQS, RDQS, and DM signal for x4/x8 configurations. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal. The ODT pin will be ignored if the Extended Mode Register (EMRS(1)) is programmed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci- dent with that input data during a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For x8 device, the function of DM or RDQS/RDQS is enabled by EMRS command. A0 - A13 Input Address Inputs: Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code dur- ing Mode Register Set commands. DQ Input/Output Data Input/ Output: Bi-directional data bus. DQS, (DQS) (LDQS), (LDQS) (UDQS), (UDQS) (RDQS), (RDQS) Input /Output Data Strobe: output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS corresponds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differential pair signaling to the system during both reads and writes. An EMRS(1) control bit enables or disables all complementary data strobe signals. In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of EMRS(1) x4 DQS/DQS x8 DQS/DQS if EMRS(1)[A11] = 0 x8 DQS/DQS, RDQS/RDQS, if EMRS(1)[A11] = 1 x16 LDQS/LDQS and UDQS/UDQS "single-ended DQS signals" refers to any of the following with A10 = 1 of EMRS(1) x4 DQS x8 DQS if EMRS(1)[A11] = 0 x8 DQS, RDQS, if EMRS(1)[A11] = 1 x16 LDQS and UDQS NC No Connect: No internal electrical connection is present. VDD / VDDQ Supply Power Supply: 1.8V +/- 0.1V, DQ Power Supply: 1.8V +/- 0.1V VSS / VSSQ Supply Ground, DQ Ground VDDL Supply DLL Power Supply: 1.8V +/- 0.1V VSSDL Supply DLL Ground VREF Supply Reference voltage - 11 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 5. DDR2 SDRAM Addressing 1Gb Addressing * Reference information: The following tables are address mapping information for other densities. 256Mb 512Mb 2Gb 4Gb Configuration 256Mb x4 128Mb x 8 64Mb x16 # of Bank 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A13 A0 ~ A13 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 64Mb x4 32Mb x 8 16Mb x16 # of Bank 4 4 4 Bank Address BA0,BA1 BA0,BA1 BA0,BA1 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A12 A0 ~ A12 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A8 Configuration 128Mb x4 64Mb x 8 32Mb x16 # of Bank 4 4 4 Bank Address BA0,BA1 BA0,BA1 BA0,BA1 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A13 A0 ~ A13 A0 ~ A12 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 512Mb x4 256Mb x 8 128Mb x16 # of Bank 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 ~ A14 A0 ~ A14 A0 ~ A13 Column Address A0 ~ A9,A11 A0 ~ A9 A0 ~ A9 Configuration 1 Gb x4 512Mb x 8 256Mb x16 # of Bank 8 8 8 Bank Address BA0 ~ BA2 BA0 ~ BA2 BA0 ~ BA2 Auto precharge A10/AP A10/AP A10/AP Row Address A0 - A15 A0 - A15 A0 - A14 Column Address A0 - A9,A11 A0 - A9 A0 - A9 - 12 - K4T1G164QE datasheet DDR2 SDRAM Rev. 1.11 K4T1G084QE K4T1G044QE 6. Absolute Maximum Ratings NOTE : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measuremen