OIF-SPI3-01.0

System Packet Interface Level 3: OC-48 System Interface for Physical and Link Layer Devices IA # OIF-SPI3-01.0 June 2000 Implementation Agreement created and approved by the Optical Internetworking Forum www.oiforum.com Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 2 Working Group: Physical – Link Layer (PLL) TITLE: System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices. SOURCE: Richard Cam Russ Tuck Technical Editor Working Group Chair PMC-Sierra Pluris Terabit Network Systems 105-8555 Baxter Place 10455 Bandley Drive Burnaby, B.C. Cupertino, CA 95014 Canada V5A 4V7 USA Phone: +1 604 415 6022 Phone: +1 408 861 3360 Email: richard_cam@pmc-sierra.com Email: tuck@pluris.com DATE: June 2000 Document Status: Implementation Agreement: OIF-SPI3-01.0 Project Name: SPI-3 Project Number: Notice: This Technical Document has been created by the Optical Internetworking Forum (OIF). This document is offered to the OIF Membership solely as a basis for agreement and is not a binding proposal on the companies listed as resources above. The OIF reserves the rights to at any time to add, amend, or withdraw statements contained herein. Nothing in this document is in any way binding on the OIF or any of its members. The user's attention is called to the possibility that implementation of the OIF implementation agreement contained herein may require the use of inventions covered by the patent rights held by third parties. By publication of this OIF implementation agreement, the OIF makes no representation or warranty whatsoever, whether expressed or implied, that implementation of the specification will not infringe any third party rights, nor does the OIF make any representation or warranty whatsoever, whether expressed or implied, with respect to any claim that has been or may be asserted by any third party, the validity of any patent rights related to any such claim, or the extent to which a license to use any such rights may or may not be available or the terms hereof. For additional information contact: The Optical Internetworking Forum, 39355 California Street, Suite 307, Fremont, CA 94538 510-608-5928 phone Φ info@oiforum.com Copyright (C) The Optical Internetworking Forum (OIF) (2001). All Rights Reserved. hello Highlight Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 3 This document and translations of it may be copied and furnished to others, and derivative works that comment on or otherwise explain it or assist in its implementation may be prepared, copied, published and distributed, in whole or in part, without restriction other than the following, (1) the above copyright notice and this paragraph must be included on all such copies and derivative works, and (2) this document itself may not be modified in any way, such as by removing the copyright notice or references to the OIF, except as needed for the purpose of developing OIF Implementation Agreements. By downloading, copying, or using this document in any manner, the user consents to the terms and conditions of this notice. Unless the terms and conditions of this notice are breached by the user, the limited permissions granted above are perpetual and will not be revoked by the OIF or its successors or assigns. This document and the information contained herein is provided on an "AS IS" basis and THE OIF DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTY THAT THE USE OF THE INFORMATION HEREIN WILL NOT INFRINGE ANY RIGHTS OR ANY IMPLIED WARRANTIES OF MERCHANTABILITY, TITLE OR FITNESS FOR A PARTICULAR PURPOSE. Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 4 1 Table of Contents 0 Cover Sheet ...............................................................................................1 1 Table of Contents.......................................................................................4 2 List of Figures.............................................................................................5 3 List of Tables..............................................................................................5 4 Document Revision History ........................................................................6 5 Introduction ................................................................................................7 6 SPI-3 Reference Definition.........................................................................6 7 Compatibility Options .................................................................................7 8 Specification Summary...............................................................................8 8.1 Signal Naming Conventions................................................................8 8.2 Bus Widths..........................................................................................8 8.3 Clock Rates.........................................................................................8 8.4 Packet Interface Synchronization........................................................9 8.5 Application Line Rates ......................................................................11 8.6 PHY and Link Layer Interface Examples...........................................11 9 Interface Data Structures .........................................................................14 10 Transmit Packet Interface Description .....................................................16 10.1 Transmit Signals ...............................................................................16 10.2 Examples ..........................................................................................21 10.3 AC Timing .........................................................................................24 11 Receive Packet Interface Description ......................................................27 11.1 Receive Signals ................................................................................28 11.2 Examples ..........................................................................................31 11.3 AC Timing .........................................................................................34 12 Summary ..............................................................................................38 13 References ...........................................................................................38 13.1 Normative references........................................................................38 13.2 Informative references ......................................................................38 14 Appendix A: Glossary ...........................................................................38 15 Appendix B: Open Issues / current work items .....................................39 16 Appendix C: List of companies belonging to OIF when document is approved.............................................................................................................39 Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 5 2 List of Figures 6.1 SPI-3 Reference Points............................................................................6 8.1 SPI-3 PHY to Link Layer 32-bit Interface ...............................................12 8.2 SPI-3 PHY to Link Layer 8-bit Interface .................................................15 9.1 32-bit Interface Data Structures .............................................................15 9.2 8-bit Interface Data Structures ...............................................................15 10.1 Transmit Logical Timing .........................................................................21 10.2 Packet-Level Transmit Polling Logical Timing.......................................22 10.3 Transmit Logical Timing (single-port without in-band addressing) .........23 10.4 Transmit Physical Timing .......................................................................25 11.1 Receive Logical Timing .........................................................................32 11.2 Receive Logical Timing with Pausing ....................................................32 11.3 Receive Logical Timing (single-port without in-band addressing)..........33 11.4 Receive Physical Timing .......................................................................35 3 List of Tables 8.1 Interface Bit Rates.................................................................................11 10.1 Transmit Signal Descriptions.................................................................16 10.2 Transmit Interface Timing......................................................................24 11.1 Receive Signal Descriptions..................................................................28 11.2 Receive Interface Timing.......................................................................34 Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 6 4 Document Revision History Oif2000.008 24 December 1999 Baseline document produced from adoption of contribution oif99.125 at the October 99 OIF meeting. Oif2000.008.1 01 February 2000 Revised document formatted to the OIF template for technical documents (oif2000.022), inserted all changes from contribution oif00.031 at the Jan/Feb 00 OIF meeting, as approved by the PLL working group. Oif2000.008.2 24 April 2000 Revised document containing comment resolution from straw ballot, as well as some editorial corrections of typos. Oif2000.008.3 4 October 2000 Updated document status to “Approved Implementation Agreement”. One editorial correction of a typo. Updated technical editor (formerly Chen Goldenberg, Novanet Semiconductor / Pentacom) and working group chair (formerly Sid Chaudhuri, AT&T / Tellium). Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 7 5 Introduction This document specifies the Optical Internetworking Forum's recommended interface for the interconnection of Physical Layer (PHY) devices to Link Layer devices. This specification is based on the SATURN Development Group’s "POS-PHY Level 3" interface [1], which will be referred to hereon as the SPI-3 interface. SPI-3 fulfills the need for system designers to target a standard POS Physical Layer interface. Although targeted at implementing POS, the SPI-3 specification is not restricted to this application. It provides a versatile bus interface for exchanging packets within a communication system. SPI-3 defines the requirements for interoperable single-PHY (one PHY layer device connected to one Link Layer device) and multi-PHY (multiple PHY layer devices connected to one Link Layer device) applications. It stresses simplicity of operation to allow forward migration to more elaborate PHY and Link Layer devices. This specification defines 1-the physical implementation of the SPI-3 bus, 2- the signaling protocol used to communicate data and 3-the data structure used to store the data into holding FIFO’s. Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 8 6 SPI-3 Interface Reference Definition The SPI-3 interface defines the interface between SONET/SDH Physical layer devices and Link Layer devices, which can be used to implement several packet-based protocols like HDLC and PPP. Figure 6.1: SPI-3 Reference Points PMD Device PHY-Link Interface Link Layer Facility Interface PHY Diagram Definitions Facility: An optical fiber, twisted pair electrical or coaxial cable electrical transmission facility. Link Layer: Switching Function Layer. PHY: Physical Layer for Packet over SONET. PHY-LINK: Physical Layer to Link Layer electrical interface. PMD: Physical Medium Dependent Layer. SPI-3 specifies the PHY-LINK interface. The Facility Interface (such as SONET OC-3) is defined by several National and International standards organizations including Bellcore and ITU. hello Highlight hello Highlight Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 9 7 Compatibility Options The SPI-3 specification does not attempt to be compatible to any existing standard. There is no existing equivalent standard. Specifically, SPI-3 does not intend to be compatible with similar ATM specifications like Utopia [3, 4] and SCI-PHY [2]. Although this information is not critical to any implementation, the following bullets highlight the differences between the Utopia/SCI-PHY and SPI-3 interfaces. • Allowance for an 8-bit bus or a 32-bit bus interface running at a maximum speed of 104 MHz. The bus interface is point-to-point (one output driving only one input load). • Byte or double-word (4 bytes) data format that can accommodate variable size packets. • Modification to the RSOC/TSOC start of cell signals to identify the start of packets being transferred over the interface. Renamed the signals to RSOP/TSOP. • Addition of the REOP/TEOP end of packet signals which delineate the end of packets being transferred over the interface. • Addition of the RMOD[1:0]/TMOD[1:0] modulo signals which indicate if the last double-word of the packet transfer contains 1, 2, 3 or 4 valid bytes of data. • Addition of the RERR/TERR error signals which, during the end of the packet, indicates if the transferred packet must be discarded/aborted. • Deletion of the RCA signal. Receive interface of the PHY pushes packet data to the Layer device. Multi-port PHY devices are responsible for performing round-robin servicing of their ports. PHY address is inserted in-band with the packet data. • Transmit interface of the PHY is selected using an in-band address that is provided on the same bus transferring the packet data. • Addition of the RSX/TSX start of transfer signals which identify when the in-band port address of the PHY is on the RDAT/TDAT bus. • Modification of the TCA cell available signals to form the TPA packet available signals. TPA logic values are defined based on the FIFO fill level (in terms of bytes). In multi-port PHY devices, PHY status indication can be provided using either a polling or a direct status indication scheme. hello Highlight hello Highlight Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 10 Polled PHY address is provided by a separate address bus and has pipelined timing. • Interface FIFO fill level granularity is byte-based. For the Transmit Interface FIFO, the packet available status and start of transmission FIFO fill levels are programmable. For the Receive Interface, the maximum burst transfer size is programmable. 8 Specification Summary 8.1 Signal Naming Conventions The interface where data flows from the Link Layer device to the Physical layer device will be labeled the Transmit Interface. The interface where data flows from the Physical Layer device to the Link Layer device will be labeled the Receive Interface. All signals are active high unless denoted by a trailing "B". SIGNAL Active high signaling. SIGNALB Active low signaling. 8.2 Bus Widths SPI-3 compatible devices support an 8-bit and/or a 32-bit data bus structure. The bus interface is point-to-point (one output driving only one input load) and thus a 32-bit data bus would support only one device. To support multiple lower rate devices with point-to-point connections, an 8-bit data bus structure is defined. Thus, each PHY device would use an 8-bit interface reducing the total number of pins required. To support variable length packets, the RMOD[1:0]/TMOD[1:0] signals are defined to specify valid bytes in the 32-bit data bus structure. Each double- word must contain four valid bytes of packet data until the last double-word of the packet transfer which is marked with the end of packet REOP/TEOP signal. This last double-word of the transfer will contain up to four valid bytes specified by the RMOD[1:0]/TMOD[1:0] signals. 8.3 Clock Rates SPI-3 compatible devices can support a transfer clock rate up to 104 MHz. Some devices may support multiple rates. Generally, devices targeted at single or multi-PHY applications, where the aggregate PHY bit rate approaches 622 Mbit/s will use the 8-bit data bus structure with a 104 MHz FIFO clock rate. Devices targeted at applications where the aggregate PHY hello Highlight Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 11 bit rate approaches 2.4 Gbit/s will use the 32-bit data bus structure with a 104 MHz FIFO clock rate. 8.4 Packet Interface Synchronization The SPI-3 packet interface supports transmit and receive data transfers at clock rates independent of the line bit rate. As a result, PHY layer devices must support packet rate decoupling using FIFOs. To ease the interface between the Link Layer and PHY layer devices and to support multiple PHY layer interfaces, FIFOs are used. Control signals are provided to both the Link Layer and PHY layer devices to allow either one to exercise flow control. Since the bus interface is point-to-point, the receive interface of the PHY device pushes data to the Link Layer device. For the transmit interface, the packet available status granularity is byte-based. In the receive direction, when the PHY layer device has stored an end-of- packet (a complete small packet or the end of a larger packet) or some predefined number of bytes in its receive FIFO, it sends the in-band address followed by FIFO data to the Link Layer device. The data on the interface bus is marked with the valid signal (RVAL) asserted. A multi-port PHY device with multiple FIFOs would service each port in a round-robin fashion when sufficient data is available in its FIFO. The Link Layer device can pause the data flow by deasserting the enable signal (RENB). In the transmit direction, when the PHY layer device has space for some predefined number of bytes in its transmit FIFO, it informs the Link Layer device by asserting a transmit packet available (TPA). The Link Layer device can then write the in-band address followed by packet data to the PHY layer device using an enable signal (TENB). The Link Layer device shall monitor TPA for a high to low transition, which would indicate that the transmit FIFO is near full (the number of bytes left in the FIFO can be user selectable, but must be predefined), and suspend data transfer to avoid an overflow. The Link Layer device can pause the data flow by deasserting the enable signal (TENB). SPI-3 defines both byte-level and packet-level transfer control in the transmit direction. In byte-level transfer, FIFO status information is presented on a cycle-by-cycle basis. With packet-level transfer, the FIFO status information applies to segments of data. When using byte level transfer, direct status indication must be used. In this case, the PHY layer device provides the transmit packet available status of the selected port (STPA) in the PHY device. As well, the PHY layer device may provide direct access to the transmit packet available status of all ports (DTPA[]) in the PHY device if the number of ports is small. With packet level transfer, the Link Layer device is able to do status polling on the transmit direction. The Link Layer device can Implementation Agreement: OIF-SPI3-01.0 SPI-3 Optical Internetworking Forum 12 use the transmit port ad