PIC24F Family Reference Manual 07 Reset

R eset 7 Section 7. Reset HIGHLIGHTS This section of the manual contains the following topics: 7.1 Introduction .................................................................................................................... 7-2 7.2 Clock Source Selection at Reset ................................................................................... 7-5 7.3 Power-on Reset (POR) .................................................................................................. 7-5 7.4 MCLR Reset .................................................................................................................. 7-7 7.5 Software RESET Instruction (SWR) .............................................................................. 7-7 7.6 Watchdog Timer Reset (WDTR) .................................................................................... 7-7 7.7 Brown-out Reset (BOR) ................................................................................................. 7-8 7.9 Trap Conflict Reset (TCR).............................................................................................. 7-9 7.10 Illegal Opcode Reset (IOPUWR) ................................................................................... 7-9 7.11 Uninitialized W Register Reset ...................................................................................... 7-9 7.12 Registers and Status Bit Values................................................................................... 7-10 7.13 Device Reset to Code Execution Start Time ................................................................ 7-12 7.14 Special Function Register (SFR) Reset States ............................................................ 7-16 7.15 Electrical Specifications ............................................................................................... 7-17 7.16 Design Tips .................................................................................................................. 7-18 7.17 Related Application Notes............................................................................................ 7-19 7.18 Revision History ........................................................................................................... 7-20 © 2010 Microchip Technology Inc. DS39712C-page 7-1 PIC24F Family Reference Manual 7.1 INTRODUCTION The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • MCLR: Pin Reset • SWR: RESET Instruction • WDTR: Watchdog Timer Reset • BOR: Brown-out Reset • TRAPR: Trap Conflict Reset • IOPUWR: Illegal Opcode/Uninitialized W Register Reset Figure 7-1 displays a simplified block diagram of the Reset module. Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known “Reset state”. Most registers are unaffected by a Reset; their status is unknown on Power-on Reset (POR) and unchanged by all other Resets. All types of device Resets will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 7-1). A POR will clear all bits, except for the BOR and POR bits (RCON<1:0>) which are set. Users may set or clear any of the bits at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset. The RCON register also has other bits associated with the Watchdog Timer (WDT) and device power-saving states. For more information on the function of these bits, refer to Section 7.12.1 “Using the RCON Status Bits”. Figure 7-1: Reset System Block Diagram Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. MCLR VDD VDD Rise Detect POR Sleep or Idle Brown-out Reset RESET Instruction WDT Module Glitch Filter BOR Trap Conflict Illegal Opcode Uninitialized W Register SYSRST Voltage Regulator Enable Only in Devices with On-Chip Regulator DS39712C-page 7-2 © 2010 Microchip Technology Inc. Section 7. Reset R eset 7 Register 7-1: RCON: Reset Control Register(1) R/W-0 R/W-0 U-0 U-0 U-0 R/C-0 U-0 U-0 TRAPR IOPUWR — — — DPSLP(2) CM PMSLP(2,3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWR SWDTEN(4) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or an uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred bit 13-11 Unimplemented: Read as ‘0’ bit 10 DPSLP: Program Memory Power During Sleep bit(2) 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred bit 9 CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has occurred 0 = A Configuration Mismatch Reset has not occurred bit 8 PMSLP: Program Memory Power During Sleep Control bit(2,3) 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep; voltage regulator enters Standby mode bit 7 EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred bit 6 SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed bit 5 SWDTEN: Software WDT Enable/Disable bit(4) 1 = WDT is enabled 0 = WDT is disabled bit 4 WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: Implemented on select PIC24F devices only; otherwise unimplemented, read as ‘0’. 3: This bit is named VREGS in some earlier PIC24F devices, with a different description of the bit’s functionality. Regardless of the name or description, its function in power reduction is identical in all devices. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. © 2010 Microchip Technology Inc. DS39712C-page 7-3 PIC24F Family Reference Manual bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred; the BOR is also set after a Power-on Reset 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Register 7-1: RCON: Reset Control Register(1) (Continued) Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: Implemented on select PIC24F devices only; otherwise unimplemented, read as ‘0’. 3: This bit is named VREGS in some earlier PIC24F devices, with a different description of the bit’s functionality. Regardless of the name or description, its function in power reduction is identical in all devices. 4: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS39712C-page 7-4 © 2010 Microchip Technology Inc. Section 7. Reset R eset 7 7.2 CLOCK SOURCE SELECTION AT RESET If clock switching is enabled (OSWEN), the system clock source at device Reset is chosen, as displayed in Table 7-1. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 6. “Oscillator” for further details. Table 7-1: Oscillator Selection vs. Type of Reset (Clock Switching Enabled) 7.3 POWER-ON RESET (POR) The POR monitors the core power supply for adequate voltage levels to ensure proper chip oper- ation. There are two threshold voltages associated with a POR. The first voltage is the device threshold voltage, VPOR. The device threshold voltage is the voltage at which the POR module becomes operable. The second voltage associated with a POR event is the POR circuit threshold voltage. Once the correct threshold voltage is detected, a power-on event occurs and the POR module hibernates to minimize current consumption. A power-on event generates an internal POR pulse when a VDD rise is detected. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR pulse. In particular, VDD must fall below VPOR before a new POR is initiated. For more information on the VPOR and VDD rise rate specifications, refer to the “Electrical Characteristics” section of the specific device data sheet. The POR pulse resets the POR timer and places the device in the Reset state. The POR also selects the device clock source identified by the oscillator Configuration bits. After the POR pulse is generated, the POR circuit inserts a small delay, TPOR, which is nominally 5 s and ensures that internal device bias circuits are stable. After the expiration of TPOR, a delay, TSTARTUP, is always inserted. TSTARTUP is applied every time the device resumes operation after any power-down. In the devices with an on-chip regulator, the TSTARTUP parameter depends on whether the on-chip voltage regulator is enabled or disabled. When the on-chip voltage regulator is enabled, there is a delay until the regulator can generate a proper voltage level, referred to as TVREG. During this time, code execution is disabled. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed 64 ms nominal delay at device start-up. The PWRT is used to extend the duration of a power-up sequence when the on-chip voltage regulator is disabled and the core is supplied from an external power supply. Hence, the TSTARTUP delay can either be TVREG (for devices using an on-chip voltage regulator), or the Power-up Timer delay TPWRT (for devices not using a regulator). The power-on event sets the BOR and POR status bits (RCON<1:0>). In some devices, the PWRT can be disabled by using the device Configuration bit. After TSTARTUP expires, an additional start-up time for the system clock (either TOST, TFRC or TLPRC, depending on the source) occurs while the clock source becomes stable. Code execution is delayed further by a small delay, designated as TRST. The TRST delay is required to transfer the configuration values from Flash Configuration Words (FCW) in the pro- gram memory into the Configuration registers, and occurs after any device Reset. SYSRST is released and the device is no longer held in Reset, but the device clocks are prevented from running during TRST, as depicted in Figure 7-2. Once all of the delays have expired, the system clock is released and code execution can begin. Refer to Section 7.15 “Electrical Specifications” for more information on the values of the delay parameters. Reset Type Clock Source Selected Based on POR Oscillator Configuration Bits FNOSC<2:0>BOR MCLR COSC Control bits OSCCON<14:12> WDTR SWR TRAPR IOPUWR Note: Some device data sheets use the term, TPM (Program Memory Available Delay), in place of TVREG. The terms can be considered to be interchangeable. © 2010 Microchip Technology Inc. DS39712C-page 7-5 PIC24F Family Reference Manual Figure 7-2: POR Module Timing Sequence for Rising VDD TPOR VDD VPOR POR Circuit Threshold Voltage SYSRST TSTARTUP(1) Internal Power-on Reset Pulse Occurs and Begins POR Delay Time, TPOR POR Circuit is Initialized at VPOR Time System Clock is Started After TSTARTUP Delay Expires TRST System Clock Released and Code Execution Begins POR PWRT System Clock NOTE 1: TVREG if the on-chip regulator is enabled or TPWRT if the on-chip regulator is disabled. 2: Timer and interval are determined by the initial start-up oscillator configuration; TOSC is for external oscillator modes, TFRC is for the FRC oscillator or TLPRC for the internal 31 kHz RC oscillator. (Note 2) Oscillator Delay(2) System Reset is Released After Clock is Stable Note: When the device exits the Reset condition (begins normal operation), the device operating parameters (voltage, frequency, temperature, etc.) must be within their operating ranges; otherwise, the device will not function correctly. The user must ensure that the delay between the time power is first applied and the time SYSRST becomes inactive is long enough to get all operating parameters within the specification. DS39712C-page 7-6 © 2010 Microchip Technology Inc. Section 7. Reset R eset 7 7.3.1 Using the POR Circuit To take advantage of the POR circuit, just tie the MCLR pin directly to VDD. This will eliminate external RC components usually needed to create a POR delay. A minimum rise time for VDD is required. Refer to the “Electrical Characteristics” section of the specific device data sheet for more information. Depending on the application, a resistor may be required between the MCLR pin and VDD. This resistor can be used to decouple the MCLR pin from a noisy power supply rail. Figure 7-3 displays a possible POR circuit for a slow power supply ramp up. The external POR circuit is only required if the device would exit Reset before the device VDD is in the valid operating range. The diode, D, helps discharge the capacitor quickly when VDD powers down. Figure 7-3: External Power-on Reset Circuit (for Slow VDD Rise Time) 7.4 MCLR RESET Whenever the MCLR pin is driven low, the device asynchronously asserts SYSRST, provided the input pulse on MCLR is longer than a certain minimum width, SY10 (see Section 7.15 “Electrical Specifications”). When the MCLR pin is released, SYSRST is also released. The Reset vector fetch starts after the expiration of the TRST delay, starting from the SYSRST release. The processor continues to use the existing clock source that was in use before the MCLR Reset occurred. The EXTR status bit (RCON<7>) is set to indicate the MCLR Reset. 7.5 SOFTWARE RESET INSTRUCTION (SWR) Whenever the RESET instruction is executed, the device asserts SYSRST. This Reset state does not re-initialize the clock. The clock source that is in effect prior to the RESET instruction remains in effect. SYSRST is released at the next instruction cycle, but the Reset vector fetch starts only after the TRST delay. 7.6 WATCHDOG TIMER RESET (WDTR) Whenever a Watchdog Timer time-out occurs, the device asynchronously asserts SYSRST. The clock source remains unchanged. Note that a WDT time-out during Sleep or Idle mode will wake-up the processor, but NOT reset the processor. For more information, refer to Section 9. “Watchdog Timer (WDT)”. Note 1: The value of R should be low enough so that the voltage drop across it does not violate the VIH specification of the MCLR pin. 2: R1 limits any current flowing into MCLR from external capacitor, C, in the event of MCLR/VPP pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). R1(2) MCLR PIC24F R(1)D C VDD VDD © 2010 Microchip Technology Inc. DS39712C-page 7-7 PIC24F Family Reference Manual 7.7 BROWN-OUT RESET (BOR) When the on-chip regulator is enabled, PIC24F family devices have a simple brown-out capabil- ity. BOR is applicable only when the regulator is enabled. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<0>). Refer to Section 7.15 “Electrical Specifications” for further details. 7.7.1 Detecting BOR When the BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to ‘0’ in the software immediately after any POR event. If the BOR bit is ‘0’ while POR is ‘1’, it can be reliably assumed that a BOR event has occurred. 7.7.2 Deep Sleep BOR (DSBOR) (Select Devices Only) For devices with Deep Sleep capability, an independent Deep Sleep BOR (DSBOR) circuit pro- vides simple BOR/POR protection during Deep Sleep operation. Rather than trigger a Reset in its own right, the DSBOR re-arms the regular POR circuit to ensure a device Reset if VDD drops below the POR threshold during Deep Sleep operation. The DSBOR operates on a single trip point of 2.0V nominal. Because it is designed for very low-current consumption, its accuracy may vary. DSBOR events (BOR and POR) are monitored through the DSCON and DSWAKE registers, respectively. Refer to Section 39. “Power-Saving Features with Deep Sleep” for a more detailed discussion. The DSBOR circuit can be selectively enabled or disabled using the DSBOREN Configuration bit. By default, the circuit is enabled. Figure 7-4: Brown-out Situations Note: As with other BOR events in other power-saving modes, both the POR and the BOR are set when the device exits from the Deep Sleep mode. VDDCORE SYSRST VBOR VDDCORE SYSRST VBOR VDDCORE SYSRST VBOR VDDCORE Dips Again Before TPWRT + TRST Expires TVREG + TRST TVREG + TRST TVREG + TRST DS39712C-page 7-8 © 2010 Microchip Technology Inc. Section 7. Reset R eset 7 7.8 CONFIGURATION MISMATCH RESET To maintain the integrity of the stored configuration values, all device Configuration bits are implemented as a complementary set of register bits. For each bit, as the actual value of the register is written as ‘1’, a complementary value, ‘0’, is stored in its corresponding background register and vice versa. The bit pairs are compared every time, including Sleep mode. During this comparison, if the Configuration bit values are not found opposite to each other, a Configuration Mismatch event is generated which causes a device Reset. If a device Reset occurs as a result of a Configuration Mismatch, the CM status bit (RCON<9>) is set. 7.9 TRAP CONFLICT RESET (TCR) A Trap Conflict Reset (TCR) occurs when a hard and a soft trap occur at the same time. The TRAPR status bit (RCON<15>) is set on this event. Refer to Section 8. “Interrupts” for more information on traps. 7.10 ILLEGAL OPCODE RESET (IOPUWR) A device Reset is generated if the device attempts to execute an illegal opcode value that was fetched from program memory. If a device Reset occurs as a result of an illegal opcode value, the IOPUWR status bit (RCON<14>) is set. The Illegal Opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the Illegal Opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. 7.11 UNINITIALIZED W REGISTER RESET The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. An attempt to use an uninitialized register as an Address Pointer causes a device Reset and sets the IOPUWR status bit (RCON<14>). © 2010 Microchip Technology Inc. DS39712C-page 7-9 PIC24F Family Reference Manual 7.12 REGISTERS AND STATUS BIT VALUES Status bits from the RCON register are set or cleared differently in different Reset situations, as indicated in Table 7-2. Table 7-2: Status Bits, Their Significance and the Initial