8080 汇编(8080 compilation)
8080 汇编(8080 compilation)
Order (long shift)
JMP unconditional transfer instruction
CALL procedure call
The RET/RETF procedure returns
2> conditional transfer instruction (short transfer, -128 to
+127 distance)
(if and only if (SF, XOR, OF) =1, OP1 loop control instruction (short transfer)
LOOP CX does not loop at zero
LOOPE/LOOPZ CX is not zero and indicates Z=1 when it is loop
LOOPNE/LOOPNZ CX is not zero and indicates Z=0 when it is loop
PUSH, POP
Function: press operands into or take out the stack
Syntax: PUSH operand, POP operand
Format: PUSH, R, PUSH, M, PUSH, data, POP, R,, POP, M
PUSHF, POPF, PUSHA, POPA
Stack instruction group
Format: PUSHF, POPF, PUSHA, POPA
LEA, LDS, LES
Function: take address to register
Syntax: LEA, R, m, LDS, R, m, LES, R, M
XLAT (XLATB)
Function: look-up table instruction
Syntax: XLAT, XLAT, M
arithmetic operation
ADD, ADC
Function: addition instruction
Syntax: ADD, OP1, OP2, ADC, OP1, OP2
Format: ADD, R1, R2, ADD, R, m, ADD, m, R, ADD, R, data
Impact flags: C, P, A, Z, S, O
SUB, SBB
Function: subtraction instruction
Syntax: SUB, OP1, OP2, SBB, OP1, OP2
Format: SUB, R1, R2, SUB, R, m, SUB, m, R, SUB, R, data, SUB,
m, data
Impact flags: C, P, A, Z, S, O
INC, DEC
Function: add or subtract one from the value of OP
Syntax: INC, OP, DEC, OP
Format: INC, r/m, DEC, r/m
Impact flags: P, A, Z, S, O
NEG
Function: inverting the symbol of OP (binary complement)
Syntax: NEG OP
Format: NEG r/m
Impact flags: C, P, A, Z, S, O
MUL, IMUL
Function: multiply instruction
Syntax: MUL, OP, IMUL, OP
Format: MUL, r/m, IMUL, r/m
Impact flags: C, P, A, Z, S, O (IMUL only affects the S flag)
DIV, IDIV
Function: Division instruction
Syntax: DIV, OP, IDIV, OP
Format: DIV, r/m, IDIV, r/m
CBW, CWD
Function: extended instruction with signed number
Syntax: CBW CWD
AAA, AAS, AAM, AAD
Function: non pressure BCD code operation adjustment command
Syntax: AAA, AAS, AAM, AAD
Impact flags: A, C (AAA, AAS), S, Z, P (AAM, AAD)
DAA, DAS
Function: compress BCD code, adjust instruction
Syntax: DAA DAS
Impact flags: C, P, A, Z, S
Bit arithmetic instruction set
AND, OR, XOR, NOT, TEST
Function: perform logical operations between BIT and BIT
Syntax: AND, r/m, r/m/data, OR, r/m, r/m/data, XOR, r/m, r/m/data, TEST, r/m, r/m/data, NOT, r/m
Impact flags: C, O, P, Z, NOT, S (where two flags of C and O are set to 0), and the instruction does not affect any flag bits
SHR, SHL, SAR, SAL
Shift instruction
Syntax: SHR, r/m, data/CL, SHL, r/m, data/CL, SAR, r/m, data/CL,
SAL, r/m, data/CL
Impact flags: C, P, Z, S, O
ROR, ROL, RCR, RCL
Function: cyclic shift instruction
Syntax: ROR, r/m, data/CL, ROL, r/m, data/CL, RCR, r/m, data/CL,
RCL, r/m,
Data/CL
Impact flags: C, P, Z, S, O
Program flow control instruction set
CLC, STC, CMC
Function: set carry flag
Syntax: CLC, STC, CMC
Flag bit: C
CLD, STD
Function: set the direction sign
Syntax: CLD STD
Flag bit: D
CLI, STI
Function: setting interrupt flag
Syntax: CLI STI
Flag bit: I
CMP
Function: compare the values of OP1 and OP2
Syntax: CMP, r/m, r/m/data
Flag bits: C, P, A, Z, O
JMP
Function: jump to the specified address
Syntax: JMP address
JXX
Function: when a given condition is established, jump to the
specified address
Syntax: JXX address
Note:
A: ABOVE, set up when C=0, Z=0
B: BELOW, set up when C=1
C: CARRY, when the CXZ: CX register was established. The value
is 0 (ZERO) was
E: EQUAL, set up when Z=1
G: GREATER (greater than) when Z=0 and S=0 are established
L: LESS (less than) when S is not zero
N: NOT (the opposite condition) should be used in conjunction
with other symbols
O:, OVERFLOW, O=1 set up
P:, PARITY, P=1 set up
PE:, PARITY, EVEN, P=1, set up
PO:, PARITY, ODD, P=0, set up
S:, SIGN, S=1 set up
Z:, ZERO, Z=1 set up
LOOP
Function: cyclic instruction set
Syntax: LOOP address
LOOPE (Z)
Address LOOPNE (Z) address
Flag bit: no
CALL, RET
Function: subroutine call, return instruction
Syntax: CALL address, RET, RET, n
Flag bit: no
INT, IRET
Functions: interrupts, calls, and return instructions
Syntax: INT, N, IRET
Flag: when executing the INT, CPU will automatically sign the register value into the stack, in the implementation of IRET
will mark the value in the register stack.
String operations instruction set
MOVSB, MOVSW, MOVSD
Function: String transfer instruction
Syntax: MOVSB, MOVSW, MOVSD
Flag bit: no
CMPSB, CMPSW, CMPSD
Function: string comparison instruction
Syntax: CMPSB, CMPSW, CMPSD
Flag bits: C, P, Z, S, O
SCASB, SCASW
Function: string search instruction
Syntax: SCASB SCASW
Flag bits: C, P, Z, S, O
LODSB, LODSW, STOSB, STOSW
Function: String loading or storage instruction
Syntax: LODSB, LODSW, STOSB, STOSW
Flag bit: no
REP, REPE, REPNE
Function: repeating prefix instruction set
Syntax: REP instruction, S REPE instruction, S REPNE
instruction, S
Flag bit: according to instruction S
Method 1: swap up and down
Method two: equivalent replacement method
The most difficult to master, you need a part of the compilation
of knowledge
Such as: push - pop, push, eax, eax, pop
Je - JNZ JE 41000 changed to JNZ 41000
Add - sub, add, ECX, 2, sub, ECX, -2
JE changed to JMP
TEST changed to XOR
JLE changed to JL
NOP two.JMP addresses
Transposition of MOV and XOR
ADD transposition
JE changed to JMP
75 change 74
TEST changed to OR
JBE changed to JB
38 change 37
Transposition of CALL and MOV
JA changed to JG
JNZ changed to JMP
TEST changed to AND
Discover a new instruction for equivalent JNZ
The general change is JNZ - Ja
Can also be changed to JNZ - jno
Data transfer instruction
- - - - - - - - - - - - - - - - - - - -
They transfer data between memory and registers, registers, and between input and output ports.
1. Universal data transfer instruction.
MOV transfers words or bytes.
MOVSX first symbol extension, and then transfer.
MOVZX first zero extension, and then transfer.
PUSH presses the words onto the stack.
POP pops up the word stack.
PUSHA presses AX, CX, DX, BX, SP, BP, SI, DI in the stack in turn.
POPA pops up the stack in DI, SI, BP, SP, BX, DX, CX, AX, in turn.
PUSHAD presses EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI in the stack in turn.
POPAD pops up the stack in EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX, in turn.
BSWAP switches the order of bytes in a 32 bit register
XCHG swap words or bytes. (at least one operand is a register, and segment registers cannot be used as operands)
CMPXCHG compares and exchanges operands. (the second operand must be the accumulator AL/AX/EAX)
XADD first swap and then accumulate. (results in the first operand)
XLAT byte look-up table conversion.
- BX points to the starting point of a 256 byte table, and AL is the index value of the table (0-255, that is, the index value of the table
0-FFH) returns AL as table look-up result. ([BX+AL]->AL)
2. Input / output port transfer instruction.
IN I/O port input. (Syntax: IN accumulator, {port number / DX})
OUT I/O port output. (Syntax: OUT {DX}, port number, accumulator)
The input and output ports are specified immediately, with a range of 0-255; specified by the register DX,
Its range is 0-65535.
3. Destination address transfer instruction.
LEA loads valid addresses.
Example: LEA, DX, string; saves the offset address to DX.
LDS sends the target pointer and loads the pointer content into DS.
Example: LDS, SI, string; the segment address: offset address is saved to DS:SI.
LES sends the target pointer and loads the pointer content into ES.
Example: LES, DI, string; the segment address: offset address is saved to ES:DI.
LFS sends the target pointer and loads the pointer content into FS.
Example: LFS, DI, string; the segment address: offset address is saved to FS:DI.
LGS sends the target pointer and loads the pointer content into GS.
Example: LGS, DI, string; the segment address: offset address is saved to GS:DI.
LSS sends the target pointer and loads the pointer content into SS.
Example: LSS, DI, string; the segment address: offset address is saved to SS:DI.
4. Flag transfer instruction.
The LAHF flag register transmits the flag to the AH.
The SAHF flag register transfers the contents of the AH into the flag register.
PUSHF flag stack.
POPF marks the stack.
PUSHD 32 bit flag stack.
The POPD 32 bit flags the stack.
Two, arithmetic operations instruction
- - - - - - - - - - - - - - - - - - - -
ADD addition.
ADC carry addition.
INC plus 1.
ASCII code adjustment of AAA addition.
Decimal adjustment of DAA addition.
SUB subtraction.
SBB subtraction with borrow.
DEC minus 1.
NEC reverse (minus 0).
CMP comparison. (two operands are subtracted, only flag bits
are not modified, and results are not returned).
ASCII code tuning for AAS subtraction.
Decimal adjustment of DAS subtraction.
MUL unsigned multiplication.
IMUL integer multiplication.
The above two, the results sent back to AH and AL (byte
operations), or DX and AX (word computing),
ASCII code tuning for AAM multiplication.
DIV unsigned division.
IDIV integer division.
The above two, the results sent back:
The quotient returns AL, and the remainder returns AH (byte operation);
Or quotient returns AX, and the remainder returns DX (word operation).
ASCII code adjustment for AAD division.
CBW bytes converted to words. (extending the byte symbol in AL to AH)
The word "CWD" is converted into two characters. (extend the symbols of words in AX to DX)
The word "CWDE" is converted into two characters. (extending the word symbols in AX to EAX)
CDQ double word extensions. (extend the symbols of words in EAX to EDX)
Three 、 logical operation instruction
-- -- -- -- -- -- -- -- -- -- --
AND and operation.
OR or operation.
XOR XOR operation.
NOT take reverse.
TEST test. (two operands and operations, modify flag bits only, and do not send back results).
SHL logic moves left.
SAL arithmetic left shift. (=SHL)
SHR logical right shift.
SAR arithmetic right shift. (=SHR)
ROL loop left shift.
ROR loop right shift.
RCL moves left by loop of carry.
RCR moves right by loop of carry.
The shift times of the above eight shift instructions are up to 255 times.
Shift once,
Operator code can be used directly. Such as SHL, AX, 1.
When shift >1 times, the shift number is given by register CL.
Such as MOV, CL, 04
SHL, AX, CL
Four, serial instructions
- - - - - - - - - - - - - - - --
DS:SI source string segment register: source string index.
ES:DI target string segment register: target string index.
CX repeat count counter.
AL/AX scan value.
The D flag 0 indicates that the SI and DI should be automatically incremented during repetition, and 1 indicates automatic decrement.
The Z flag is used to control the end of the scan or comparison operation.
MOVS string transfer.
(MOVSB transfer characters). MOVSW transfer word. MOVSD transfers two characters. )
CMPS string comparison.
(CMPSB compare characters. CMPSW compare words. )
SCAS serial scan.
Compare the contents of AL or AX with the target string, and compare the results to the flag bits.
LODS load string.
Load the elements (words or bytes) in the source string one by one into AL or AX.
(LODSB transfer characters). LODSW transfer word. LODSD transfers two characters. )
STOS save string.
Is the inverse process of LODS.
REP repeat when CX/ECX<>0.
REPE/REPZ repeats when ZF=1 or the comparison results are equal and CX/ECX<>0.
REPNE/REPNZ repeats when the ZF=0 or the comparison results are not equal and CX/ECX<>0.
REPC repeats when CF=1 and CX/ECX<>0.
REPNC repeats when CF=0 and CX/ECX<>0.
Five, program transfer instructions
- - - - - - - - - - - - - - - -
1> unconditional transfer instruction (long shift)
JMP unconditional transfer instruction
CALL procedure call
RET/RETF process returns.
2> conditional transfer instruction (short transfer, -128 to +127 distance)
(if and only if (SF, XOR, OF) =1, OP1 JA/JNBE is not less than or not equal to the transfer.
JAE/JNB greater than or equal to transfer.
JB/JNAE is less than metastasis.
JBE/JNA less than or equal to transfer.
The above four tests the results of unsigned integer operations (marks C and Z).
JG/JNLE is greater than metastasis.
JGE/JNL greater than or equal to transfer.
JL/JNGE is less than metastasis.
JLE/JNG less than or equal to transfer.
The above four tests the results of signed integer operations
(marks S, O, and Z).
JE/JZ is equal to transfer.
JNE/JNZ is not equal to time shift.
JC has carry time transfer.
JNC transfer without carry.
JNO does not overflow when transferred.
JNP/JPO if the parity is odd.
The JNS symbol is shifted to '0'.
JO overflow transfer.
JP/JPE even if the parity is even.
The JS symbol is shifted to '1'.
3> loop control instruction (short transfer)
LOOP CX does not loop at zero.
LOOPE/LOOPZ CX is not zero and flags Z=1 cycles.
LOOPNE/LOOPNZ CX is not zero and flags Z=0 cycles.
JCXZ CX transfers at zero.
JECXZ ECX transfers at zero.
4> interrupt instruction
INT interrupt instruction
INTO overflow interrupt
IRET interrupt return
5> processor control instruction
The HLT processor is paused until the interrupt or reset signal
is continued.
WAIT when the chip TEST is high, CPU is put into the waiting
state.
ESC converts to an external processor.
LOCK blocked bus.
NOP empty operation.
STC carry carry flag bit.
CLC clear carry flag bit.
CMC carry flag back.
STD sets the direction flag bit.
CLD clear heading bit.
STI sets the interrupt enable bits.
CLI clear interrupt enable bit.
Six, pseudo directive
- - - - - - - - - - - - - - - --
DW defines the word (2 bytes).
PROC definition process.
The ENDP process is over.
SEGMENT definition segment.
ASSUME creates segment register addressing.
End of paragraph ENDS.
END program is over.
I. mechanical code, also known as machine code
UltraEdit opens, and when you edit the EXE file, you'll see
Lots of 0,1,2,3,4,5,6,7,8,9, A, B, C, D, E,
F composed of digital, these digital
It's machine code
When modifying a program, you must modify the machine code to modify the EXE file
Two. Need to master all the assembly knowledge (only so much)
Not easy to understand, you can first force back to live, mixed face cooked, and then slowly understand
CMP, a, B compare a and B
MOV, a, and B send the value of B to a
RET returns the main program
NOP has no effect. The abbreviation "no operation" in English means "do nothing" (machine code 90). The meaning of * * machine code is shown above
(explanation: when UltraEdit opens the edit EXE file, you see 90, equivalent to the assembly statement NOP)
Call call subroutine
If JE or JZ is equal, jump (machine code 74 or 0F84)
If jne or JNZ is not equal, jump (machine code 75 or 0F85)
JMP unconditional jump (machine code EB)
JB jump if less than
JA jump if larger than
JG jump if larger than
Jge jump if it is greater than or equal to
JL jump if less than
JLE jump if less than equal
Pop stack
Push stack
Three. Common changes (machine code)
74=>75 74=>90 74=>EB
75=>74 75=>90 75=>EB
Jnz->nop
75->90 (corresponding machine code modification)
JNZ - > JMP
75 - > EB (the corresponding machine code modification)
JNZ - > JZ
75->74 (normal) 0F 0F (85 - > 84 special cases, sometimes, the corresponding machine code modification)
Four. Different modification methods for two different situations
1. modify to JMP
Je (jne, JZ, JNZ) =>jmp the corresponding machine code EB (the first jump found in the error message), JMP's role is absolute jump, unconditional jump, so as to skip the following error messages
XXXXXXXXXXXX error information, for example: the registration code is wrong, sorry, the registered version, "Function Not Avaible... In Demo" or "Command Not Avaible" or "Can' t save in; Shareware/Demo" (we want to skip it, do not let it appear)
...
...
Where is the correct route for XXXXXXXXXXXX?
2. modify to NOP
Je (jne, JZ, JNZ) =>nop the corresponding machine code 90 (the correct information to the first jump found on) the role of NOP is to remove the jump, the jump is invalid, out of action, so that the program successfully came to follow the correct information at the following
XXXXXXXXXXXX correct information, such as: successful registration, thank you for your support, etc. (we hope that it will not be skipped, let it appear, the program must come here smoothly)
...
...
XXXXXXXXXXXX error messages (we don't want to skip here or let it happen) they transfer data between memory and registers, registers, and between input and output ports
1. general data transfer instructions
MOV transfers words or bytes
MOVSX first symbol extension, and then transfer
MOVZX first zero extension, and then transfer
PUSH presses the word onto the stack
POP pops up the word stack
PUSHA presses AX, CX, DX, BX, SP, BP, SI, DI in the stack in turn
POPA pops up the stack in DI, SI, BP, SP, BX, DX, CX, AX, in turn
PUSHAD presses EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI in the stack in turn
POPAD pops up the stack in EDI, ESI, EBP, ESP, EBX, EDX, ECX, EAX, in turn
BSWAP switches the order of bytes in a 32 bit register
XCHG swap words or bytes. (at least one operand is a register, and segment registers cannot be used as operands)
CMPXCHG compares and exchanges operands. (the second operand must be the accumulator AL/AX/EAX)
XADD first swap and then accumulate (the result is in the first operand)
XLAT byte look-up table conversion
- BX points to the starting point of a 256 byte table, and AL is the index value of the table (0-255, that is, the index value
of the table
0-FFH) returns AL as table look-up result ([BX+AL]->AL)
2. input and output ports transmit instructions
IN I/O input port. (Syntax: IN accumulator, {port number / DX})
OUT I/O port output
(Syntax: OUT {DX}, port number, accumulator)
The input and output ports are specified immediately, with a range of 0-255; specified by the register DX,
Its range is 0-65535.
3. destination address transfer instruction
LEA loads valid addresses
Example: LEA, DX, string; saves the offset address to DX.
LDS sends the target pointer and loads the pointer content into DS.
Example: LDS, SI, string; the segment address: offset address is saved to DS:SI.
LES sends the target pointer and loads the pointer content into ES.
Example: LES, DI, string; the segment address: offset address is saved to ESI.
LFS sends the target pointer and loads the pointer content into FS.
Example: LFS, DI, string; the segment address: offset address is saved to FSI.
LGS sends the target pointer and loads the pointer content into GS.
Example: LGS, DI, string; the segment address: offset address is saved to GSI.
LSS sends the target pointer and loads the pointer content into SS.
Example: LSS, DI, string; the segment address: offset address is saved to SSI.
4. flag transfer instructions
The LAHF flag register transmits the flag to the AH.
The SAHF flag register transfers the contents of the AH into the flag register
PUSHF flags into the stack
POPF marks the stack
PUSHD 32 bit flag into the stack
POPD 32 bits indicate the stack
Two, arithmetic operations instruction
- - - - - - - - - - - - - - - - - - - - - - - - - - --
ADD addition
ADC with carry addition
INC plus 1.
AAA addition ASCII code adjustment
Decimal adjustment of DAA addition
SUB subtraction
SBB subtraction with borrow.
DEC minus 1.
NEC reverse (minus 0)
CMP compare. (two operand subtraction, modify flag bit only,
not echo result)
ASCII subtraction AAS code adjustment
Decimal adjustment of DAS subtraction
MUL unsigned multiplication
IMUL integer multiplication
The above two, the results sent back to AH and AL (byte operations), or DX and AX (word computing),
ASCII code adjustment for AAM multiplication
DIV unsigned Division
IDIV integer division
The above two, the results sent back:
The quotient returns AL, and the remainder returns AH (byte operation);
Or the quotient returns AX, and the remainder returns DX (word operation)
ASCII code adjustment for AAD Division
CBW bytes are converted to words. (extending the symbols of bytes in AL to AH)
The word "CWD" is converted to "double word" (extending the word
symbols in AX to DX)
The word "CWDE" is converted to "double word" (extending the word symbols in AX to EAX)
CDQ double word extension (extending the word symbols in EAX to EDX)
Three 、 logical operation instruction
- - - - - - - - - - - - - - - - - - - - - - - - - - --
AND and arithmetic
OR or arithmetic
XOR XOR operation
NOT take the reverse
TEST test. (two operand and operation, modify flag bit only, not echo result)
SHL logic left shift
SAL arithmetic left shift. (=SHL)
The SHR logic moves right
SAR arithmetic right shift. (=SHR)
ROL loop left shift
The ROR loop moves right
RCL moves left by loop of carry
RCR moves right by loop of carry
The shift times of the above eight shift instructions can reach up to 255 times
Once shifted, you can use the opcode directly, such as SHL, AX, 1.
When shift >1 times, the shift number is given by register CL
Such as MOV, CL, 04
SHL, AX, CL
Four, serial instructions
- - - - - - - - - - - - - - - - - - - - - - - - - - --
DS:SI source string segment register: source string index
ESI target string segment register: target string index
CX repeat count counter
AL/AX scan value
The D flag 0 indicates that the SI and DI should be automatically incremented during repetition, and 1 indicates automatic decrement
The Z flag is used to control the end of the scan or comparison operation
MOVS string transfer
(MOVSB transport characters. MOVSW transfer words. MOVSD transfer double characters.)
CMPS string comparison
(CMPSB compare characters. CMPSW compare words.)
SCAS serial scan
Compare the contents of AL or AX with the destination string, and compare the results to the flag bits
LODS load string
Load the elements (words or bytes) in the source string one by one into AL or AX
(LODSB transport characters. LODSW transfer words. LODSD transfer double characters.)
STOS save string
Is the inverse process of LODS
REP repeat when CX/ECX<>0
REPE/REPZ repeats when ZF=1 or the comparison results are equal and CX/ECX<>0
REPNE/REPNZ repeats when the ZF=0 or the comparison results are not equal and CX/ECX<>0
REPC repeat when CF=1 and CX/ECX<>0
REPNC repeat when CF=0 and CX/ECX<>0
Five, program transfer instructions
- - - - - - - - - - - - - - - - - - - - - - - - - - --
1> unconditional transfer instruction (long shift)
JMP unconditional transfer instruction
CALL procedure call
The RET/RETF procedure returns
2> conditional transfer instruction (short transfer, -128 to +127 distance)
(if and only if (SF, XOR, OF) =1, OP1 loop control instruction (short transfer)
LOOP CX does not loop at zero
LOOPE/LOOPZ CX is not zero and indicates Z=1 when it is loop
LOOPNE/LOOPNZ CX is not zero and indicates Z=0 when it is loop
JCXZ CX transfers at zero
JECXZ ECX transfers at zero
4> interrupt instruction
INT interrupt instruction
INTO overflow interrupt
IRET interrupt return
5> processor control instruction
The HLT processor is paused until the interrupt or reset signal
is continued
WAIT when the chip TEST is high, CPU is put into the waiting
state
ESC converts to an external processor
LOCK blocked the bus
NOP empty operation
STC put carry flag bits
CLC clear carry flag bit
CMC carry flag take reverse
STD sets the direction flag bit
CLD clear heading bit
STI sets the interrupt enable bits
CLI clear interrupts allow bits
Six, pseudo directive
- - - - - - - - - - - - - - - - - - - - - - - - - - --
DW defines the word (2 bytes)
The PROC definition process
The ENDP process is over
SEGMENT definition segment
ASSUME creates segment register addressing
End of paragraph ENDS
END program is over