MAG3110（指南针）

Document Number: MAG3110 Rev 2.0, 02/2011 Freescale Semiconductor Advance Information This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2011. All rights reserved. 3-Axis, Digital Magnetometer Freescale’s MAG3110 is a small, low-power, digital 3-axis magnetometer. The device can be used in conjunction with a 3-axis accelerometer to produce orientation independent accurate compass heading information. It features a standard I2C serial interface output and smart embedded functions. The MAG3110 is capable of measuring magnetic fields with an Output Data Rate (ODR) up to 80 Hz; these output data rates correspond to sample intervals from 12 ms to several seconds. The MAG3110 is available in a plastic DFN package and it is guaranteed to operate over the extended temperature range of -40°C to +85°C. Features • 1.95V to 3.6V Supply Voltage (VDD) • 1.65V to VDD IO Voltage (VDDIO) • Ultra Small 2 mm x 2 mm x 0.85 mm, 0.4 mm Pitch, 10 Pin Package • Full Scale Range ±1000 μT • Sensitivity of 0.10 μT • Noise down to 0.05 μT rms • Output Data Rates (ODR) up to 80 Hz • I2C digital output interface (operates up to 400 kHz Fast Mode) • 7-bit I2C address = 0x0E • Sampled Low Power Mode • RoHS compliant Applications • Electronic Compass • Dead-reckoning assistance for GPS backup • Location-based Services ORDERING INFORMATION Part Number Temperature Range Package Description Shipping MAG3110FCR2 -40°C to +85°C DFN-10 Tape and Reel 10 PIN DFN 2 mm x 2 mm x 0.85 mm CASE 2154 MAG3110 MAG3110: 3-AXIS DIGITAL MAGNETOMETER Top and Bottom View Top View Pin Connections Cap-A VDD NC Cap-R GND GND INT1 SDA VDDIO SCL 1 2 3 4 5 10 9 8 7 6 MAG3110 Application Notes for Reference MAG3110 The following is a list of Freescale Application Notes written for the MAG3110: • AN4246, Calibrating for Soft Iron and Hard Iron Distortions • AN4247, PCB Layout Guidelines and Recommendations • AN4248, Using the MAG3110 Magnetometer for an eCompass Application • AN4249, Using the MAG3110 Magnetometer to Implement a 3-D Pointer 1 Block Diagram and Pin Description 1.1 Block Diagram Figure 1. Block Diagram 1.2 Pin Description Figure 2. Pin Connections Figure 3. Measurement Coordinate System Digital Signal SDA SCL Processing andY-axis Self-Test Clock Oscillator Reference INT1 X-axis Z-axis MUX ADC Control Trim Logic + Regulator VDD VDDIO (TOP VIEW) X Y Z 1 (TOP VIEW) Cap-A VDD NC Cap-R GND GND INT1 SDA VDDIO SCL 1 2 3 4 5 10 9 8 7 6 MAG3110 Sensors Freescale Semiconductor 2 MAG3110 1.3 Application Circuit The device power is supplied through VDD line. Power supply decoupling capacitors (100 nF ceramic) should be placed as near as possible to pins 1 and 2 of the device. VDDIO supplies power for the I/O pins SCL, SDA, and INT1. The control signals SCL and SDA, are not tolerant of voltages more than VDDIO + 0.3 volts. If VDDIO is removed, the control signals SCL and SDA will clamp any logic signals with their internal ESD protection diodes. Figure 4. Electrical Connection Table 1. Pin Description Pin Name Function 1 Cap-A Bypass Cap for Internal Regulator 2 VDD Power Supply, 1.95V – 3.6V 3 NC No Connect – do not connect 4 Cap-R Cap for Reset Pulse 5 GND GND 6 SDA I2C Serial Data (Write = 0x1C; Read = 0x1D) 7 SCL I2C Serial Clock 8 VDDIO Power for I/O Buffers, 1.65V - VDD 9 INT1 Interrupt - Active High Output 10 GND GND SDA VDDIO 1 2 3 4 5 10 9 8 7 6 MAG3110 (Top View) 100 nF 1 μF VDD 100 nF 100 nF SCL INT1 4.7K 100 nF 4.7K Sensors 3 Freescale Semiconductor 2 Operating and Electrical Specifications MAG3110 2.1 Operating Characteristics 2.2 Absolute Maximum Ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 2. Operating Characteristics @ VDD = 1.8 V, T = 25°C unless otherwise noted. Parameter Test Conditions Symbol Min Typ Max Unit Full Scale Range FS ±1000 µT Output Data Range (RAW = 1) -15,000 15,000 bits Output Data Range (RAW = 0) -30,000 30,000 bits Sensitivity So 0.10 µT/bits Sensitivity Change vs. Temperature Tc ±0.1 %/°C Zero Flux Offset Accuracy ±500 µT Zero Flux Change with Temperature Tco ±0.01 µT/°C Hysteresis 1 % Non Linearity Best Fit Straight Line NL -1 ±0.3 1 %FS Temp Sensor Repeatability 1 °C Magnetometer Output Noise OS = 00(1) 1. OS = Over Sampling Ratio. Noise 0.14 µT rms OS = 01 0.1 OS = 10 0.07 OS = 11 0.05 Self-test Output Change(2) X-axis Y-axis Z-axis 2. Self-test is one direction only. Vst 20 LSB 20 LSB 20 LSB Operating Temperature Range Top -40 +85 °C Table 3. Maximum Ratings Rating Symbol Value Unit Supply Voltage VDD -0.3 to +3.6 V Input Voltage on any Control Pin (SCL, SDA) Vin -0.3 to VDD + 0.3 V Maximum Applied Magnetic Field — 100,000 µT Operating Temperature Range Top -40 to +85 °C Storage Temperature Range TSTG -40 to +125 °C Table 4. ESD and Latch-up Protection Characteristics Rating Symbol Value Unit Human Body Model HBM ±2000 V Machine Model MM ±200 V Charge Device Model CDM ±500 V Latch-up Current at T = 85°C — ±100 mA This device is sensitive to mechanical shock. Improper handling can cause permanent damage of the part or cause the part to otherwise fail. This is an ESD sensitive, improper handling can cause permanent damage to the part. Sensors Freescale Semiconductor 4 2.3 Electrical Characteristics MAG3110 Table 5. Electrical Characteristics @ VDD = 2.0V, VDDIO = 1.8V, T = 25°C unless otherwise noted Parameter Test Conditions Symbol Min Typ Max Unit Supply Voltage VDD 1.95 2.4 3.6 V Interface Supply Voltage VDDIO 1.62 VDD V Supply Current in ACTIVE Mode ODR(1) 10 Hz, OS(1) = 11 1. ODR = Output Data Rate; OS = Over Sampling Ratio. Idd 900 µA ODR 10 Hz, OS = 10 480 ODR 10 Hz, OS = 01 280 ODR 10 Hz, OS = 00 140 ODR 5 Hz, OS = 00 70 ODR 1.25 Hz, OS = 00 24 Supply Current Drain in STANDBY Mode Measurement mode off IddStby 2 µA Digital High Level Input Voltage SCL, SDA VIH 0.75*VDDIO V Digital Low Level Input Voltage SCL, SDA VIL 0.3* VDDIO V High Level Output Voltage INT1 IO = 500 µA VOH 0.9*VDDIO V Low Level Output Voltage INT1 IO = 500 µA VOL 0.1* VDDIO V Low Level Output Voltage SDA IO = 500 µA VOLS 0.1* VDDIO V Output Data Rate (ODR) ODR 0.8*ODR ODR 1.2 *ODR Hz Signal Bandwidth BW ODR/2 Hz Boot Time from Power applied to Boot Complete BT 10 ms Turn-on Time(2) 2. Time to obtain valid data from STANDBY mode to ACTIVE Mode. OS = 1 Ton 25 ms Operating Temperature Range Top -40 +85 °C Sensors 5 Freescale Semiconductor 2.4 I2C Interface Characteristics MAG3110 Table 6. I2C Slave Timing Values(1) 1. All values referred to VIH (min) and VIL (max) levels. Parameter Symbol I 2C Fast Mode Unit Min Max SCL Clock Frequency Pull-up = 1 kΩ, Cb = 20 pF Pull-up = 1 kΩ, Cb = 400 pF fSCL 0 0 400 TBD kHz kHz Bus Free Time between STOP and START Condition tBUF 1.3 μs Repeated START Hold Time tHD;STA 0.6 μs Repeated START Set-up Time tSU;STA 0.6 μs STOP Condition Set-up Time tSU;STO 0.6 μs SDA Data Hold Time(2) 2. tHD;DAT is the data hold time that is measured from the falling edge of SCL, applies to data in transmission and the acknowledge. tHD;DAT 50(3) 3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. (4) 4. The maximum tHD;DAT could be must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This device does not stretch the LOW period (tLOW) of the SCL signal. μs SDA Valid Time (5) 5. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). tVD;DAT 0.9(4) μs SDA Valid Acknowledge Time (6) 6. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse). tVD;ACK 0.9(4) μs SDA Set-up Time tSU;DAT 100(7) 7. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time ns SCL Clock Low Time tLOW 1.3 μs SCL Clock High Time tHIGH 0.6 μs SDA and SCL Rise Time tr 20 + 0.1Cb(8) 1000 ns SDA and SCL Fall Time (3) (8) (9) (10) 8. Cb = total capacitance of one bus line in pF. 9. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. 10.In Fast mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. tf 20 + 0.1Cb(8) 300 ns Pulse width of spikes on SDA and SCL that must be suppressed by input filter tSP 50 ns Sensors Freescale Semiconductor 6 MAG3110 Figure 5. I2C Slave Timing Diagram 2.5 General I2C Information The SCL and SDA signals are driven by open-drain buffers and a pull-up resistor is required to make the signals rise to the high state. The value of the pull-up resistors depends on the system I2C clock rate and the capacitance load on the I2C bus. Higher resistance value pull-up resistors consume less power, but have a slower the rise time (due to the RC time constant between the bus capacitance and the pull-up resistor) and will limit the I2C clock frequency. Lower resistance value pull-up resistors consume more power, but enable higher I2C clock operating frequencies. High bus capacitance is due to long bus lines or a high number of I2C devices connected to the bus. A lower value resistance pull-up resistor is required in higher bus capacitance systems. For standard 100 kHz clock I2C, pull-up resistors typically are between 5k and 10 kΩ. For a heavily loaded bus, the pull-up resistor value may need to be reduced. For higher speed 400 kHz or 800 kHz clock I2C, bus capacitance will need to be kept low, in addition to selecting a lower value resistance pull-up resistor. Pull-up resistors for high speed buses typically are about 1 KΩ. In a well designed system with a microprocessor and one I2C device on the bus, with good board layout and routing, the I2C bus capacitance can be kept under 20 pF. With a 1K pull-up resistor, the I2C clock rates can be well in excess of a few megahertz. 3 Modes of Operation Table 7. Modes of Operation Description Mode I2C Bus State Function Description STANDBY I2C communication is possible. Only POR and digital blocks are enabled. Analog subsystem is disabled. ACTIVE I2C communication is possible. All blocks are enabled (POR, Digital, Analog). Sensors 7 Freescale Semiconductor 4 Functionality MAG3110 MAG3110 is a small low-power, digital output, 3-axis linear magnetometer packaged in a 10 pin DFN. The device contains a magnetic transducer for sensing and an ASIC for control and digital I2C communications. 4.1 I2C Serial Interface Communication with the MAG3110 takes place over an I2C bus. The MAG3110 also has an interrupt signal indicating that new magnetic data readings are available. Interrupt driven sampling allows operation without the overhead of software polling. 4.2 Factory Calibration MAG3110 is factory calibrated for sensitivity, offset and temperature coefficient. All factory calibration coefficients are applied automatically by the MAG3110 ASIC before the magnetic field readings are written to registers 0x01 to 0x06 (see section 5). There is no need for the user to apply the calibration correction in the software and the calibration coefficients are not therefore accessible to the user. The offset registers in the addresses 0x09 to 0x0E are not a factory calibration offset but allow the user to define a hard iron offset which can be automatically subtracted from the magnetic field readings (see section 4.3.3). 4.3 Digital Interface There are two signals associated with the I2C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). External pull- up resistors (connected to VDDIO) are needed for SDA and SCL. When the bus is free, both lines are high. The I2C interface is compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards. 4.3.1 General I2C Operation I2C is an asynchronous, open collector driven, addressed and packetized serial bus interface. It is capable of supporting multiple masters and multiple slave devices on the same bus. I2C uses two bi-directional lines, the serial clock line or SCL and the serial data line or SDA. Pull-up resistors are required on both lines. An I2C transaction starts with a start condition (START) and ends with a stop condition (STOP). A START condition is defined as a HIGH to LOW transition on the data line while the clock line is held HIGH. A STOP condition is defined as a LOW to HIGH transition on the data line while the clock line is held HIGH. At all other times, the data line can only change state when the clock line is low. If the data line changes state when the clock is high, the I2C transaction is aborted and the new start or stop condition is recognized. After START has been transmitted by the master, the bus is considered busy. The next byte of data transmitted after START condition is the slave address in the first 7 bits, and the eighth bit is the Read/Write (R/W) bit (read = 1, write = 0). The R/W bit determines whether the I2C master intends on receiving data from the slave – Read mode or intends to transmit data to the slave – Write mode. When an address is sent, each device on the I2C bus compares the first 7 bits after a start condition with its own internal address. If the address matches, the device considers itself addressed by the Master and continues to respond. If the address does not match, the device ignores further bus activity until the next start condition happens. The ninth bit (clock pulse), following each I2C byte is for the acknowledge (ACK) bit. The master releases the SDA line during the ACK period. Because of the pull-up resistor, the data line will tend to float high. To signal ACK back to the master, the slave must then pull the data line low during this clock period. The number of bytes per transfer can be unlimited. If a receiving device can't accept another complete byte of data until it has performed some other function, it can hold the clock line, SCL, low to force the transmitter into a wait state. Data transfer only continues when the receiver is ready for another byte and releases the data line. This delay action is called clock stretching. The MAG3110 device does clock stretching. A data transfer is always terminated by a STOP. The MAG3110 I2C 7-bit device address is 0x0E. In I2C practice, the device address is shifted left by one bit field and a read/ write bit is set in the lowest bit position. The I2C 8-bit write address is 0x1C and the read address is 0x1D. The I2C 8-bit write address is 0x3A and the read address is 0x3B. Please consult the factory for alternate addresses. Table 8. Serial Interface Pin Description Pin Name Pin Description VDDIO IO voltage SCL I2C Serial Clock SDA I2C Serial Data INT Data ready interrupt pin Sensors Freescale Semiconductor 8 See Figure 6 for details on how to perform read/write operations with MAG3110. MAG3110 * Data Bytes Outgoing * Data Bytes Incoming Figure 6. MAG3110 I2C Generic Read/Write Operations 4.3.2 Fast Read Mode When the Fast Read (FR) bit is set (CTRL_REG1, 0x10, bit 2), the MSB 8-bit data is read through the I2C bus. Auto-increment is set to skip over the LSB data. When FR bit is cleared, the complete 16-bit data is read accessing all 6 bytes sequentially (OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB). 4.3.3 User Offset Corrections The 2’s complement user offset correction register values are used to compensate for correcting the X, Y, and Z-axis after device board mount. These values may be used to compensate for hard iron interference. Depending on the setting of the RAW bit (CTRL_REG2, 0x11, bit 5) the magnetic field sample data is corrected with the user offset values (RAW = 0), or can be read out uncorrected for user offset values (RAW = 1). The factory calibration correction is always applied irrespective of the setting of the RAW bit. The factory calibration for gain, offset and temperature compensation is always automatically applied irrespective of the setting of the RAW bit which only controls the subtraction of the user defined hard iron offset. 4.3.4 INT1 The DR_STATUS register (see section 5.1.1) contains the ZYXDR bit which denotes the presence of new measurement data on one or more axes. Software polling can be used to detect the transition of the ZYXDR bit from 0 to 1 but, since the ZYXDR bit is also logically connected to the INT1 pin, a more efficient approach is to use INT1 to trigger a software interrupt when new measurement data is available as follows: 1. Put MAG3110 in ACTIVE mode (CTRL_REG1 = 0bXXXXXX01). 2. Idle until INT1 goes HIGH and activates an interrupt service routine in the user software. 3. Read magnetometer data as required from registers 0x01 to 0x06. INT1 is cleared when register 0x01 OUT_X_MSB is read and this register must therefore always be read in the interrupt service routine. 4. Return to idle in step 2. 4.3.5 Triggered Measurements Set the TM bit in CTRL_REG1 when you want the part to acquire only 1 sample on each axis. See table below for details. Single/Burst Write Operation IIC Start IIC Slave ADDR (R/W bit = 0) MAG3110 Register Address to Start Write Data0* Data1 — IIC STOP Single/Burst Read Operation IIC Start IIC Slave ADDR (R/W bit = 0) MAG3110 Register Address to Start Read IIC Repeated Start IIC Slave ADDR (R/W bit = 1) Data0* Data1 — IIC STOP AC TM Description 0 0 ASIC is in low power standby mode. 0 1 The ASIC shall exit standby mode, perform one measurement cycle based on the programmed ODR and OSR setting, update the I2C data registers and re- enter standby mode. 1 0 The ASIC shall perform continuous measurements based on the current OSR and ODR settings. 1 1 The ASIC shall continue current measurement at fastest applicable ODR for programmed OSR. The ASIC shall return to programmed ODR after completing the triggered measurement. Sensors 9 Freescale Semiconductor 5 Register Description MAG3110 Table 9. Register Address Map Name Type RegisterAddress Auto-Increment Address (Fast Read)(1) 1. Fast Read mode for quickly reading the Most Significant Bytes (MSB) of the sampled data. Default Value Comment DR_STATUS(2) 2. Register contents are preserved when transitioning from “ACTIVE” to “STANDBY” mode. R 0x00 0x01 0000 0000 Data ready status per axis OUT_X_MSB(2) R 0x01 0x02 (0x03) data Bits [15:8] of X measurement OUT_X_LSB(2) R 0x02 0x03 data Bits [7:0] of X measurement OUT_Y_MSB(2) R 0x03 0x04 (0x05) data Bits [15:8] of Y measurement OUT_Y_LSB(2) R 0x04 0x05 data Bits [7:0] of Y measurement OUT_Z_MSB(2) R 0x05 0x06 (0x07) data Bits [15:8] of Z measurement OUT_Z_LSB(2) R 0x06 0x07 data Bits [7:0] of Z measurement WHO_AM_I(2) R 0x07 0x08 0x