RAM Memory

nullRAM MemoryRAM Memory ----Theory of Operation Iris Liu 1/19/2005nullDynamic RAM(DRAM) Memory Static RAM(SRAM) Memory Brief Introduction of DRAMBrief Introduction of DRAMLower cost, but much slower than SRAM The DRAM chip receives the address (the exact location the current bus master wants to communication with) in two steps The row address The column addressDRAM Addressing Sequence

DRAM Addressing Sequence

Row address must be routed to the memory address bus DRAM addressing logic asserts RAS#. Row address decoder begins to decode the latched row address, selecting one row line to be activated (the row latch) Logic delays a certain time (RAS/CAS delay) DRAM addressing logic routes the column address portion and asserts CAS# (the column latch) The point at which the row & the column lines intersect identifies the storage location Notice the state of DRAM’ｓread/write input pin (data bus stands by) Row and Column Address SourceRow and Column Address SourceFrom the DRAM addressing logic’ｓperspective, the address is treated as three packets of info. (for example output 24-bit) The upper-most bits (23:20) to DRAM addressing decoder (determine if the address is valid) The lower portion is divided into two packets of equal size The row address (19:10) The column address (9:0)DRAM Addressing Logic

DRAM Addressing Logic

The DRAM addressing decoder The time delay (triggered at specified intervals) The DRAM addressing multiplexer, or MUX (is nothing more than a switch) The RAS/CAS generation logic Detailed Description of DRAM Addressing Sequence

Detailed Description of DRAM Addressing Sequence

DRAM address decoder The row address Row address strobe RAS/CAS delay The column address Column address strobe Read or write The data transferHow Data is Stored in DRAMHow Data is Stored in DRAMAn electrical charge is placed on the capacitor to store a one, while the capacitor is discharge to store a zero in the location The discharge time is related partly to the size of the capacitor. The capacitors in DRAM cells are quite small, therefore, the capacitor will loses the bit stored in it much quickly.DRAM RefreshDRAM RefreshActivate a row line with the DRAM ’ｓread/write pin in the read state, every storage location along the row will be refreshed. Refresh Logic & RAS-only Refresh CAS-before-RAS Refresh Hidden Refresh Self-RefreshRefresh Logic & RAS-only RefreshRefresh Logic & RAS-only RefreshThe refresh logic consists of A refresh row counter The refresh timer, time #1 (REFRESH TRIGGER once every 15ms) The refresh logic must run in two steps: Become bus master & send a row address to the DRAM Run the refresh bus cycle (set the DRAM ’ｓread/write control line to the read state) Refresh Logic & RAS-only Refresh

Refresh Logic & RAS-only Refresh

Refresh timer sends REFRESH TRIGGER  refresh logic on the system board The refresh logic sends HOLDCPU, waiting CPUHLDA The refresh logic asserts MRDC# to indicate that a memory read bus cycle is in progress The refresh row counter outputs its current row number onto the lower address portion (internally incremented from 0 to 1) Currently row zero selects the A set of inputs onto its memory address bus. The addressing logic then asserts RAS# to latch the row addressRefresh Logic & RAS-only Refresh

Refresh Logic & RAS-only Refresh

The read/write pin on every DRAM chip will be set to the read state This set of actions causes the exact same row in every DRAM chip to be activated at the same time After refresh bus cycle, the refresh logic returns bus ownership to the CPU by deasserting HOLD CPU deasserts HLDA to indicate that it is bus again. Program execution resumes and continues until another 15ms has elapsed. Then the refresh timer asserts REFRESH TEIGGER again to request another refresh bus cycle The refresh logic again outputs the contents of the refresh row counter (incremented by one) onto the lower address portion Refresh Logic & RAS-only RefreshRefresh Logic & RAS-only RefreshWhen the last row within the DRAM chips has been refreshed, the row counter rolls over to all zeros again and process starts over at the first row in the DRAM chips The actions described earlier in step 5 are for what ’ｓcalled RAS-only refreshOther methods of RefreshOther methods of RefreshCAS-before-RAS Refresh A DRAM chip capable of CBR refresh has an internal refresh row counter, so it does not need to receive a row address from the refresh logic. (CAS# first, then RAS#) Hidden Refresh (a variation of CBR refresh) CAS# is left asserted when RAS# is deasserted at the end of the access. The DRAM is thus providing data and doing refresh simultaneously, thus the refresh appears to be hidden Other methods of RefreshOther methods of RefreshSelf-Refresh They own their internal refresh row counters and internal refresh timer, without waiting for a signal from the system board. (used in lieu of SRAM for low power) It initiates its refresh operation when it sees CAS# asserted followed by RAS#. It continues to refresh itself until it sees RAS# and CAS# deasserted.Destructive Read: Pre-Charge Delay & Cycle Time

Destructive Read: Pre-Charge Delay & Cycle Time

Pre-charge delay It takes an appreciable amount of time to recharge a DRAM location back to a good level again During the pre-charge period, the data received may very well be garbage The overall period of time consisting of the access time and the pre-charge delay is known as the cycle time DRAM BankDRAM BankTo create a usable design, a series of eight DRAM chips are combined so that they can store one byte of information per location The RAS# & CAS# lines are connected to all eight DRAM chips The read/write control line is connected as well The designer connects each individual data bus line to the data input/output pin on a separate DRAM chip within the bank of DRAM DRAM Bank WidthDRAM Bank WidthThe system has an 8-bit data bus: a bank of DRAM consists of 8 DRAM chips plus a parity bit The system has an 16-bit data bus: a bank of DRAM consists of 16 DRAM chips. All even-addressed locations are located in the lower half (connected to the lower data path D[7:0]). Each half consists of 8 data DRAM and a parity DRAM The system has an 32-bit data bus: each bank of DRAM consists of 32 data DRAM chips, plus four parity DRAMsDRAM Error Detection & Correction

DRAM Error Detection & Correction

Soft errors (caused by improper refresh) Crosstalk & noise on the data bus can cause data to become garbled between the DRAM chip and the bus master DRAM Parity (detects errors and cannot correct them) The parity generator/checker chip Parity is not checked for correctness during memory write operations, only during memory reads When the bus master writes a byte to the DRAM chips The parity generator ’ｓjob is to force the 9-bit pattern written into memory to always consist of an even number of one bits (if using “even parity”) On a read bus cycle If the parity check logic generates a parity error, which causes a NMI request to the CPUDRAM Error Detection & CorrectionDRAM Error Detection & CorrectionError-Checking-and-Correcting Memory (ECC) The ECC memory controller encodes the bytes (written data) before storing them There are more bits in the ECC (invalid bit patterns exit) than there are in the original data byte If the ECC controller subsequently reads one of these invalid patterns, it knows an error has occurred, then it can usually correct the error by finding the valid bit pattern that it “closest” to the invalid bit pattern Page-Mode DRAM and Its VariationsPage-Mode DRAM and Its VariationsPage Mode DRAM Enhanced Page Mode DRAM Burst and Nibble Mode DRAM Static Column RAM (SCRAM) Synchronous DRAMPage Mode DRAMPage Mode DRAMJust a variation on standard DRAM memory, sequentially along a row. Consider one row of RAM memory to be a page of DRAM memory location 0: row 0, column 0 location 1: row 0, column 1 … The first access to a page mode is identical to that for a standard DRAM. When RAS# is asserted in a page mode DRAM system, then The DRAM chips latch the row address The row address is latched into the row latch that is external to the DRAM chips Page Mode DRAM

Page Mode DRAM

External support logic consists of a row latch & a row comparator The row address currently held by the row latch ?= the address bus containing the row address for the next upcoming DRAM access Equal: page hit the DRAM addressing logic responds by keeping RAS# asserted at the end of the current bus cycle (no need to wait for RAS/CAS delay to elapse) Differ: page miss the page mode DRAM chips must forget the currently latched row address by deasserting RAS#. Then begin a new access as a standard DRAM access Enhanced Page Mode DRAMEnhanced Page Mode DRAM(Faster than standard page mode DRAM) Beginning the column address decode as soon as a new column address appears on the memory address bus, even before CAS# is asserted (the DRAM access time is improved)Burst and Nibble Mode DRAM

Burst and Nibble Mode DRAM

It is a optimum performance when the cache is reading/writing lines of info. from main RAM Burst and nibble mode DRAM have internal column counters, so they do not need to see new column addresses during the burst. CAS# is toggled cause the DRAM to increment its internal column counter and to access that column Notice that burst and nibble mode DRAM lack the ability to do random accesses along the current rowStatic Column RAM (SCRAM)

Static Column RAM (SCRAM)

SCRAM is structured with sequential memory locations distributed along a row Different from page mode: SCRAM does not need to have CAS# asserted each time a new column address is presented to it. If a memory subsystem is designed for page mode DRAM, it would also work with SCRAMSynchronous DRAMSynchronous DRAMIt is not a type of DRAM by itself To achieve optimum performance with the microprocessor, the DRAM must be synchronized to the microprocessor Synchronous DRAM interfaces are often used on burst mode DRAM Interleaved Memory Architecture

Interleaved Memory Architecture

One bank of DRAM memory is split up into two banks (Bank A & Bank B) The microprocessor is able to perform back-to-back read operations without waiting for the pre-charge delay. Waiting only when the next memory access is within the same bank as the precious access If page mode DRAM is used in the interleaved banks, then the pre-charge delay may be avoided even if the current bus master accesses the same bank consecutively.Static RAM (SRAM)Static RAM (SRAM)SRAM uses single-bit latches known as D flip-flops. So it does not require refreshing in order to maintain the info. stored in memory. SRAM receives the entire address at once, so its access is faster than DRAM. But SRAM is cost-prohibitive to populate an entire system with it. limited amounts of high-speed SRAM are used as cache memory to improve the system overall transfer rate when addressing memoryQuestion and AnswerQuestion and AnswerThank You