UC3875 组成的1000W移相全桥软开关

1 A PP LI C AT IO N N O TE APT9703 By: Ken Dierberger A New Generation of Power MOSFET Offers Inproved Performance at Reduced Cost 2 A New Generation Of Power MOSFETs Offers Improved Performance At Reduced Cost Ken Dierberger Application Engineering Manager Advanced Power Technology Inc. Bend, Oregon 97702 ABSTRACT In today’s power electronic market place, as in other areas of electronics, reducing cost is necessary to stay competitive. A new generation of high voltage Power MOSFETs offers lower on-resistance (RDS(ON)) using the same chip area as a previous generation of devices. Smaller die MOSFETs are also being produced with this technology that have the same RDS(ON) as a previous generation but now at a lower price. This paper covers the use of these devices in a phase shifted control mode full bridge DC/DC converter featuring zero voltage switching. A comparison was made between the performance of an older generation device to the new generation device. The comparison shows that the new smaller die device, while providing reduced cost, produced equal performance to the older generation. Introduction Advances in resonant and quasi-resonant power conversion technology offer alternative solutions to a conflicting set of square wave conversion design goals; obtaining high efficiency operation at a high switching frequency from a high voltage source. Presently, the conventional approaches are by far, still in the production mainstream. However, an increasing challenge can be witnessed by the emerging resonant and quasi-resonant technologies, primarily due to their lossless switching merits. The concept of quasi-resonant, “lossless” switching is not new, most noticeably patented by P. Vinciarelli [1]. Numerous efforts focusing on zero current switching ensued, first perceived as the likely candidate for tomorrow’s generation of high frequency power converters. In theory, the ON-OFF transitions occur at a time in the resonant cycle where the switch current is zero, facilitating zero current switching, hence zero power switching. While true, two obvious concerns can impede the quest for high efficiency operation with high voltage inputs. By nature of the resonant tank and zero current switching limitation, the peak switch current is significantly higher than its square wave counterpart. In fact, the peak of the full load switch current is a minimum of twice that of its square wave kin, significantly increasing conduction losses. In its OFF state, the switch returns to blocking a high voltage every cycle. When activated by the next drive pulse, the MOSFET output capacitance (Coss) is discharged by the FET, contributing a significant power loss at high frequencies and high voltages. Instead, both of these losses are avoided by implementing a zero voltage switching technique. APT9703 3 Zero Voltage Switching Conventional zero voltage switching can best be defined as square wave power conversion during the switch’s ON-time with “resonant” zero volt turn-ON switching transitions. For the most part, it can be considered as square wave power using either a constant OFF or ON time while varying the conversion frequency to maintain regulation of the output voltage Fixed frequency conversion using variable OFF and ON times can also be used to maintain regulation of the output voltage. The benefits of lossless Zero Voltage Transition (ZVT) switching techniques are well known through the power supply industry.[2] The parasitic circuit elements can be used advantageously to facilitate resonant transitions rather than snubbing dissipatively. The resonant tank functions to put zero voltage across the switching devices prior to turn-ON, eliminating power loss due to the simultaneous overlap of switch current and voltage at each transition. High frequency converters operating from high voltage input sources gain significant improvements in efficiency with this technique. The full bridge topology as shown in Figure 1 will be the specific focus of this paper, with emphasis placed on the fixed frequency, phase shifted mode of operation. Phase Shifted Control The phase shifted mode H-bridge functions by applying two square waves to the primary of a transformer. For an output duty cycle of D=1 the two square waves would be 180 degrees out of phase as shown in Figure 2. For an output duty cycle of D<1 one of the square waves would be phase shifted resulting in the primary of the transformer being short circuited during a portion of the period, Figure 3. +VIN -VIN QA QC QDQB T1 LO CO D1 D2 VO A phase shifted mode power supply can be implemented using a conventional H- Bridge circuit, Figure 1. The switch drive signals are fixed frequency square waves with QA and QB switched 180 degrees out of phase and QC and QD switched 180 degrees out of phase. Using the switch drive signal of QA and QB as a reference, the switch drive signal of QC and QD will be phase shifted to create the duty cycle needed to produce the correct DC output. Figure 2. Phase Shifted Mode for D=1. Figure 3. Phase Shifted Mode for D<1. Figure 1. Full Bridge Topology. APT9703 4 The gate drive signals for switch operation is shown in Figure 4. Interval 1, QA and QD are ON and QB and QC are OFF resulting in a positive voltage output from the transformer and transferring power to the inductor and the load. During interval 2, QC is switched ON and QD is switched OFF resulting in QA and QC shorting the primary of the transformer producing no output voltage and no power is delivered to the inductor from the power source. The inductor will free wheel during interval 2 and along with CO will continue to deliver stored energy to the load. During interval 3, QA and QB are switched OFF and ON respectively resulting in a negative voltage being applied to the transformer. Again the power source will deliver power to the inductor and the load. The final interval 4, QC and QD are switched OFF and ON respectively resulting in a short across the transformer and no output voltage is produced. Again no power is delivered to the output and the inductor, along with CO will continue to deliver stored energy to the load. The next interval QA QB QC QD 1 2 3 4 5INTERVAL GATE DRIVE OUTPUT T1 Figure 4. Gate Drive and T1 Output Signals. 5, QA returns to ON and QB is returned to OFF. With QB and QC OFF and QA and QD ON this is the same conditions that existed in interval 1 and one cycle has been completed. It is noteworthy to point out that this circuit is hard switched and considerable power will be lost as a result of switching losses. The circuit, as described, will suffer from shoot- through current and resulting losses as QA- QB or QC-QD will most likely conduct current simultaneously during the transition between intervals. One method commonly used to prevent shoot-through current power losses is to delay the turn-ON of one switch until the other switch in the leg has completely turned OFF. If we examine the use of this technique during the transition from interval 1 to 2 we note something interesting. Zero Voltage Switched Phase Shifted Control Figure 5 shows a MOSFET H-Bridge with output capacitances and intrinsic diodes included. Also shown as a separate component is the transformer leakage inductance LR. Examining the switching transition between intervals 1 and 2 in more detail, with a short delay added between the turn-OFF of QD and the turn-ON of QC, reveals it more than just limits the shoot-through current. When QD is turning OFF the voltage at the drain of QD will only rise as fast as the primary current of T1 can charge the capacitance CD, and discharge the capacitance CC. If the turn- OFF speed of QD is much faster than the charge/discharge time of CD/CC the drain voltage of QD will remain low during turn-OFF and this will minimize the turn-OFF losses of QD. The drain voltage will continue to rise, but will not dissipate any power as energy is being stored in CD and the energy stored in APT9703 5 CC is returned to the input supply +VIN, until it reaches a voltage slightly above the positive supply voltage (+VIN). At this point the intrinsic diode DC will begin to conduct clamping the drain voltage to VIN. After DC is conducting the voltage across the drain-source of QC is essentially zero and QC can be turned ON with a Zero Voltage Transition (ZVT) resulting in lossless switching. A MOSFET channel can conduct current in both forward and reverse directions and turning the MOSFET ON while the body diode is conducting will result in reducing the conduction losses of the diode. The current driving the transition of the right leg can be approximated as the reflected load current in the primary of transformer T1 (IP). During the right leg transition the current IP will remain relatively constant as current will continue to flow through the output diode (D1) into the output inductor (LO). The resulting right leg transition time is a linear ramp calculated from equation (1) : PI = RC dv dt or dt = RC dv PI (1) where: IP is the primary current of T1 at the end of interval 1 dv=VIN dt is the transition time CR is the effective value of CC+CD which is: RC = 4 3 CC + DC( ) (2) The 4/3 factor is used to estimate the average output capacitance over the drain voltage range. At the end of the right leg transition the primary voltage of T1 will be zero as both QA and QC are conducting, resulting in a short circuit of the primary. With the primary of T1 at zero volts the secondary will also be at zero volts, stopping transfer of power to the output. The presence of LR in the primary circuit of T1 will steer the output current to continue to flow in D1 during the clamped freewheeling interval. Note that the current in the secondary windings never splits in half during the OFF period of power transfer as it does in a conventional, non-phase shifted H-bridge. During interval 2 the current in LR will remain nearly constant as the current in LO is still being reflected to the primary. At the end of interval 2, QA will turn-OFF and QB will turn-ON, with a short delay added between the events. When QA is turning OFF the voltage at the source of QA will only drop as fast as the current supplied by LR can charge CA and discharge CB. If the turn-OFF +VIN -VIN QA QC QDQB T1 LR LO CO D1 D2 VO DA DC DDDB CA CB CD CC Figure 5. H-Bridge With Parasitic Diodes and Capacitances Shown. APT9703 6 speed of QA is much faster than the charge/ discharge time of CA/CB the drain-source voltage of QA will remain low during turn-OFF and this will minimize the turn-OFF losses of QA. The source voltage will continue to drop until it reaches a voltage slightly below the supply voltage return (-VIN). This transition will not result in any power dissipation as energy is being stored in CA and the energy stored in CB is returned to the input supply +VIN. At this point the intrinsic diode DB will begin to conduct clamping the drain voltage to -VIN. After DB is conducting the voltage across the drain-source of QB is essentially zero and QB can be turned ON with a Zero Voltage Transition (ZVT) resulting in lossless switching. Note that the left leg transition is resonant and not linear like the right leg transition. As soon as the left leg transition begins the reflected output inductor disappears from the primary circuit. Reverse voltage being impressed on the primary of T1 will begin the output diode commutation from D1 to D2 resulting in a short circuit of the secondary winding during the left leg transition thus removing the reflection of LO from the primary circuit. The left leg resonant transition must be fueled by energy stored in LR. The exact circuit to describe this transition is a series L/ C circuit with an initial current flowing equal to IP at the start of the transition. LR is the total series primary inductance and CR is the effective circuit capacitance, 4/3(CA+CB). If the leakage inductance, LR, of T1 is too low and has insufficient energy to complete the resonant left leg transition a small inductor will need to be added in series with the primary of T1. The primary current during this transition has a sinusoidal shape with the peak amplitude occurring at the beginning of the transition. Because of this, solving for the exact transition time will require taking the arcsin of the function describing the transition parameters at the beginning of the transition. TRAN(LEFT)t = 1 Rω arcsin INV RZ PI (3) Where ZR is the resonant tank circuit impedance and ωR is the resonant tank self oscillating frequency in radians: RZ = RL RC (4) Rω = 1 RL RC (5) At the end of the left leg transition T1 will have VIN impressed across the primary as both QB and QC are conducting. With the primary of T1 at VIN the secondary will be at VIN multiplied by the turns ratio of T1, resuming transfer of power to the output. At the end of interval 3 an identical analysis can be done to facilitate the transition from the conduction of QB and QC back to the conduction of QA and QD. The only difference is QC will be exchanged with QD and QB will be exchanged with QA in the discussion. The right leg will transition first in a linear mode as before and the left leg will transition second in a resonant mode as before. The shorted primary function will be done by the lower switches QB and QD. A more detailed discussion of the preceding can be found in reference [2]. Evaluation Power Supply To demonstrate the Phase Shifted ZVT Controlled Power Conversion technique we obtained an evaluation board from Unitrode Corp. which uses their UC3875 PWM controller IC. The evaluation board was APT9703 7 designed for 250 watts +12 to +32 volts output. Advanced Power Technology (APT) made some modifications to the evaluation power supply to convert it to 1000 watts at 48 volts output. Specifications for the power supply are: VIN 400VDC VOUT 48VDC IOUT 20.5ADC POUT 1000W Efficiency >93% 400VDC input voltage was chosen because this allows the power supply to be operated from a Power Factor Corrected (PFC) universal input (85 to 265VAC) preregulator. The 48VDC output voltage was chosen to match the requirements of the telecom industry. Design Overview The circuit used for the evaluation power supply is shown in Figure 6 with the parts list shown in Appendix 1. This design conforms in principle with the Unitrode application notes References [2, 3, 4]. Details of the differences between this design and the aforementioned application notes can be found in reference [5]. In summary the main differences in the evaluation power supply are: 1. The control circuitry is ground referenced to the output DC ground not the input DC ground. This improves the regulation of the output voltage and allows easier implementation of over current protection. 2. Coupling capacitors C1 and C2 are inserted in series with the driver transformers primary to improve the symmetry of the v-t product for the transformer cores and protects against saturation. A coupling capacitor C3 has been added in series with the power transformer T4 and has the same function as C1 and C2. 3. The v-t product can be asymmetrical if there are differences in coupling of both secondary halves to the primary, differences in the forward voltage between the rectifier diodes or by modulation of the error amplifiers output by clock- synchronous distortion. The disadvantages of this method are: The gate drive transformers may require additional insulation to meet safety standards. An isolated auxiliary power supply must be provided to power the UC3875. This is easily implemented if a PFC Preregulator is used to drive the converter. Three major modifications made by APT to increase the evaluation power supply design to 1000W were: The main power transformer was changed back to a planar transformer similar to the design in reference [3]. APT30D20K diodes were used for the output rectifiers to accommodate the increased output current requirements. APT5020BNFR, APT5020BVFR and APT5017BVFR FREDFETs were all evaluated in the circuit. The APT5020BNFR, APT5020BVFR were found to provide equal performance. The APT5017BVFR showed a few tenths of a percent better efficiency. All devices offer low RDS(ON) to minimize conduction losses which are the dominant losses of the switching transistors. The APT5020BVFR is the better choice due to its lower price. The FREDFET was selected to provide better safety margin for commutative dv/dt of the body diode during no-load and short circuit operation of the power supply.[6] Several minor modifications were needed to adjust the operation of the controller to accommodate the higher power and output voltage. The clock frequency was increased to 300KHz to provide a conversion frequency of 150KHz. The ramp and slope were adjusted for the new frequency. The current sense resistor was changed to 5 milliohms. The voltage divider for the error amplifier was adjusted for the 48V output voltage. APT9703 8 The power supply board layout is shown actual size in Figure 7. Note the small heat sinks required to cool the power MOSFETs. In fact the power dissipation of each FET is estimated to be under 2W at full load. A small fan was required to cool the power supply as the resonant inductor L1 was operating hot. Additional refinement of this component appears to be required. All other components were cool to the touch after several minutes of run time. The overheating of L1 prevented long run time testing. Once L1 is optimized it is believed that the better performance of the APT5017BVFR will be more significant and will make this device the better choice for the power supply. The parts list is given Appendix 1. +VIN -VIN -VAUX +VAUX R1 10 R4 10 R9 30 R16 15.8K R18 220K R21 4.7K T1 R2 2.7K R5 2.7K R10 270 R11 70.5K R12 4.7K R24 1KR25 1K R23 33K R28 33K R22 470K R13 0.005 R3 2.7K R6 2.7K L2 L3 L1 R 14 1 5. 8K R 15 4 .7 K R 17 4 70 R 19 1 1K R 20 7 .5 K R 26 1 K R 27 1 K L4 39µH C28 2.2µF C1 .22µF C2 .22µF C3 .68µF C7 470pF C25 47nF C27 33nF C9 1000µF C10 1000µF C11 1.0µF C5 1500pF C6 1500pF C13 1000µF C12 1µF C14 0.1µF C21 47pF C20 47nF C15 1.0nF C 16 0 .1 µF C1 7 0. 1µ F C1 8 22 0p F C1 9 27 0p F C2 2 4 7n F C2 3 47 nF C2 4 47 nF 11 16 17 1 6 5 2 3 15 7 418 19 20 1289131410 FR EQ . S ET SY NC VR EF SL O PE SS RA M P CS + E/ A O UT E/ A- D EL A/ B D EL C/ D E/ A+ S G ND PW R G ND O UT D O UT C O UT B O UT AVC VI N IC1 UC3875 IC2 UC3610 D3,4,5,6 1N4148 D7 APT30D20B D8 APT30D20B D9 1N4148 T3 T4 T2Q1 APT5020BVFR Q3 APT5020BVFR Q2 APT5020BVFR Q4 APT5020BVFR 5 4 6 8 7 IC3 1/2 LM258 + - 6 2 1 8 C4 0.1µF C8 4.7µ Figure 6. Schematic of the Evaluation Power Supply. Performance The evaluation power supply was tested over a load range of 100W to 1000W. The unit maintained ZVT to a load of under 50% and achieved an efficiency of over 93% from a load range of 750W to 1000W. Load regulation was ±0.18% from 100W to over 900W and was ±0.56% from 100W to 1000W. The loss of regulation above 900W was due to the required duty cycle reaching very near 100%. This could be corrected by an adjustment in the transformer turns ratio. A graph of the measured converter efficiency is shown in Figure 8 for loads above 100W. Efficiency remains above 91% above 450W. The efficiency drops under 91% with APT9703 9 Figure 7. Power Supply Board Layout. C13 L4 C12 IC1 C1 4 R2 0 C2 3 C1 7 C1 8 C2 4 C2 0 C2 1 R1 8 R 27 R21 R25 R11 C11 R13 R26 R17 R9 C25 R23 C10 C9 IC2 C1 R4 C2 D6 D4 D5 D3 T1 T2 T3 T4 C6 C5 L1 C8 D8 D7 Q2 Q1 Q3 Q4 -VAUX +VAUX -VIN +VIN C28 C3 C7 R 19 C2 2 C1 5 R 14 R 15 C1 8