how use ddr2

USER’S MANUAL HOW TO USE DDR2 SDRAM Document No. E0437E30 (Ver.3.0) Date Published April 2007 (K) Japan URL: http://www.elpida.com © Elpida Memory, Inc. 2004-2007 User’s Manual E0437E30 (Ver.3.0) 3 INTRODUCTION Readers This manual is intended for users who design application systems using double data rate 2 synchronous DRAM (DDR2 SDRAM). Readers of this manual are required to have general knowledge in the fields of electrical engineering, logic circuits, as well as detailed knowledge of the functions and usage of conventional synchronous DRAM (SDRAM) and double data rate synchronous DRAM (DDR SDRAM). Purpose This manual is intended to give users understanding of basic functions and usage of DDR2 SDRAM. For details about the functions of individual products, refer to the corresponding data sheet. Since operation examples that appear in this manual are strictly illustrative, numerical values that appear are not guaranteed values. Use them only for reference. Legend Caution: Information requiring particular attention Note: Footnote for items marked with Note in the text Remark: Supplementary information Related Documents Related documents indicated in this manual may include preliminary versions, but they may not be explicitly marked as preliminary. Document Name Document No. HOW TO USE SDRAM USER’S MANUAL E0123N HOW TO USE DDR SDRAM USER’S MANUAL E0234E User’s Manual E0437E30 (Ver.3.0) 4 CONTENTS CHAPTER 1 ODT (ON DIE TERMINATION)..............................................................................................................................6 1.1 Signal Reflection .......................................................................................................................................................................6 1.2 Motherboard Termination..........................................................................................................................................................7 1.2.1 Signal reflection when using motherboard termination ..........................................................................................................7 1.3 Overview of ODT ......................................................................................................................................................................8 1.3.1 ODT features ..........................................................................................................................................................................8 1.3.2 Advantages of ODT ................................................................................................................................................................8 1.3.3 Structure of ODT ....................................................................................................................................................................9 1.4 Setting of ODT Impedance Value..............................................................................................................................................9 1.5 ODT's ON/OFF timing ............................................................................................................................................................10 1.5.1 ODT's ON/OFF timing for power-down mode .....................................................................................................................10 1.5.2 ODT's ON/OFF timing for active mode and standby mode..................................................................................................11 1.5.3 ODT's ON timing at entering power-down mode .................................................................................................................12 1.5.4 ODT's OFF timing at entering power-down mode................................................................................................................13 1.5.5 ODT's ON timing at exiting power-down mode ...................................................................................................................14 1.5.6 ODT's OFF timing at exiting power-down mode..................................................................................................................15 1.6 ODT in Self-refresh Mode .......................................................................................................................................................15 CHAPTER 2 OCD (OFF CHIP DRIVER) ....................................................................................................................................16 2.1 Overview of OCD....................................................................................................................................................................16 2.1.1 Drive performance and transition time..................................................................................................................................16 2.1.2 DQS signal, /DQS signal, and drive performance.................................................................................................................17 2.1.3 DQS signal, /DQS signal, and valid data window.................................................................................................................18 2.1.4 Extension of valid data window by voltage adjustment ........................................................................................................19 2.2 Setting of OCD Impedance Value............................................................................................................................................20 2.2.1 OCD impedance adjustment method ....................................................................................................................................20 2.2.2 OCD impedance adjustment steps ........................................................................................................................................20 2.3 Setting of OCD Value..............................................................................................................................................................22 2.3.1 Drive (1) mode......................................................................................................................................................................23 2.3.2 Drive (0) mode......................................................................................................................................................................24 2.3.3 Adjustment mode..................................................................................................................................................................25 2.3.4 OCD calibration mode exit ...................................................................................................................................................26 2.3.5 OCD calibration default ........................................................................................................................................................26 2.3.6 Example of impedance value test circuit...............................................................................................................................26 User’s Manual E0437E30 (Ver.3.0) 5 CHAPTER 3 4-BIT PREFETCH...................................................................................................................................................27 3.1 Semiconductor Processes and Acceleration Limits..................................................................................................................27 3.2 Prefetch Operation ...................................................................................................................................................................27 3.2.1 Operations of DDR2 SDRAM, DDR SDRAM, and SDR SDRAM .....................................................................................27 3.3 Operating Speeds of DDR2 SDRAM, DDR SDRAM, and SDR SDRAM..............................................................................29 CHAPTER 4 POSTED CAS AND ADDITIVE LATENCY.........................................................................................................30 4.1 Overview of Posted CAS.........................................................................................................................................................30 4.1.1 Problems with DDR SDRAM...............................................................................................................................................30 4.1.2 Improvements in DDR2 SDRAM.........................................................................................................................................31 4.2 Read Operation ........................................................................................................................................................................32 4.2.1 Read operation in DDR SDRAM..........................................................................................................................................32 4.2.2 Read operation in DDR2 SDRAM........................................................................................................................................32 4.3 Write Operation .......................................................................................................................................................................33 4.3.1 Write operation in DDR SDRAM.........................................................................................................................................33 4.3.2 Write operation in DDR2 SDRAM.......................................................................................................................................33 4.4 Setting of Additive Latency .....................................................................................................................................................34 4.5 Read Latency and Write Latency.............................................................................................................................................35 4.5.1 Read latency..........................................................................................................................................................................35 4.5.2 Write latency.........................................................................................................................................................................36 CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 6 CHAPTER 1 ODT (ON DIE TERMINATION) This chapter describes ODT (On Die Termination). ODT is a new function that has been added to DDR2 SDRAM. It reduces signal reflection by including a termination resistance in the DRAM. The DRAM controller can use ODT to set the termination resistance ON and OFF simultaneously for each data I/O pin signal (DQ) as well as differential data strobe signals (DQS, /DQS, RDQS and /RDQS) and write data mask signal (DM). By reducing signal reflection (a source of noise), this function makes for higher signal quality and thus helps enable faster data transfers. This function also simplifies system design since it eliminates the need for layout and wiring of termination resistors. It also means there are fewer components to mount on the motherboard, which lowers part-related costs. 1.1 Signal Reflection A ball that is thrown against a wall will bounce back. Similarly, electrical signals are reflected back when they reach the end of a transmission path. Electrical signals also can be reflected at points where impedance differs, such as at bus and DRAM connection points. Signal reflection causes noise, which lowers signal quality. In a high-speed data transfer system, high-quality signals are required and even a slight amount of noise can be a major problem. CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 7 1.2 Motherboard Termination Motherboard termination is a termination method that reduces signal reflection by attaching a resistor (termination resistance) with a suitable resistance value at the end of each transmission path. However, this method does not reduce signal reflection adequately in the operating frequency range used by DDR2 SDRAM. Also, adding termination resistors to the motherboard increases the component count and tends to raise costs. 1.2.1 Signal reflection when using motherboard termination As mentioned above, motherboard termination may not be able to reduce signal reflection adequately. If there are several DRAMs on the same bus, such as is shown in Figure 1-1, DRAM currently being accessed is affected by reflected signals from other DRAM. Thus, to ensure high signal quality required in a high-speed data transfer system, a processing technology is needed to control signal reflection with greater precision than is possible with motherboard termination. Write in progress Waiting for access Write in progress Waiting for access Write in progress Waiting for access DRAM1 DRAM2 VTT Motherboard termination Motherboard termination Motherboard termination Controller Signal Signal Signal Signal DQ bus DRAM1 DRAM2 VTT Controller Reflected DQ bus DRAM1 DRAM2 VTT Controller Reflected Reflected DQ bus STEP 1 STEP 2 STEP 3 Reflected signals are in both direction; to the end of the bus and to DRAM1. Reflected signal to the end of the bus is absorbed by a termination resistor. Reflected signal from DRAM2　 causes noise that is added to the　 signal from the memory controller, lowering the signal integrity. DRAM1 receives signal from the memory controller and reflected signal from DRAM2 DRAM2 reflects signals. Memory controller's signals are propagated on signal line. Figure 1-1 Signal Reflection when Using Motherboard Termination CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 8 1.3 Overview of ODT When using ODT, the on-die termination resistance for each DRAM can be switched ON and OFF. Accordingly, even when several DRAMs exist on the same bus, signals transmitted to the DRAM can be terminated. As a result, DRAM currently being accessed is less likely to be affected by reflected signals from other DRAM. DRAM1 DRAM2 Controller Signal Signal DQ bus DRAM1 DRAM2 Controller ON VTT ON VTT Reflected Write in progress Waiting for access Write in progress Waiting for access STEP 1 STEP 2 Internal termination resistance of DRAM2 suppresses signal reflection. DRAM1 is less likely to be affected by reflected signals from DRAM2 and therefore signal integrity is preserved. Memory controller's signals are propagated on signal line. Figure 1-2 ODT and Reflected Signals 1.3.1 ODT features DDR2 SDRAM embeds the termination resistors that used to be placed on the motherboard. The DRAM controller can use ODT to set the termination resistance simultaneously to each pin (DQ, DQS, /DQS, RDQS, and /RDQS) ON and OFF. The impedance value of the termination resistors can be selected as "ODT not selected", "ODT selected (50Ω)", "ODT selected (75Ω)", or "ODT selected (150Ω)". The value to be selected is set in advance via EMRS (1), (Extended Mode Registers Set (1)). 1.3.2 Advantages of ODT DDR2 SDRAM contains termination resistors that were previously mounted on the motherboard, thereby reducing the number of parts on the motherboard. This also eliminates some of the wiring on the motherboard, which facilitates system design. CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 9 1.3.3 Structure of ODT DDR2 SDRAM can use the ODT control pin to set the termination resistance simultaneously to each pin (DQ, DQS, /DQS, RDQS, and /RDQS) ON and OFF. The termination resistor's impedance value is set in advance via EMRS (1) (Extended Mode Registers Set (1)). 1/2 VDDQ ODT control pin DRAM input buffer Input pins DQ, DQS, /DQS, RDQS, /RDQS DRAM Either "ODT not selected ( Ω)" or "ODT selected (50Ω, 75Ω, 150Ω)" can be selected via a setting in the EMRS (1). Figure 1-3 Structure of ODT 1.4 Setting of ODT Impedance Value The ODT impedance value is set via EMRS (1) (Extended Mode Registers Set (1)). Use two bits (A6 and A2) to select "ODT not selected", "ODT selected (50Ω)", "ODT selected (75Ω)", or "ODT selected (150Ω)". Once the ODT impedance value is set, the setting is retained until another setting is entered or the power is turned off. A13BA0BA1BA2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address 100 0 /DQS OCD program Rtt Additive latency Rtt D.I.C DLL Extended Mode Registers Set (1) A6 0 0 1 1 A2 0 1 0 1 Rtt (nominal value) ODT not selected 75Ω 150Ω 50Ω RDQSQoff ODT impedance value Figure 1-4 ODT Impedance Value Settings via Extended Mode Registers Set (1) CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 10 1.5 ODT ON/OFF Timing The ODT settings are controlled based on the input level of the ODT control pin. The standard value of ODT timing varies between power-down mode and other modes (such as active mode or standby mode). 1.5.1 ODT ON/OFF timing for power-down mode Figure 1-5 shows the ODT ON/OFF timing for power-down mode. When ODT is set to ON (ODT control pin input is at high level) during power-down mode, the ODT turn-on delay time (tAONPD) elapses, then the internal termination resistor (Rtt) is set to ON. When ODT is set to OFF (ODT control pin input is at low level) during power-down mode, the ODT turn-off delay time (tAOFPD) elapses, then the internal termination resistor (Rtt) is set to OFF. CK /CK T0 T1 T2 T3 T4 T5 T6 ODT CKE Internal Term Res. Rtt tIS tIS tAONPD max. tAOFPD min. tAOFPD max. tAXPD ≤ 6tCK tAONPD min. Figure 1-5 ODT ON/OFF Timing for Power-down Mode CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 11 1.5.2 ODT ON/OFF timing for active mode and standby mode Figure 1-6 shows the ODT ON/OFF timing for active mode and standby mode. When ODT is set to ON (ODT control pin input is at high level) during either standby mode or active mode, the ODT turn-on delay time (tAOND) elapses, then the internal termination resistor (Rtt) is set to ON. When ODT is set to OFF (ODT control pin input is at low level) during either standby mode or active mode, the ODT turn-off delay time (tAOFD) elapses, then the internal termination resistor (Rtt) is set to OFF. CK /CK T0 T1 T2 T3 T4 T5 T6 ODT CKE Internal Term Res. Rtt tIS tIS tAOND tAOFD tAON max. tAON min. tAOF min. tAOF max. tAXPD ≤ 6tCK Figure 1-6 ODT ON/OFF Timing for Active Mode and Standby Mode CHAPTER 1 ODT (ON DIE TERMINATION) User’s Manual E0437E30 (Ver.3.0) 12 1.5.3 ODT ON timing at entering power-down mode Figure 1-7 shows the timing when ODT is set to ON while entering power-down mode. The turn-on delay time must elapse before ODT is turned ON. The timing differs depending on whether or not this delay time has elapsed when power-down mode is entered. If the delay time has not elapsed when power-down mode is entered, the ODT turn-on delay time will be longer than normal. When power-down mode is entered after the ODT turn-on delay time has elapsed, DRAM is set to active mode or standby mode at the same time as power-down mode is entered. If power-down mode is entered before ODT turn-on delay time has elapsed, t