HA-5101斜杠883

1 ® HA-5101/883 N C V- N C B A L N C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 1994, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Low Noise, High Performance Operational Amplifier The HA-5101/883 is a dielectrically isolated operational amplifier featuring low noise and high performance. This amplifier has an excellent noise voltage density of 4.5nV/√Hz (max) at 1kHz. The unity gain stable HA-5101/883 yields a 10MHz unity gain bandwidth and a 6V/µs slew rate. DC characteristics of the HA-5101/883 assure accurate performance. The 3mV (max) offset voltage is externally adjustable and offset voltage drift is just 3µV/°C. Low bias currents (200nA max) reduce input current errors and the high open loop voltage gain of 100kV/V, over temperature, increases the loop gain for low distortion amplification. The HA-5101/883 is ideal for audio applications, especially low-level signal amplifiers such as microphone, tape head and preamplifiers. Additionally, it is well suited for low distortion oscillators, low noise function generators and high Q filters. Features • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Low Noise Voltage @ 1kHz . . . . . . . . . . . 4.5nV/√Hz Max • Low Noise Current @ 1kHz . . . . . . . . . . . . . 3pA/√Hz Max • Wide Unity Gain Bandwidth . . . . . . . . . . . . . . . 10MHz Min • High Gain (Full Temp) . . . . . . . . . . . . . . . . . .100kV/V Min (Room Temp) . . . . . . . . . . . . . . . . . 1MV/V Typ • Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V/µs Min • High CMRR/PSRR (Full Temp) . . . . . . . . . . . . . 80dB Min • High Output Drive Capability (Full Temp) . . . . . . . . . 25mA Applications • High Quality Audio Preamplifiers • High Q Active Filters • Low Noise Function Generators • Low Distortion Oscillators • Low Noise Comparators Pinouts Ordering Information PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # HA7-5101/883 -55 to 125 8 Ld CerDIP F8.3A 5962-89636012A -55 to 125 20 Ld Ceramic LCC J20.A HA7-5101/883 (CERDIP) TOP VIEW 5962-896360 (CLCC) TOP VIEW BAL -IN +IN V- 2 3 4 1 V+ OUT 7 6 5 8 NC BAL + - NC -IN NC +IN NC N C B A L N C N C N C NC V+ NC OUT NC 4 5 6 7 8 10 11 12 139 3 2 1 20 19 16 17 18 15 14 - + Data Sheet August 17, 2005 FN3931.1 HA-5101/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . V+ to V- Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25mA Output Short Circuit Duration. . . . . . . . . . . . . . . . . . . . . . . Indefinite Junction Temperature (TJ). . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .<2000V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . .+300°C Operating Conditions Operating Temperature Range . . . . . . . . . . . . . . . -55°C to +125°C Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . ±5V to ±15V VINcm ≤ 1/2 (V+ - V-) RL ≥ 500Ω Thermal Resistance θJA (°C/W) θJC (°C/W) Ceramic DIP Package . . . . . . . . . . . . . 120 30 Ceramic LCC Package. . . . . . . . . . . . . 86 26 Package Power Dissipation Limit at +75°C for TJ ≤ +175°C Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.22W Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.35W Package Power Dissipation Derating Factor Above +75°C Ceramic DIP Package . . . . . . . . . . . . . . . . . . . . . . . . .12.2mW/°C Ceramic LCC Package. . . . . . . . . . . . . . . . . . . . . . . . .13.5mW/°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VS= ±15V, RS = 100Ω, RL = 500kΩ, VOUT = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP (°C) LIMITS UNITSMIN MAX Input Offset Voltage VIO VCM = 0V 1 +25 -3 3 mV 2, 3 +125, -55 -4 4 mV Input Bias Current +IB VCM = 0V +RS = 100kΩ -RS = 100Ω 1 +25 -200 200 nA 2, 3 +125, -55 -325 325 nA -IB VCM = 0V +RS = 100Ω -RS = 100kΩ 1 +25 -200 200 nA 2, 3 +125, -55 -325 325 nA Input Offset Current IIO VCM = 0V +RS = 100kΩ -RS = 100kΩ 1 +25 -75 75 nA 2, 3 +125, -55 -125 125 nA Common Mode Range +CMR V+ = 3V V- = -27V 1 +25 12 - V 2, 3 +125, -55 12 - V -CMR V+ = 27V V- = -3V 1 +25 - -12 V 2, 3 +125, -55 - -12 V Large Signal Voltage Gain +AVOL VOUT = 0V and +10V RL = 2kΩ 4 +25 100 - kV/V 5, 6 +125, -55 100 - kV/V -AVOL VOUT = 0V and −10V RL = 2kΩ 4 +25 100 - kV/V 5, 6 +125, -55 100 - kV/V Common Mode Rejection Ratio +CMRR ∆VCM = +10V V+ =+5V V- = -25V VOUT = -10V 1 +25 80 - dB 2, 3 +125, -55 80 - dB -CMRR ∆VCM = -10V V+ = +25V V- = -5V VOUT = +10V 1 +25 80 - dB 2, 3 +125, -55 80 - dB 2 FN3931.1 August 17, 2005 HA-5101/883 Output Voltage Swing +VOUT1 RL = 2kΩ 1 +25 12 - V 2, 3 +125, -55 12 - V -VOUT1 RL = 2kΩ 1 +25 - -12 V 2, 3 +125, -55 - -12 V +VOUT2 VS = ±18V RL = 600Ω 1 +25 15 - V 2, 3 +125, -55 15 - V -VOUT2 VS = ±18V RL = 600Ω 1 +25 - -15 V 2, 3 +125, -55 - -15 V Output Current +IOUT VOUT = -15V VS = ±18V 1 +25 25 - mA 2, 3 +125, -55 25 - mA -IOUT VOUT = +15V VS = ±18V 1 +25 - -25 mA 2, 3 +125, -55 - -25 mA Quiescent Power Supply Current +ICC VOUT = 0V IOUT = 0mA 1 +25 - 6 mA 2, 3 +125, -55 - 6 mA -ICC VOUT = 0V IOUT = 0mA 1 +25 -6 - mA 2, 3 +125, -55 -6 - mA Power Supply Rejection Ratio +PSRR ∆VS = 10V V+ = +10V, V- = -15V V+ = +20V, V- = -15V 1 +25 80 - dB 2, 3 +125, -55 80 - dB -PSRR ∆VS = 10V V+ = +15V, V- = -10V V+ = +15V, V- = -20V 1 +25 80 - dB 2, 3 +125, -55 80 - dB Offset Voltage Adjustment +VIOAdj Note 4 RL = 2kΩ, CL = 50pF AV = +1V/V 1 +25 VIO-1 - mV 2, 3 +125, -55 VIO-1 - mV -VIOAdj 1 +25 VIO+1 - mV 2, 3 +125, -55 VIO+1 - mV TABLE 1. D.C. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VS= ±15V, RS = 100Ω, RL = 500kΩ, VOUT = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP (°C) LIMITS UNITSMIN MAX TABLE 2. A.C. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VS= ±15V, RS = 50Ω, RL = 2kΩ, CL = 50pF, AVCL = +1V/V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP (°C) LIMITS UNITSMIN MAX Slew Rate +SR VOUT = -3V to +3V 4 +25 6 - V/µs -SR VOUT = +3V to -3V 4 +25 6 - V/µs Rise and Fall Time tR VOUT = 0V to +200mV 10% ≤ tR ≤ 90% 4 +25 - 200 ns 5, 6 +125, -55 - 400 ns tF VOUT = 0V to -200mV 10% ≤ tF ≤ 90% 4 +25 - 200 ns 5, 6 +125, -55 - 400 ns Overshoot +OS VOUT = 0V to +200mV 4 +25 - 35 % 5, 6 +125, -55 - 35 % -OS VOUT = 0V to -200mV 4 +25 - 35 % 5, 6 +125, -55 - 35 % 3 FN3931.1 August 17, 2005 HA-5101/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VS= ±15V, RL = 2kΩ, CL = 50pF, AV = +1, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS NOTES TEMP (°C) LIMITS UNITSMIN MAX Differential Input Resistance RIN VCM = 0V 1 +25 250 - kΩ Low Frequency Peak-to-Peak Noise EnP-P 0.1Hz to 10Hz 1 +25 - 0.2 µVP-P Input Noise Voltage Density En RS = 20Ω, fo = 1000Hz 1 +25 - 4.5 nV/√Hz Input Noise Current Density In RS = 2MΩ, fo = 1000Hz 1 +25 - 3 pA/√Hz Unity Gain Bandwidth UGBW VO = 100mV 1 +25 10 - MHz Full Power Bandwidth FPBW VPEAK = 10V 1, 2 +25 95 - kHz Minimum Closed Loop Stable Gain CLSG 1 -55 to +125 +1 - V/V Output Resistance ROUT Open Loop 1 +25 - 150 Ω Quiescent Power Consumption PC VOUT = 0V, IOUT = 0mA 1, 3 -55 to +125 - 180 mW NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK). 3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.) 4. Offset adjustment range is [VIO (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 & 2) Interim Electrical Parameters (Pre Burn-in) 1 Final Electrical Test Parameters 1*, 2, 3, 4, 5, 6 Group A Test Requirements 1, 2, 3, 4, 5, 6 Groups C & D Endpoints 1 *PDA applies to Subgroup 1 only. 4 FN3931.1 August 17, 2005 HA-5101/883 tR tF tFtR 5 FN3931.1 August 17, 2005 HA-5101/883 Burn-in Circuits CERAMIC MINI-DIP 2 3 4 1 7 6 5 8 + - V+ V- D1C3C1 D2 C2 R1 CERAMIC LCC NOTES: R1 = 1MΩ, ±5%, 1/4W (Min) C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row, (Min) C3 = 0.01µF/Socket, 10% D1 = D2 = 1N4002 or Equivalent/Board (V+) - (V-) = 30V 6 FN3931.1 August 17, 2005 HA-5101/883 Schematic R24 Q24 R35 R37 Q37 R22 Q36 R36 Q35 Q21 R20 Q20 Q19A Q19B R19A R19B R11 R10 R25 R23 Q23 Q25 QL41 Q45 Q44 Q41 Q11 Q10 Q12 R12 Q33 Q32 Q31 Q46 QL2 Q2A Q2B Q30 Q38 Q29 Q43 Q1B Q1A QL1 Q26 R26 R34 Q5 Q4Q3 Q9 R3A Q39 R38R27 Q27 Q47 R60 R28 Q28 Q16 Q14 Q15 OUTPUT +IN R17A Q17 C1 C2 R58 Q8 Q18 Q48 Q51 Q42 Q13 R18 V- BAL BAL R15 Q50Q49 R4B R4A Q6 Q34 V+ Q7 -IN 3.65K 830 830 3.65K Q22 D2D1 8 8 7 FN3931.1 August 17, 2005 8 FN3931.1 August 17, 2005 Die Characteristics DIE DIMENSIONS 70 X 70 X 19 mils ±1mil 1790 x 1780 x 483µm ±25.4µm METALLIZATION Type: AI, 1% Cu Thickness: 16kÅ ±2kÅ GLASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ WORST CASE CURRENT DENSITY: 1.38 x 105A/cm2 SUBSTRATE POTENTIAL (Powered Up): V- TRANSISTOR COUNT: 54 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5101/883 BAL NC -IN +IN OUT V+ BALV- HA-5101/883 9 FN3931.1 August 17, 2005 HA-5101/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E S1 b2 b A e M c1 b1 (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa C A - BM DS S eA F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 N 8 8 8 Rev. 0 4/94 10 FN3931.1 August 17, 2005 HA-5101/883 Ceramic Leadless Chip Carrier Packages (CLCC) D j x 45o D3 B h x 45o A A1 E L L3 e B3 L1 D2 D1 e1 E2 E1 L2 PLANE 2 PLANE 1 E3 B2 0.010 E HS S 0.010 E FS S -E- 0.007 E FM S H S B1 -H- -F- J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE SYMBOL INCHES MILLIMETERS NOTESMIN MAX MIN MAX A 0.060 0.100 1.52 2.54 6, 7 A1 0.050 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 B2 0.072 REF 1.83 REF - B3 0.006 0.022 0.15 0.56 - D 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC - D2 0.100 BSC 2.54 BSC - D3 - 0.358 - 9.09 2 E 0.342 0.358 8.69 9.09 - E1 0.200 BSC 5.08 BSC - E2 0.100 BSC 2.54 BSC - E3 - 0.358 - 9.09 2 e 0.050 BSC 1.27 BSC - e1 0.015 - 0.38 - 2 h 0.040 REF 1.02 REF 5 j 0.020 REF 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 3 NE 5 5 3 N 20 20 3 Rev. 0 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 11 ® HA-5101 The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves Unless Otherwise Specified: VS = ±15V, TA = +25°C FIGURE 1. NOISE SPECTRUM FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE AV = 25,000, VS = ±15V (0.09nVP-P RTI) PEAK-TO-PEAK NOISE 0.1Hz TO 10Hz AV = 25,000, VS = ±15V (12.89mVP-P RTO or 0.52µVP-P RTI) PEAK-TO-PEAK TOTAL NOISE 0.1Hz TO 1MHz FREQUENCY (Hz) 10 100 1K 10K 100K 0 1 2 3 4 5 6 7 8 IN PU T N O IS E C U R R EN T (p A /√H z) IN PU T N O IS E VO LT A G E (n V/ √H z) VOLTAGE CURRENT TEMPERATURE (°C) 1251007550250-25-50 0 500 1000 1500 O FF SE T VO LT A G E (µV ) DESIGN INFORMATION Data Sheet August 17, 2005 FN3931.1 HA-5101 FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME (NORMALIZED TO ZERO FINAL VALUE) (SIX REPRESENTATIVE UNITS) FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE FIGURE 8. SHORT CIRCUIT CURRENT vs TIME Typical Performance Curves Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued) 0 20 -20 -40 -60 -55 -25 0 25 50 75 100 125 TEMPERATURE (°C) IN PU T O FF SE T C U R R EN T (n A ) 150 200 100 50 0 -55 -25 0 25 50 75 100 125 TEMPERATURE (°C) B IA S C U R R EN T (n A ) 250 450 500 TIME (s) 400350300250200150100500 -30 -20 -10 0 10 20 30 O FF SE T C H A N G E (µV ) MAXIMUM MINIMUM TYPICAL 20 SUPPLY VOLTAGE (±V) 181614121086420 0 1 2 3 4 5 SU PP LY C U R R EN T (m A ) 0.6 -60 -40 0 20 60 80 100 120 TEMPERATURE (°C) 40-20 0.7 0.8 0.9 1.0 1.1 RISE TIME SLEW RATE RL = 2K, CL = 50pF 0.6 0.7 0.8 0.9 1.0 1.1 SL EW R AT E (N O R M A LI ZE D ) R IS E TI M E (N O R M A LI ZE D ) 160140120100806040200 0 10 20 30 40 50 60 D B C A TIME (s) O U TP U T C U R R EN T (m A ) VIN VOUT A +15mV ±15V B -15mV ±15V C +15mV 0V D -15mV 0V 12 FN3931.1 August 17, 2005 HA-5101 FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE FIGURE 10. SETTLING WAVEFORM FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND LOW TEMPERATURES FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUENCY AT DIFFERENT CLOSED LOOP GAINS Typical Performance Curves Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued) 1510 185 SUPPLY VOLTAGE (±V) 10K (80) 100K (100) 1M (120) 10M (140) O PE N L O O P VO LT A G E G A IN V /V (d B ) VERROR 2.65µs 1mV TIME (1.5µs/DIV) AV = 1V/V RL = 2K, CL = 50pF 100M FREQUENCY (Hz) 10M1M100K10K -12 -9 -6 -3 0 3 6 -45 -90 -135 -180 PH A SE S H IF T (D EG R EE S) C LO SE D L O O P VO LT A G E G A IN (d B ) -55°C GAIN -225 125°C GAIN -55°C PHASE125°C PHASE 0 RL = 2K, CL = 50pF 100M FREQUENCY (Hz) 10M1M100K10K -20 -10 0 10 20 30 40 G A IN (d B ) AV = 10 AV = 100 AV = 1 13 FN3931.1 August 17, 2005 HA-5101 FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUENCY FIGURE 14. REJECTION RATIOS vs FREQUENCY FIGURE 15. SLEW RATE WAVEFORM FIGURE 16. SMALL SIGNAL WAVEFORM Typical Performance Curves Unless Otherwise Specified: VS = ±15V, TA = +25°C (Continued) 100M FREQUENCY (Hz) 10M1M100K10K1K10010 0 20 40 60 80 100 120 140 0 45 90 135 180 PH A SE S H IF T (D EG R EE S) VO LT A G E G A IN (d B ) GAIN PHASE -PSRR/CMRR +PSRR FREQUENCY (Hz) 100 1K 10K 100K 1M -120 -80 -100 -60 -40 R EJ EC TI O N R AT IO (d B ) VIN = VOUT = ±3V, AV = +1, RL = 2kΩ, CL = 50pF Timescale = 500ns/Div., Scale: Input = 5V/Div, Output = 2V/Div VIN = VOUT = 0V to +200mV, AV = +1, RL = 2K, CL = 50pF Timescale = 20ns/Div. Rise Time and Overshoot 14 FN3931.1 August 17, 2005 HA-5101 Applications Information Operation At ±5V Supply The HA-5101 performs well at VS = ±5V exhibiting typical characteristics as listed below: Input Protection The HA-5101 has built-in back-to-back protection diodes which will limit the differential input voltage to approximately 7V. If the HA-5101 will be used in conditions where that volt- age may be exceeded, then current limiting resistors must be used. No more than 25mA should be allowed to flow in the HA-5101’s input. Output Saturation When an op amp is overdriven, output devices can saturate and sometimes take a long time to recover. Saturation can be avoided (sometimes) by using circuits such as: If saturation cannot be avoided the HA-5101 recovers from a 25% overdrive in about 6.5µs (see photo). Offset Adjustment The following is the recommended VIO adjust configuration: NOTE: Proper decoupling is always recommended, 0.1µF high quality capacitor should be at or very near the device’s supply pins. Comparator Circuit Choose RLIM Such That: ICC . . . . . . . . . . . . . . . . . . . . .